Lines Matching defs:XX
3176 # define XX(_n) *p++ = (_n)
3178 case Xsse_MOV: /*movups*/ XX(0x0F); XX(0x10); break;
3179 case Xsse_OR: XX(0x0F); XX(0x56); break;
3180 case Xsse_XOR: XX(0x0F); XX(0x57); break;
3181 case Xsse_AND: XX(0x0F); XX(0x54); break;
3182 case Xsse_PACKSSD: XX(0x66); XX(0x0F); XX(0x6B); break;
3183 case Xsse_PACKSSW: XX(0x66); XX(0x0F); XX(0x63); break;
3184 case Xsse_PACKUSW: XX(0x66); XX(0x0F); XX(0x67); break;
3185 case Xsse_ADD8: XX(0x66); XX(0x0F); XX(0xFC); break;
3186 case Xsse_ADD16: XX(0x66); XX(0x0F); XX(0xFD); break;
3187 case Xsse_ADD32: XX(0x66); XX(0x0F); XX(0xFE); break;
3188 case Xsse_ADD64: XX(0x66); XX(0x0F); XX(0xD4); break;
3189 case Xsse_QADD8S: XX(0x66); XX(0x0F); XX(0xEC); break;
3190 case Xsse_QADD16S: XX(0x66); XX(0x0F); XX(0xED); break;
3191 case Xsse_QADD8U: XX(0x66); XX(0x0F); XX(0xDC); break;
3192 case Xsse_QADD16U: XX(0x66); XX(0x0F); XX(0xDD); break;
3193 case Xsse_AVG8U: XX(0x66); XX(0x0F); XX(0xE0); break;
3194 case Xsse_AVG16U: XX(0x66); XX(0x0F); XX(0xE3); break;
3195 case Xsse_CMPEQ8: XX(0x66); XX(0x0F); XX(0x74); break;
3196 case Xsse_CMPEQ16: XX(0x66); XX(0x0F); XX(0x75); break;
3197 case Xsse_CMPEQ32: XX(0x66); XX(0x0F); XX(0x76); break;
3198 case Xsse_CMPGT8S: XX(0x66); XX(0x0F); XX(0x64); break;
3199 case Xsse_CMPGT16S: XX(0x66); XX(0x0F); XX(0x65); break;
3200 case Xsse_CMPGT32S: XX(0x66); XX(0x0F); XX(0x66); break;
3201 case Xsse_MAX16S: XX(0x66); XX(0x0F); XX(0xEE); break;
3202 case Xsse_MAX8U: XX(0x66); XX(0x0F); XX(0xDE); break;
3203 case Xsse_MIN16S: XX(0x66); XX(0x0F); XX(0xEA); break;
3204 case Xsse_MIN8U: XX(0x66); XX(0x0F); XX(0xDA); break;
3205 case Xsse_MULHI16U: XX(0x66); XX(0x0F); XX(0xE4); break;
3206 case Xsse_MULHI16S: XX(0x66); XX(0x0F); XX(0xE5); break;
3207 case Xsse_MUL16: XX(0x66); XX(0x0F); XX(0xD5); break;
3208 case Xsse_SHL16: XX(0x66); XX(0x0F); XX(0xF1); break;
3209 case Xsse_SHL32: XX(0x66); XX(0x0F); XX(0xF2); break;
3210 case Xsse_SHL64: XX(0x66); XX(0x0F); XX(0xF3); break;
3211 case Xsse_SAR16: XX(0x66); XX(0x0F); XX(0xE1); break;
3212 case Xsse_SAR32: XX(0x66); XX(0x0F); XX(0xE2); break;
3213 case Xsse_SHR16: XX(0x66); XX(0x0F); XX(0xD1); break;
3214 case Xsse_SHR32: XX(0x66); XX(0x0F); XX(0xD2); break;
3215 case Xsse_SHR64: XX(0x66); XX(0x0F); XX(0xD3); break;
3216 case Xsse_SUB8: XX(0x66); XX(0x0F); XX(0xF8); break;
3217 case Xsse_SUB16: XX(0x66); XX(0x0F); XX(0xF9); break;
3218 case Xsse_SUB32: XX(0x66); XX(0x0F); XX(0xFA); break;
3219 case Xsse_SUB64: XX(0x66); XX(0x0F); XX(0xFB); break;
3220 case Xsse_QSUB8S: XX(0x66); XX(0x0F); XX(0xE8); break;
3221 case Xsse_QSUB16S: XX(0x66); XX(0x0F); XX(0xE9); break;
3222 case Xsse_QSUB8U: XX(0x66); XX(0x0F); XX(0xD8); break;
3223 case Xsse_QSUB16U: XX(0x66); XX(0x0F); XX(0xD9); break;
3224 case Xsse_UNPCKHB: XX(0x66); XX(0x0F); XX(0x68); break;
3225 case Xsse_UNPCKHW: XX(0x66); XX(0x0F); XX(0x69); break;
3226 case Xsse_UNPCKHD: XX(0x66); XX(0x0F); XX(0x6A); break;
3227 case Xsse_UNPCKHQ: XX(0x66); XX(0x0F); XX(0x6D); break;
3228 case Xsse_UNPCKLB: XX(0x66); XX(0x0F); XX(0x60); break;
3229 case Xsse_UNPCKLW: XX(0x66); XX(0x0F); XX(0x61); break;
3230 case Xsse_UNPCKLD: XX(0x66); XX(0x0F); XX(0x62); break;
3231 case Xsse_UNPCKLQ: XX(0x66); XX(0x0F); XX(0x6C); break;
3236 # undef XX
