Lines Matching refs:instr_offset
859 idx, CLG_(bb_base) + current_ii->instr_offset, memline);
876 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset;
947 cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
967 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \
1068 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
1071 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes));
1093 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);
1095 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);
1098 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
1099 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) );
1126 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);
1128 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);
1130 Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size);
1133 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
1134 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res),
1135 CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) );
1165 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
1169 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),
1228 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
1232 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),
