Lines Matching defs:tst
74 static void setup_sigcontext ( ThreadState* tst, struct vki_sigcontext **sc1,
79 VG_TRACK(pre_mem_write, Vg_CoreSignal, tst->tid, "signal frame mcontext",
81 sc->sc_regs[1] = tst->arch.vex.guest_r1;
82 sc->sc_regs[2] = tst->arch.vex.guest_r2;
83 sc->sc_regs[3] = tst->arch.vex.guest_r3;
84 sc->sc_regs[4] = tst->arch.vex.guest_r4;
85 sc->sc_regs[5] = tst->arch.vex.guest_r5;
86 sc->sc_regs[6] = tst->arch.vex.guest_r6;
87 sc->sc_regs[7] = tst->arch.vex.guest_r7;
88 sc->sc_regs[8] = tst->arch.vex.guest_r8;
89 sc->sc_regs[9] = tst->arch.vex.guest_r9;
90 sc->sc_regs[10] = tst->arch.vex.guest_r10;
91 sc->sc_regs[11] = tst->arch.vex.guest_r11;
92 sc->sc_regs[12] = tst->arch.vex.guest_r12;
93 sc->sc_regs[13] = tst->arch.vex.guest_r13;
94 sc->sc_regs[14] = tst->arch.vex.guest_r14;
95 sc->sc_regs[15] = tst->arch.vex.guest_r15;
96 sc->sc_regs[16] = tst->arch.vex.guest_r16;
97 sc->sc_regs[17] = tst->arch.vex.guest_r17;
98 sc->sc_regs[18] = tst->arch.vex.guest_r18;
99 sc->sc_regs[19] = tst->arch.vex.guest_r19;
100 sc->sc_regs[20] = tst->arch.vex.guest_r20;
101 sc->sc_regs[21] = tst->arch.vex.guest_r21;
102 sc->sc_regs[22] = tst->arch.vex.guest_r22;
103 sc->sc_regs[23] = tst->arch.vex.guest_r23;
104 sc->sc_regs[24] = tst->arch.vex.guest_r24;
105 sc->sc_regs[25] = tst->arch.vex.guest_r25;
106 sc->sc_regs[26] = tst->arch.vex.guest_r26;
107 sc->sc_regs[27] = tst->arch.vex.guest_r27;
108 sc->sc_regs[28] = tst->arch.vex.guest_r28;
109 sc->sc_regs[29] = tst->arch.vex.guest_r29;
110 sc->sc_regs[30] = tst->arch.vex.guest_r30;
111 sc->sc_regs[31] = tst->arch.vex.guest_r31;
112 sc->sc_pc = tst->arch.vex.guest_PC;
113 sc->sc_mdhi = tst->arch.vex.guest_HI;
114 sc->sc_mdlo = tst->arch.vex.guest_LO;
128 ThreadState* tst = VG_(get_ThreadState)(tid);
136 tst = VG_(get_ThreadState)(tid);
137 if (! ML_(sf_maybe_extend_stack)(tst, sp, sp_top_of_frame - sp, flags))
161 ucp->uc_stack = tst->altstack;
167 setup_sigcontext(tst, &(scp), siginfo);
168 ucp->uc_sigmask = tst->sig_mask;
180 tst->arch.vex.guest_r4 = siginfo->si_signo;
181 tst->arch.vex.guest_r5 = (Addr) &frame->rs_info;
182 tst->arch.vex.guest_r6 = (Addr) &frame->rs_uc;
183 tst->arch.vex.guest_r29 = (Addr) frame;
184 tst->arch.vex.guest_r25 = (Addr) handler;
187 tst->arch.vex.guest_r31 = (Addr) restorer;
189 tst->arch.vex.guest_r31 = (Addr)&VG_(mips64_linux_SUBST_FOR_rt_sigreturn);
193 priv->vex_shadow1 = tst->arch.vex_shadow1;
194 priv->vex_shadow2 = tst->arch.vex_shadow2;
199 tst->arch.vex.guest_PC = (Addr) handler;
207 ThreadState *tst;
215 tst = VG_(get_ThreadState)(tid);
216 sp = tst->arch.vex.guest_r29;
221 tst->sig_mask = ucp->uc_sigmask;
222 tst->tmp_sig_mask = ucp->uc_sigmask;
227 tst->arch.vex.guest_r1 = mc->sc_regs[1];
228 tst->arch.vex.guest_r2 = mc->sc_regs[2];
229 tst->arch.vex.guest_r3 = mc->sc_regs[3];
230 tst->arch.vex.guest_r4 = mc->sc_regs[4];
231 tst->arch.vex.guest_r5 = mc->sc_regs[5];
232 tst->arch.vex.guest_r6 = mc->sc_regs[6];
233 tst->arch.vex.guest_r7 = mc->sc_regs[7];
234 tst->arch.vex.guest_r8 = mc->sc_regs[8];
235 tst->arch.vex.guest_r9 = mc->sc_regs[9];
236 tst->arch.vex.guest_r10 = mc->sc_regs[10];
237 tst->arch.vex.guest_r11 = mc->sc_regs[11];
238 tst->arch.vex.guest_r12 = mc->sc_regs[12];
239 tst->arch.vex.guest_r13= mc->sc_regs[13];
240 tst->arch.vex.guest_r14 = mc->sc_regs[14];
241 tst->arch.vex.guest_r15 = mc->sc_regs[15];
242 tst->arch.vex.guest_r16 = mc->sc_regs[16];
243 tst->arch.vex.guest_r17 = mc->sc_regs[17];
244 tst->arch.vex.guest_r18 = mc->sc_regs[18];
245 tst->arch.vex.guest_r19 = mc->sc_regs[19];
246 tst->arch.vex.guest_r20 = mc->sc_regs[20];
247 tst->arch.vex.guest_r21 = mc->sc_regs[21];
248 tst->arch.vex.guest_r22 = mc->sc_regs[22];
249 tst->arch.vex.guest_r23 = mc->sc_regs[23];
250 tst->arch.vex.guest_r24 = mc->sc_regs[24];
251 tst->arch.vex.guest_r25 = mc->sc_regs[25];
252 tst->arch.vex.guest_r26 = mc->sc_regs[26];
253 tst->arch.vex.guest_r27 = mc->sc_regs[27];
254 tst->arch.vex.guest_r28 = mc->sc_regs[28];
255 tst->arch.vex.guest_r30 = mc->sc_regs[30];
256 tst->arch.vex.guest_PC = mc->sc_pc;
257 tst->arch.vex.guest_r31 = mc->sc_regs[31];
258 tst->arch.vex.guest_r29 = mc->sc_regs[29];
260 tst->arch.vex.guest_HI = mc->sc_mdhi;
261 tst->arch.vex.guest_LO = mc->sc_mdlo;
262 tst->arch.vex_shadow1 = priv1->vex_shadow1;
263 tst->arch.vex_shadow2 = priv1->vex_shadow2;
269 tid, isRT, tst->arch.vex.guest_PC);
