Lines Matching refs:srcStep
61 srcStep RN 1
118 M_LDR ValC, [pSrc], srcStep ;// Load [c3 c2 c1 c0]
119 M_LDR ValD, [pSrc], srcStep ;// Load [d3 d2 d1 d0]
120 M_LDR ValE, [pSrc], srcStep ;// Load [e3 e2 e1 e0]
121 SUB pSrc, pSrc, srcStep, LSL #2
133 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0]
140 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0]
141 M_LDR ValB, [pSrc], srcStep ;// Load [b3 b2 b1 b0]
148 SUB ValA, pSrc, srcStep, LSL #1
161 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0]
186 ADD pSrc, pSrc, srcStep, LSL #1
192 SUB pSrc, pSrc, srcStep, LSL #2
