Lines Matching refs:srcStep
40 srcStep RN 1
87 VLD1 dSrc0, [pSrc], srcStep ;// [a0 a1 a2 a3 .. ]
88 ADD Temp, pSrc, srcStep, LSL #2
89 VLD1 dSrc1, [pSrc], srcStep ;// [b0 b1 b2 b3 .. ]
91 VLD1 dSrc5, [Temp], srcStep
93 VLD1 dSrc2, [pSrc], srcStep ;// [c0 c1 c2 c3 .. ]
95 VLD1 dSrc3, [pSrc], srcStep
97 VLD1 dSrc6, [Temp], srcStep ;// TeRi
99 VLD1 dSrc4, [pSrc], srcStep
100 VLD1 dSrc7, [Temp], srcStep ;// TeRi
103 VLD1 dSrc8, [Temp], srcStep ;// TeRi
108 ; VLD1 dSrc6, [Temp], srcStep
116 ; VLD1 dSrc7, [Temp], srcStep
124 ; VLD1 dSrc8, [Temp], srcStep ;// [i0 i1 i2 i3 .. ]
