Lines Matching refs:dRow0
64 VLD1 dRow0, [pSrc], srcStep
73 VST1 dRow0, [pDst@64], dstStep
111 VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep
112 VEXT dRow0Shft, dRow0, dRow0Shft, #1
127 $M_VHADDR dRow0, dRow0, dRow0Shft
129 VST1 dRow0, [pDst@64], dstStep
172 VLD1 dRow0, [pSrc], srcStep
180 $M_VHADDR dRow0, dRow0, dRow1
183 VST1 dRow0, [pDst@64], dstStep
205 ;// 1. VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep ;// Load the row and next 8 bytes
206 ;// 2. VEXT dRow0Shft, dRow0, dRow0Shft, #1 ;// Generate the shifted row
207 ;// 3. VADDL qSum0, dRow0, dRow0Shft ;// Generate the sum of row and shifted row
209 ;// 6. VSHRN dRow0, qSum0, #2 ;// Divide by 4
210 ;// 7. VST1 dRow0, [pDst@64], dstStep ;// Store
233 VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep
236 VEXT dRow0Shft, dRow0, dRow0Shft, #1
242 VADDL qSum0, dRow0, dRow0Shft
257 VSHRN dRow0, qSum0, #2
262 VST1 dRow0, [pDst@64], dstStep
307 dRow0 DN D0.U8
