Lines Matching refs:mv_fields
677 #define P5(x) psb__trace_message("PARAMS: " #x "\t= %d\n", p->mv_fields.bits.x)
891 ctx->mv_mode = pic_params->mv_fields.bits.mv_mode;
893 ctx->mv_mode = pic_params->mv_fields.bits.mv_mode2;
900 if ((pic_params->picture_fields.bits.picture_type == WMF_PTYPE_P) && (pic_params->mv_fields.bits.four_mv_switch == 1)) {
902 pic_params->mv_fields.bits.mv_mode = WMF_MVMODE_MIXED_MV;
905 pic_params->mv_fields.bits.mv_mode = WMF_MVMODE_1MV;
923 if (pic_params->mv_fields.bits.extended_dmv_flag == 1) {
924 ctx->extend_x = gDMVRANGE_ExtHorizontal_RemapTable[pic_params->mv_fields.bits.extended_dmv_range];
925 ctx->extend_y = gDMVRANGE_ExtVertical_RemapTable[pic_params->mv_fields.bits.extended_dmv_range];
1402 psb__bounds_check(pic_params->mv_fields.bits.four_mv_block_pattern_table, 4);
1403 ui16Table = FourMVTable[pic_params->mv_fields.bits.four_mv_block_pattern_table];
1419 psb__bounds_check(pic_params->mv_fields.bits.two_mv_block_pattern_table, 4);
1420 ui16Table = Interlace2MVTable[pic_params->mv_fields.bits.two_mv_block_pattern_table];
1469 psb__bounds_check(pic_params->mv_fields.bits.mv_table, 4);
1470 ui16Table = ProgressiveMVTable[pic_params->mv_fields.bits.mv_table];
1485 psb__bounds_check(pic_params->mv_fields.bits.mv_table, 4);
1486 ui16Table = Interlaced1RefMVTable[pic_params->mv_fields.bits.mv_table];
1489 psb__bounds_check(pic_params->mv_fields.bits.mv_table, 8);
1490 ui16Table = MVTable2RefIlace[pic_params->mv_fields.bits.mv_table]; /* LUT */
1512 ui16Table = MBMODETableFLDI[pic_params->mb_mode_table][(pic_params->mv_fields.bits.mv_mode == WMF_MVMODE_MIXED_MV) ? 1 : 0];
1516 ui16Table = MBMODETableFRMI[pic_params->mb_mode_table][(pic_params->mv_fields.bits.four_mv_switch) ? 0 : 1];
2115 REGIO_WRITE_FIELD(cmd, MSVDX_VEC_VC1, CR_VEC_VC1_BE_SPS0, VC1_BE_EXTENDED_DMV, pic_params->mv_fields.bits.extended_dmv_flag);
2116 REGIO_WRITE_FIELD(cmd, MSVDX_VEC_VC1, CR_VEC_VC1_BE_SPS0, VC1_BE_EXTENDED_MV, pic_params->mv_fields.bits.extended_mv_flag);
2173 REGIO_WRITE_FIELD(cmd, MSVDX_VEC_VC1, CR_VEC_VC1_BE_PPS1, VC1_BE_MVMODE, pic_params->mv_fields.bits.mv_mode);
2174 REGIO_WRITE_FIELD(cmd, MSVDX_VEC_VC1, CR_VEC_VC1_BE_PPS1, VC1_BE_MVMODE2, pic_params->mv_fields.bits.mv_mode2);
2215 REGIO_WRITE_FIELD(cmd, MSVDX_VEC_VC1, CR_VEC_VC1_BE_MVD5, VC1_BE_MVRANGE, pic_params->mv_fields.bits.extended_mv_range);
2368 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VC1, CR_VEC_VC1_FE_PPS1, VC1_FE_MVMODE, pic_params->mv_fields.bits.mv_mode);
2369 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VC1, CR_VEC_VC1_FE_PPS1, VC1_FE_MVMODE2, pic_params->mv_fields.bits.mv_mode2);
2423 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VC1, CR_VEC_VC1_FE_MVD_LITE1, VC1_FE_MVRANGE, pic_params->mv_fields.bits.extended_mv_range);
2473 pParseHeaderCMD->ui32SeqHdrData = (pic_params->mv_fields.bits.extended_dmv_flag) << VC1_SEQHDR_EXTENDED_DMV;
2500 pParseHeaderCMD->ui32SeqHdrData |= (pic_params->mv_fields.bits.extended_mv_flag) << VC1_SEQHDR_EXTENDED_MV;
