Home | History | Annotate | Download | only in lib

Lines Matching full:rsubhn2

3052 T?C T?C T?C 
T?C ? @/tmp/AOSP-toolchain/build/../binutils/binutils-2.24/opcodes/aarch64-opc.cqseq_list[0][known_idx] == AARCH64_OPND_NILoperand_variant_qualifier_p (qualifier) == 1opcode->operands[idx] == opnd->type && opnd->type == typeidx == 1 && (aarch64_get_operand_class (opnds[0].type) == AARCH64_OPND_CLASS_SYSTEM)stack pointer register expectednegative or unaligned offset expected/tmp/AOSP-toolchain/build/../binutils/binutils-2.24/opcodes/aarch64-opc.hls[size - 1] != (unsigned char)-1shift amount expected to be 0 or 12idx == 1 && opnds[0].type == AARCH64_OPND_Rdshift amount should be a multiple of 16negative immediate value not allowedidx == 3 && opnds[idx-1].type == AARCH64_OPND_IMM && opnds[0].type == AARCH64_OPND_Rdqualifier_value_in_range_constraint_p (qualifier) == 1shift amount expected to be 0 or 16floating-point immediate expectedidx == 0 && opnds[1].type == AARCH64_OPND_UIMM4opnd->shifter.operator_present || opnd->shifter.kind == AARCH64_MOD_LSLopnd->qualifier == AARCH64_OPND_QLF_W || opnd->qualifier == AARCH64_OPND_QLF_Xopnd->qualifier == AARCH64_OPND_QLF_W || opnd->qualifier == AARCH64_OPND_QLF_WSP || opnd->qualifier == AARCH64_OPND_QLF_X || opnd->qualifier == AARCH64_OPND_QLF_SPopnd->type != AARCH64_OPND_LEt || opnd->reglist.has_indexnum_regs >= 1 && num_regs <= 4{v%d.%s, v%d.%s, v%d.%s, v%d.%s}%s0,%s #%d[%s,%c%d%s],%svalue < 16i >= 0 && i <= 6nb_imms == 5334extraneous registermissing registerunexpected address writebackaddress writeback expectedopnd->addr.writeback == 0immediate offsetidx == 1invalid register offsetinvalid post-increment amountinvalid shift amountinvalid extend/shift operatorwidth > 0 && width < 32immediate out of rangenum >= 1 && num <= 4immediate valueinvalid shift operatorshift amountimmediate zero expectedidx == 2shift is not permittedinvalid value for immediateregister numberregister element indexidx == 1 || idx == 2extend operator expectedmissing extend operator'LSL' operator not allowedW register expectedshift operator expected'ROR' operator not allowedspsr_el1spsel%s%s, %s #%d%s, %s%s%dv%d.%sv%d.%s[%d]v%d.d[1][%d]{v%d.%s-v%d.%s}%s{v%d.%s}%s{v%d.%s, v%d.%s}%s{v%d.%s, v%d.%s, v%d.%s}%sC%d#%li#0x%-20x	// #%d#0x%-20lx	// #%li#0.0#0x%lx, lsl #%d#0x%lx#0x%lx, %s #%d#%.18e#0x%x[%s], x%d[%s], #%d[%s][%s,#%d]![%s],#%d[%s,#%d]s%u_%u_c%u_c%u_%u#0x%02xaarch64_pstatefields[i].nameadcadcssbcngcsbcsngcsaddaddscmnsubsubscmpmovnegnegssaddlvsmaxvsminvaddvuaddlvumaxvuminvfmaxnmvfmaxvfminnmvfminvsaddlsaddl2saddwsaddw2ssublssubl2ssubwssubw2addhnaddhn2sabalsabal2subhnsubhn2sabdlsabdl2smlalsmlal2sqdmlalsqdmlal2smlslsmlsl2sqdmlslsqdmlsl2smullsmull2sqdmullsqdmull2pmullpmull2uaddluaddl2uaddwuaddw2usublusubl2usubwusubw2raddhnraddhn2uabaluabal2rsubhnrsubhn2