Cross Reference: /system/core/libpixelflinger/codeflinger/Arm64Assembler.cpp

Lines Matching refs:mZeroReg

172     mZeroReg = 13;
184     mZeroReg = 13;
289     *mPC++ = A64_MOVZ_X(mZeroReg,0,0);
429         dataProcessingCommon(opSUB, s, Wd, mZeroReg, Wd);
433         dataProcessingCommon(opORR, 0, Wd, mZeroReg, Op2);
436             dataProcessingCommon(opSUB, 1, mTmpReg3, Wd, mZeroReg);
441         dataProcessingCommon(opMVN, s, Wd, mZeroReg, Op2);
445         dataProcessingCommon(opMVN, s, mTmpReg3, mZeroReg, Op2);
506         *mPC++ = A64_ADD_W(mTmpReg1, mZeroReg, mAddrMode.reg_imm_Rm,
525         dataProcessingCommon(opSUB, 1, mTmpReg1, Rd, mZeroReg);
531     *mPC++ = A64_MADD_W(Rd, Rm, Rs, mZeroReg);
589             *mPC++ = A64_ADD_IMM_X(mTmpReg1, mZeroReg, imm, 0);
591             *mPC++ = A64_SUB_IMM_X(mTmpReg1, mZeroReg, -imm, 0);
609         *mPC++ = A64_LDRSTR_Wm_SXTW_0(op, size, Rd, addrReg, mZeroReg);
625         *mPC++ = A64_LDRSTR_Wm_SXTW_0(op, size, Rd, Rn, mZeroReg);
789     *mPC++ = A64_MADD_W(Rd,mTmpReg1,mTmpReg2, mZeroReg);
804     *mPC++ = A64_SMADDL(mTmpReg3,mTmpReg1,mTmpReg2, mZeroReg);

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