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      1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation  ------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the interfaces that BPF uses to lower LLVM code into a
     11 // selection DAG.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "BPFISelLowering.h"
     16 #include "BPF.h"
     17 #include "BPFTargetMachine.h"
     18 #include "BPFSubtarget.h"
     19 #include "llvm/CodeGen/CallingConvLower.h"
     20 #include "llvm/CodeGen/MachineFrameInfo.h"
     21 #include "llvm/CodeGen/MachineFunction.h"
     22 #include "llvm/CodeGen/MachineInstrBuilder.h"
     23 #include "llvm/CodeGen/MachineRegisterInfo.h"
     24 #include "llvm/CodeGen/SelectionDAGISel.h"
     25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
     26 #include "llvm/CodeGen/ValueTypes.h"
     27 #include "llvm/Support/CommandLine.h"
     28 #include "llvm/Support/Debug.h"
     29 #include "llvm/Support/ErrorHandling.h"
     30 #include "llvm/Support/raw_ostream.h"
     31 #include "llvm/IR/DiagnosticInfo.h"
     32 #include "llvm/IR/DiagnosticPrinter.h"
     33 using namespace llvm;
     34 
     35 #define DEBUG_TYPE "bpf-lower"
     36 
     37 namespace {
     38 
     39 // Diagnostic information for unimplemented or unsupported feature reporting.
     40 class DiagnosticInfoUnsupported : public DiagnosticInfo {
     41 private:
     42   // Debug location where this diagnostic is triggered.
     43   DebugLoc DLoc;
     44   const Twine &Description;
     45   const Function &Fn;
     46   SDValue Value;
     47 
     48   static int KindID;
     49 
     50   static int getKindID() {
     51     if (KindID == 0)
     52       KindID = llvm::getNextAvailablePluginDiagnosticKind();
     53     return KindID;
     54   }
     55 
     56 public:
     57   DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
     58                             SDValue Value)
     59       : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
     60         Description(Desc), Fn(Fn), Value(Value) {}
     61 
     62   void print(DiagnosticPrinter &DP) const override {
     63     std::string Str;
     64     raw_string_ostream OS(Str);
     65 
     66     if (DLoc) {
     67       auto DIL = DLoc.get();
     68       StringRef Filename = DIL->getFilename();
     69       unsigned Line = DIL->getLine();
     70       unsigned Column = DIL->getColumn();
     71       OS << Filename << ':' << Line << ':' << Column << ' ';
     72     }
     73 
     74     OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
     75        << Description;
     76     if (Value)
     77       Value->print(OS);
     78     OS << '\n';
     79     OS.flush();
     80     DP << Str;
     81   }
     82 
     83   static bool classof(const DiagnosticInfo *DI) {
     84     return DI->getKind() == getKindID();
     85   }
     86 };
     87 
     88 int DiagnosticInfoUnsupported::KindID = 0;
     89 }
     90 
     91 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
     92                                      const BPFSubtarget &STI)
     93     : TargetLowering(TM) {
     94 
     95   // Set up the register classes.
     96   addRegisterClass(MVT::i64, &BPF::GPRRegClass);
     97 
     98   // Compute derived properties from the register classes
     99   computeRegisterProperties(STI.getRegisterInfo());
    100 
    101   setStackPointerRegisterToSaveRestore(BPF::R11);
    102 
    103   setOperationAction(ISD::BR_CC, MVT::i64, Custom);
    104   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
    105   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
    106   setOperationAction(ISD::SETCC, MVT::i64, Expand);
    107   setOperationAction(ISD::SELECT, MVT::i64, Expand);
    108   setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
    109 
    110   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
    111 
    112   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
    113   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
    114   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
    115 
    116   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
    117   setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
    118   setOperationAction(ISD::SREM, MVT::i64, Expand);
    119   setOperationAction(ISD::UREM, MVT::i64, Expand);
    120 
    121   setOperationAction(ISD::MULHU, MVT::i64, Expand);
    122   setOperationAction(ISD::MULHS, MVT::i64, Expand);
    123   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
    124   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
    125 
    126   setOperationAction(ISD::ADDC, MVT::i64, Expand);
    127   setOperationAction(ISD::ADDE, MVT::i64, Expand);
    128   setOperationAction(ISD::SUBC, MVT::i64, Expand);
    129   setOperationAction(ISD::SUBE, MVT::i64, Expand);
    130 
    131   // no UNDEF allowed
    132   setOperationAction(ISD::UNDEF, MVT::i64, Expand);
    133 
    134   setOperationAction(ISD::ROTR, MVT::i64, Expand);
    135   setOperationAction(ISD::ROTL, MVT::i64, Expand);
    136   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
    137   setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
    138   setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
    139 
    140   setOperationAction(ISD::CTTZ, MVT::i64, Custom);
    141   setOperationAction(ISD::CTLZ, MVT::i64, Custom);
    142   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
    143   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
    144   setOperationAction(ISD::CTPOP, MVT::i64, Expand);
    145 
    146   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
    147   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
    148   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
    149   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
    150 
    151   // Extended load operations for i1 types must be promoted
    152   for (MVT VT : MVT::integer_valuetypes()) {
    153     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
    154     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
    155     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
    156 
    157     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
    158     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
    159     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
    160   }
    161 
    162   setBooleanContents(ZeroOrOneBooleanContent);
    163 
    164   // Function alignments (log2)
    165   setMinFunctionAlignment(3);
    166   setPrefFunctionAlignment(3);
    167 
    168   // inline memcpy() for kernel to see explicit copy
    169   MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128;
    170   MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128;
    171   MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128;
    172 }
    173 
    174 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
    175   switch (Op.getOpcode()) {
    176   case ISD::BR_CC:
    177     return LowerBR_CC(Op, DAG);
    178   case ISD::GlobalAddress:
    179     return LowerGlobalAddress(Op, DAG);
    180   case ISD::SELECT_CC:
    181     return LowerSELECT_CC(Op, DAG);
    182   default:
    183     llvm_unreachable("unimplemented operand");
    184   }
    185 }
    186 
    187 // Calling Convention Implementation
    188 #include "BPFGenCallingConv.inc"
    189 
    190 SDValue BPFTargetLowering::LowerFormalArguments(
    191     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
    192     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
    193     SmallVectorImpl<SDValue> &InVals) const {
    194   switch (CallConv) {
    195   default:
    196     llvm_unreachable("Unsupported calling convention");
    197   case CallingConv::C:
    198   case CallingConv::Fast:
    199     break;
    200   }
    201 
    202   MachineFunction &MF = DAG.getMachineFunction();
    203   MachineRegisterInfo &RegInfo = MF.getRegInfo();
    204 
    205   // Assign locations to all of the incoming arguments.
    206   SmallVector<CCValAssign, 16> ArgLocs;
    207   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
    208   CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
    209 
    210   for (auto &VA : ArgLocs) {
    211     if (VA.isRegLoc()) {
    212       // Arguments passed in registers
    213       EVT RegVT = VA.getLocVT();
    214       switch (RegVT.getSimpleVT().SimpleTy) {
    215       default: {
    216         errs() << "LowerFormalArguments Unhandled argument type: "
    217                << RegVT.getSimpleVT().SimpleTy << '\n';
    218         llvm_unreachable(0);
    219       }
    220       case MVT::i64:
    221         unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
    222         RegInfo.addLiveIn(VA.getLocReg(), VReg);
    223         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
    224 
    225         // If this is an 8/16/32-bit value, it is really passed promoted to 64
    226         // bits. Insert an assert[sz]ext to capture this, then truncate to the
    227         // right size.
    228         if (VA.getLocInfo() == CCValAssign::SExt)
    229           ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
    230                                  DAG.getValueType(VA.getValVT()));
    231         else if (VA.getLocInfo() == CCValAssign::ZExt)
    232           ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
    233                                  DAG.getValueType(VA.getValVT()));
    234 
    235         if (VA.getLocInfo() != CCValAssign::Full)
    236           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
    237 
    238         InVals.push_back(ArgValue);
    239       }
    240     } else {
    241       DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
    242                                     "defined with too many args", SDValue());
    243       DAG.getContext()->diagnose(Err);
    244     }
    245   }
    246 
    247   if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
    248     DiagnosticInfoUnsupported Err(
    249         DL, *MF.getFunction(),
    250         "functions with VarArgs or StructRet are not supported", SDValue());
    251     DAG.getContext()->diagnose(Err);
    252   }
    253 
    254   return Chain;
    255 }
    256 
    257 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
    258                                      SmallVectorImpl<SDValue> &InVals) const {
    259   SelectionDAG &DAG = CLI.DAG;
    260   auto &Outs = CLI.Outs;
    261   auto &OutVals = CLI.OutVals;
    262   auto &Ins = CLI.Ins;
    263   SDValue Chain = CLI.Chain;
    264   SDValue Callee = CLI.Callee;
    265   bool &IsTailCall = CLI.IsTailCall;
    266   CallingConv::ID CallConv = CLI.CallConv;
    267   bool IsVarArg = CLI.IsVarArg;
    268   MachineFunction &MF = DAG.getMachineFunction();
    269 
    270   // BPF target does not support tail call optimization.
    271   IsTailCall = false;
    272 
    273   switch (CallConv) {
    274   default:
    275     report_fatal_error("Unsupported calling convention");
    276   case CallingConv::Fast:
    277   case CallingConv::C:
    278     break;
    279   }
    280 
    281   // Analyze operands of the call, assigning locations to each operand.
    282   SmallVector<CCValAssign, 16> ArgLocs;
    283   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
    284 
    285   CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
    286 
    287   unsigned NumBytes = CCInfo.getNextStackOffset();
    288 
    289   if (Outs.size() >= 6) {
    290     DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
    291                                   "too many args to ", Callee);
    292     DAG.getContext()->diagnose(Err);
    293   }
    294 
    295   for (auto &Arg : Outs) {
    296     ISD::ArgFlagsTy Flags = Arg.Flags;
    297     if (!Flags.isByVal())
    298       continue;
    299 
    300     DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
    301                                   "pass by value not supported ", Callee);
    302     DAG.getContext()->diagnose(Err);
    303   }
    304 
    305   Chain = DAG.getCALLSEQ_START(
    306       Chain, DAG.getConstant(NumBytes, getPointerTy(), true), CLI.DL);
    307 
    308   SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass;
    309 
    310   // Walk arg assignments
    311   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
    312     CCValAssign &VA = ArgLocs[i];
    313     SDValue Arg = OutVals[i];
    314 
    315     // Promote the value if needed.
    316     switch (VA.getLocInfo()) {
    317     default:
    318       llvm_unreachable("Unknown loc info");
    319     case CCValAssign::Full:
    320       break;
    321     case CCValAssign::SExt:
    322       Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
    323       break;
    324     case CCValAssign::ZExt:
    325       Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
    326       break;
    327     case CCValAssign::AExt:
    328       Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
    329       break;
    330     }
    331 
    332     // Push arguments into RegsToPass vector
    333     if (VA.isRegLoc())
    334       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
    335     else
    336       llvm_unreachable("call arg pass bug");
    337   }
    338 
    339   SDValue InFlag;
    340 
    341   // Build a sequence of copy-to-reg nodes chained together with token chain and
    342   // flag operands which copy the outgoing args into registers.  The InFlag in
    343   // necessary since all emitted instructions must be stuck together.
    344   for (auto &Reg : RegsToPass) {
    345     Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
    346     InFlag = Chain.getValue(1);
    347   }
    348 
    349   // If the callee is a GlobalAddress node (quite common, every direct call is)
    350   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
    351   // Likewise ExternalSymbol -> TargetExternalSymbol.
    352   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
    353     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, getPointerTy(),
    354                                         G->getOffset(), 0);
    355   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
    356     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), 0);
    357 
    358   // Returns a chain & a flag for retval copy to use.
    359   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
    360   SmallVector<SDValue, 8> Ops;
    361   Ops.push_back(Chain);
    362   Ops.push_back(Callee);
    363 
    364   // Add argument registers to the end of the list so that they are
    365   // known live into the call.
    366   for (auto &Reg : RegsToPass)
    367     Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
    368 
    369   if (InFlag.getNode())
    370     Ops.push_back(InFlag);
    371 
    372   Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
    373   InFlag = Chain.getValue(1);
    374 
    375   // Create the CALLSEQ_END node.
    376   Chain = DAG.getCALLSEQ_END(
    377       Chain, DAG.getConstant(NumBytes, getPointerTy(), true),
    378       DAG.getConstant(0, getPointerTy(), true), InFlag, CLI.DL);
    379   InFlag = Chain.getValue(1);
    380 
    381   // Handle result values, copying them out of physregs into vregs that we
    382   // return.
    383   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
    384                          InVals);
    385 }
    386 
    387 SDValue
    388 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
    389                                bool IsVarArg,
    390                                const SmallVectorImpl<ISD::OutputArg> &Outs,
    391                                const SmallVectorImpl<SDValue> &OutVals,
    392                                SDLoc DL, SelectionDAG &DAG) const {
    393 
    394   // CCValAssign - represent the assignment of the return value to a location
    395   SmallVector<CCValAssign, 16> RVLocs;
    396   MachineFunction &MF = DAG.getMachineFunction();
    397 
    398   // CCState - Info about the registers and stack slot.
    399   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
    400 
    401   if (MF.getFunction()->getReturnType()->isAggregateType()) {
    402     DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
    403                                   "only integer returns supported", SDValue());
    404     DAG.getContext()->diagnose(Err);
    405   }
    406 
    407   // Analize return values.
    408   CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
    409 
    410   SDValue Flag;
    411   SmallVector<SDValue, 4> RetOps(1, Chain);
    412 
    413   // Copy the result values into the output registers.
    414   for (unsigned i = 0; i != RVLocs.size(); ++i) {
    415     CCValAssign &VA = RVLocs[i];
    416     assert(VA.isRegLoc() && "Can only return in registers!");
    417 
    418     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
    419 
    420     // Guarantee that all emitted copies are stuck together,
    421     // avoiding something bad.
    422     Flag = Chain.getValue(1);
    423     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
    424   }
    425 
    426   unsigned Opc = BPFISD::RET_FLAG;
    427   RetOps[0] = Chain; // Update chain.
    428 
    429   // Add the flag if we have it.
    430   if (Flag.getNode())
    431     RetOps.push_back(Flag);
    432 
    433   return DAG.getNode(Opc, DL, MVT::Other, RetOps);
    434 }
    435 
    436 SDValue BPFTargetLowering::LowerCallResult(
    437     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
    438     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
    439     SmallVectorImpl<SDValue> &InVals) const {
    440 
    441   MachineFunction &MF = DAG.getMachineFunction();
    442   // Assign locations to each value returned by this call.
    443   SmallVector<CCValAssign, 16> RVLocs;
    444   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
    445 
    446   if (Ins.size() >= 2) {
    447     DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
    448                                   "only small returns supported", SDValue());
    449     DAG.getContext()->diagnose(Err);
    450   }
    451 
    452   CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
    453 
    454   // Copy all of the result registers out of their specified physreg.
    455   for (auto &Val : RVLocs) {
    456     Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
    457                                Val.getValVT(), InFlag).getValue(1);
    458     InFlag = Chain.getValue(2);
    459     InVals.push_back(Chain.getValue(0));
    460   }
    461 
    462   return Chain;
    463 }
    464 
    465 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
    466   switch (CC) {
    467   default:
    468     break;
    469   case ISD::SETULT:
    470   case ISD::SETULE:
    471   case ISD::SETLT:
    472   case ISD::SETLE:
    473     CC = ISD::getSetCCSwappedOperands(CC);
    474     std::swap(LHS, RHS);
    475     break;
    476   }
    477 }
    478 
    479 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
    480   SDValue Chain = Op.getOperand(0);
    481   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
    482   SDValue LHS = Op.getOperand(2);
    483   SDValue RHS = Op.getOperand(3);
    484   SDValue Dest = Op.getOperand(4);
    485   SDLoc DL(Op);
    486 
    487   NegateCC(LHS, RHS, CC);
    488 
    489   return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
    490                      DAG.getConstant(CC, MVT::i64), Dest);
    491 }
    492 
    493 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
    494   SDValue LHS = Op.getOperand(0);
    495   SDValue RHS = Op.getOperand(1);
    496   SDValue TrueV = Op.getOperand(2);
    497   SDValue FalseV = Op.getOperand(3);
    498   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
    499   SDLoc DL(Op);
    500 
    501   NegateCC(LHS, RHS, CC);
    502 
    503   SDValue TargetCC = DAG.getConstant(CC, MVT::i64);
    504 
    505   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
    506   SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
    507 
    508   return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
    509 }
    510 
    511 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
    512   switch (Opcode) {
    513   default:
    514     return NULL;
    515   case BPFISD::RET_FLAG:
    516     return "BPFISD::RET_FLAG";
    517   case BPFISD::CALL:
    518     return "BPFISD::CALL";
    519   case BPFISD::SELECT_CC:
    520     return "BPFISD::SELECT_CC";
    521   case BPFISD::BR_CC:
    522     return "BPFISD::BR_CC";
    523   case BPFISD::Wrapper:
    524     return "BPFISD::Wrapper";
    525   }
    526 }
    527 
    528 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
    529                                               SelectionDAG &DAG) const {
    530   SDLoc DL(Op);
    531   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
    532   SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
    533 
    534   return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
    535 }
    536 
    537 MachineBasicBlock *
    538 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
    539                                                MachineBasicBlock *BB) const {
    540   const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
    541   DebugLoc DL = MI->getDebugLoc();
    542 
    543   assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert");
    544 
    545   // To "insert" a SELECT instruction, we actually have to insert the diamond
    546   // control-flow pattern.  The incoming instruction knows the destination vreg
    547   // to set, the condition code register to branch on, the true/false values to
    548   // select between, and a branch opcode to use.
    549   const BasicBlock *LLVM_BB = BB->getBasicBlock();
    550   MachineFunction::iterator I = BB;
    551   ++I;
    552 
    553   // ThisMBB:
    554   // ...
    555   //  TrueVal = ...
    556   //  jmp_XX r1, r2 goto Copy1MBB
    557   //  fallthrough --> Copy0MBB
    558   MachineBasicBlock *ThisMBB = BB;
    559   MachineFunction *F = BB->getParent();
    560   MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
    561   MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
    562 
    563   F->insert(I, Copy0MBB);
    564   F->insert(I, Copy1MBB);
    565   // Update machine-CFG edges by transferring all successors of the current
    566   // block to the new block which will contain the Phi node for the select.
    567   Copy1MBB->splice(Copy1MBB->begin(), BB,
    568                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
    569   Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
    570   // Next, add the true and fallthrough blocks as its successors.
    571   BB->addSuccessor(Copy0MBB);
    572   BB->addSuccessor(Copy1MBB);
    573 
    574   // Insert Branch if Flag
    575   unsigned LHS = MI->getOperand(1).getReg();
    576   unsigned RHS = MI->getOperand(2).getReg();
    577   int CC = MI->getOperand(3).getImm();
    578   switch (CC) {
    579   case ISD::SETGT:
    580     BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
    581         .addReg(LHS)
    582         .addReg(RHS)
    583         .addMBB(Copy1MBB);
    584     break;
    585   case ISD::SETUGT:
    586     BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
    587         .addReg(LHS)
    588         .addReg(RHS)
    589         .addMBB(Copy1MBB);
    590     break;
    591   case ISD::SETGE:
    592     BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
    593         .addReg(LHS)
    594         .addReg(RHS)
    595         .addMBB(Copy1MBB);
    596     break;
    597   case ISD::SETUGE:
    598     BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
    599         .addReg(LHS)
    600         .addReg(RHS)
    601         .addMBB(Copy1MBB);
    602     break;
    603   case ISD::SETEQ:
    604     BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
    605         .addReg(LHS)
    606         .addReg(RHS)
    607         .addMBB(Copy1MBB);
    608     break;
    609   case ISD::SETNE:
    610     BuildMI(BB, DL, TII.get(BPF::JNE_rr))
    611         .addReg(LHS)
    612         .addReg(RHS)
    613         .addMBB(Copy1MBB);
    614     break;
    615   default:
    616     report_fatal_error("unimplemented select CondCode " + Twine(CC));
    617   }
    618 
    619   // Copy0MBB:
    620   //  %FalseValue = ...
    621   //  # fallthrough to Copy1MBB
    622   BB = Copy0MBB;
    623 
    624   // Update machine-CFG edges
    625   BB->addSuccessor(Copy1MBB);
    626 
    627   // Copy1MBB:
    628   //  %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
    629   // ...
    630   BB = Copy1MBB;
    631   BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg())
    632       .addReg(MI->getOperand(5).getReg())
    633       .addMBB(Copy0MBB)
    634       .addReg(MI->getOperand(4).getReg())
    635       .addMBB(ThisMBB);
    636 
    637   MI->eraseFromParent(); // The pseudo instruction is gone now.
    638   return BB;
    639 }
    640