1 /* 2 * Copyright 2012 The Android Open Source Project 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * Not a Contribution. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 #ifndef HW_AR3K_H 19 #define HW_AR3K_H 20 21 /****************************************************************************** 22 ** Constants & Macros 23 ******************************************************************************/ 24 #define MAX_CNT_RETRY 100 25 26 #define HCI_MAX_CMD_SIZE 260 27 #define HCI_MAX_EVENT_SIZE 260 28 #define HCI_CHG_BAUD_CMD_OCF 0x0C 29 #define HCI_VENDOR_CMD_OGF 0x3F 30 #define WRITE_BDADDR_CMD_LEN 14 31 #define WRITE_BAUD_CMD_LEN 6 32 #define MAX_CMD_LEN WRITE_BDADDR_CMD_LEN 33 #define GET_VERSION_OCF 0x1E 34 /* Byte order conversions */ 35 #if __BYTE_ORDER == __LITTLE_ENDIAN 36 #define htobs(d) (d) 37 #define htobl(d) (d) 38 #define btohs(d) (d) 39 #define btohl(d) (d) 40 #elif __BYTE_ORDER == __BIG_ENDIAN 41 #define htobs(d) bswap_16(d) 42 #define htobl(d) bswap_32(d) 43 #define btohs(d) bswap_16(d) 44 #define btohl(d) bswap_32(d) 45 #else 46 #error "Unknown byte order" 47 #endif 48 49 #define FW_PATH "/system/etc/firmware/ar3k/" 50 51 #define STREAM_TO_UINT16(u16, p) \ 52 {u16 = ((uint16_t)(*(p)) + (((uint16_t)(*((p) + 1))) << 8)); (p) += 2;} 53 #define UINT16_TO_STREAM(p, u16) \ 54 {*(p)++ = (uint8_t)(u16); *(p)++ = (uint8_t)((u16) >> 8);} 55 #define UINT32_TO_STREAM(p, u32) \ 56 {*(p)++ = (uint8_t)(u32); *(p)++ = (uint8_t)((u32) >> 8);\ 57 *(p)++ = (uint8_t)((u32) >> 16); *(p)++ = (uint8_t)((u32) >> 24);} 58 59 #define MAX_TAGS 50 60 #define PS_HDR_LEN 4 61 #define HCI_VENDOR_CMD_OGF 0x3F 62 #define HCI_PS_CMD_OCF 0x0B 63 64 #define VERIFY_CRC 9 65 #define PS_REGION 1 66 #define PATCH_REGION 2 67 #define BDADDR_FILE "ar3kbdaddr.pst" 68 69 70 #define MAX_PATCH_CMD 244 71 struct patch_entry { 72 int16_t len; 73 uint8_t data[MAX_PATCH_CMD]; 74 }; 75 #define HCI_UART_RAW_DEVICE 0 76 #define HCI_COMMAND_HDR_SIZE 3 77 #define PS_WRITE 1 78 #define PS_RESET 2 79 #define WRITE_PATCH 8 80 #define ENABLE_PATCH 11 81 82 #define HCI_PS_CMD_HDR_LEN 7 83 #define HCI_CMD_MAX_LEN 258 84 #define PS_RESET_PARAM_LEN 6 85 #define PS_RESET_CMD_LEN (HCI_PS_CMD_HDR_LEN + PS_RESET_PARAM_LEN) 86 87 #define PS_ID_MASK 0xFF 88 89 90 #define LOCAL_NAME_BUFFER_LEN 32 91 #define DEV_REGISTER 0x4FFC 92 #define GET_DEV_TYPE_OCF 0x05 93 94 #define HCIDEVUP _IOW('H', 201, int) 95 #define OGF_VENDOR_CMD 0x3f 96 #define EVT_CMD_COMPLETE_SIZE 3 97 #define EVT_CMD_STATUS 0x0F 98 #define EVT_CMD_STATUS_SIZE 4 99 #define HCI_COMMAND_HDR_SIZE 3 100 #define HCI_EVENT_HDR_SIZE 2 101 #define HCI_EV_SUCCESS 0x00 102 /* HCI Socket options */ 103 #define HCI_DATA_DIR 1 104 #define HCI_FILTER 2 105 #define HCI_TIME_STAMP 3 106 107 /* HCI CMSG flags */ 108 #define HCI_CMSG_DIR 0x0001 109 #define HCI_CMSG_TSTAMP 0x0002 110 111 #ifndef VENDOR_LPM_PROC_NODE 112 #define VENDOR_LPM_PROC_NODE "/sys/module/hci_uart/parameters/ath_lpm" 113 #endif 114 115 /* proc fs node for notifying write request */ 116 #ifndef VENDOR_BTWRITE_PROC_NODE 117 #define VENDOR_BTWRITE_PROC_NODE "/sys/module/hci_uart/parameters/ath_btwrite" 118 #endif 119 120 /****************************************************************************** 121 ** Local type definitions 122 ******************************************************************************/ 123 typedef struct { 124 uint8_t b[6]; 125 } __attribute__((packed)) bdaddr_t; 126 127 struct sockaddr_hci { 128 sa_family_t hci_family; 129 unsigned short hci_dev; 130 unsigned short hci_channel; 131 }; 132 133 struct tag_info { 134 unsigned section; 135 unsigned line_count; 136 unsigned char_cnt; 137 unsigned byte_count; 138 }; 139 140 struct ps_cfg_entry { 141 uint32_t id; 142 uint32_t len; 143 uint8_t *data; 144 }; 145 146 struct ps_entry_type { 147 unsigned char type; 148 unsigned char array; 149 }; 150 151 struct uart_t { 152 char *type; 153 int m_id; 154 int p_id; 155 int proto; 156 int init_speed; 157 int speed; 158 int flags; 159 int pm; 160 char *bdaddr; 161 int (*init) (int fd, struct uart_t *u, struct termios *ti); 162 int (*post) (int fd, struct uart_t *u, struct termios *ti); 163 }; 164 #endif /* HW_AR3K_H */ 165
