| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/ |
| Instruction.java | 32 package org.jf.dexlib2.iface.instruction;
37 * This class represents a generic instruction.
39 * There are two categories of sub-interfaces of this interface. The dexlib2.iface.instruction.* interfaces are set of
40 * generic categories of instructions, while the dexlib2.iface.instruction.formats.* interfaces each represent a
41 * specific instruction format, and are typically built up as a composite of generic instruction interfaces.
43 public interface Instruction {
45 * Gets the opcode of this instruction.
47 * @return The Opcode of this instruction.
52 * Gets the size of this instruction
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| /external/llvm/include/llvm/MC/ |
| MCWin64EH.h | 27 struct Instruction {
28 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) {
29 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1);
31 static WinEH::Instruction Alloc(MCSymbol *L, unsigned Size) {
32 return WinEH::Instruction(Size > 128 ? UOP_AllocLarge : UOP_AllocSmall, L,
35 static WinEH::Instruction PushMachFrame(MCSymbol *L, bool Code) {
36 return WinEH::Instruction(UOP_PushMachFrame, L, -1, Code ? 1 : 0);
38 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg,
40 return WinEH::Instruction(Offset > 512 * 1024 - 8 ? UOP_SaveNonVolBig
44 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg
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| MCWinEH.h | 23 struct Instruction {
29 Instruction(unsigned Op, MCSymbol *L, unsigned Reg, unsigned Off)
46 std::vector<Instruction> Instructions;
|
| /frameworks/compile/mclinker/lib/Target/Hexagon/ |
| HexagonRelocationFunctions.h | 18 } Instruction;
|
| /external/llvm/lib/IR/ |
| Instruction.cpp | 1 //===-- Instruction.cpp - Implement the Instruction class -----------------===//
10 // This file implements the Instruction class for the IR library.
14 #include "llvm/IR/Instruction.h"
23 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps,
24 Instruction *InsertBefore)
27 // If requested, insert this instruction into a basic block...
30 "Instruction to insert before is not in a basic block!");
35 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps
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| /external/proguard/src/proguard/classfile/instruction/ |
| Instruction.java | 21 package proguard.classfile.instruction;
25 import proguard.classfile.instruction.visitor.InstructionVisitor;
32 public abstract class Instruction
872 * Returns the canonical opcode of this instruction, i.e. typically the
882 * Shrinks this instruction to its shortest possible form.
883 * @return this instruction.
885 public abstract Instruction shrink();
890 * Writes the Instruction at the given offset in the given code attribute.
899 * Writes the Instruction at the given offset in the given code array.
918 * Returns whether the instruction is wide, i.e. preceded by a wide opcode
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| /external/lldb/source/Core/ |
| Disassembler.cpp | 424 Instruction *inst = disasm_ptr->GetInstructionList().GetInstructionAtIndex (i).get();
555 Instruction::Instruction(const Address &address, AddressClass addr_class) :
563 Instruction::~Instruction()
568 Instruction::GetAddressClass ()
576 Instruction::Dump (lldb_private::Stream *s,
647 Instruction::DumpEmulation (const ArchSpec &arch)
660 Instruction::ReadArray (FILE *in_file, Stream *out_stream, OptionValue::Type data_type)
672 out_stream->Printf ("Instruction::ReadArray: Error reading file (fgets).\n")
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 101 Instruction *insn = src->value->getUniqueInsn();
173 if (!insn || !insn->bb) // Unbound instruction ?
180 Instruction *insn = (*it)->getInsn();
276 Instruction *insn = getInsn();
552 void Instruction::init()
582 Instruction::Instruction()
593 Instruction::Instruction(Function *fn, operation opr, DataType ty)
603 Instruction::~Instruction(
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| nv50_ir_from_tgsi.cpp | 41 class Instruction
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
209 unsigned int Instruction::srcMask(unsigned int s) const
213 switch (insn->Instruction.Opcode) {
248 assert(insn->Instruction.Texture);
251 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &
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| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| Instruction.java | 54 public class Instruction implements RawDexObject {
63 // Immutable information about this class of instruction.
66 // The raw bytes of the instruction.
67 // Only used during reading, and writing out is done from the decoded instruction data.
86 * Clone an instruction.
88 public Instruction clone() {
89 Instruction newInsn = new Instruction();
90 // If we've generated a new instruction, we won't have calculated its raw array.
157 * Get the size of an instruction, in code-words. (Code-words are 16-bits.
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| /external/lldb/include/lldb/Core/ |
| Disassembler.h | 30 class Instruction
33 Instruction (const Address &address,
37 ~Instruction();
129 Address m_address; // The section offset address of this instruction
130 // We include an address class in the Instruction class to
131 // allow the instruction specify the eAddressClassCodeAlternateISA
139 Opcode m_opcode; // The opcode for this instruction
199 public Instruction
214 // TODO: fill this in and put opcode name into Instruction::m_opcode_name,
215 // mnemonic into Instruction::m_mnemonics, and any comment into
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| /external/llvm/bindings/python/llvm/ |
| core.py | 30 "Instruction",
343 return i and Instruction(i)
348 return i and Instruction(i)
384 if not isinstance(self.inst, Instruction):
400 class Instruction(Value):
408 return i and Instruction(i)
413 return i and Instruction(i)
582 # Instruction Declarations.
583 library.LLVMGetNextInstruction.argtypes = [Instruction]
586 library.LLVMGetPreviousInstruction.argtypes = [Instruction]
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| /external/llvm/lib/DebugInfo/DWARF/ |
| DWARFDebugFrame.cpp | 63 /// An entry may contain CFI instructions. An instruction consists of an
66 struct Instruction {
67 Instruction(uint8_t Opcode)
75 std::vector<Instruction> Instructions;
77 /// Convenience methods to add a new instruction with the given opcode and
80 Instructions.push_back(Instruction(Opcode));
84 Instructions.push_back(Instruction(Opcode));
89 Instructions.push_back(Instruction(Opcode));
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_parse.h | 95 struct tgsi_instruction Instruction;
|
| /external/llvm/include/llvm/IR/ |
| Instruction.h | 1 //===-- llvm/Instruction.h - Instruction class definition -------*- C++ -*-===//
10 // This file contains the declaration of the Instruction class, which is the
33 struct ilist_traits<Instruction>
34 : public SymbolTableListTraits<Instruction, BasicBlock> {
40 Instruction *createSentinel() const;
41 static void destroySentinel(Instruction *) {}
43 Instruction *provideInitialHead() const { return createSentinel(); }
44 Instruction *ensureHead(Instruction *) const { return createSentinel();
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc.h | 297 struct tgsi_instruction Instruction;
|
| /external/v8/src/arm64/ |
| instructions-arm64.h | 86 // instruction (such as with fcvta). It cannot be set in FPCR.
97 class Instruction {
124 V8_INLINE Instruction* following(int count = 1) {
128 V8_INLINE Instruction* preceding(int count = 1) {
219 // does not check that the instruction actually has an Rd field.
248 // does not check that the instruction actually has an Rn field.
291 // The range of the branch instruction, expressed as 'instr +- range'.
329 // A marking nop is an instruction
338 // Find the PC offset encoded in this instruction. 'this' may be a branch or
339 // a PC-relative addressing instruction
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| /external/llvm/lib/MC/ |
| MCStreamer.cpp | 261 MCCFIInstruction Instruction =
264 CurFrame->Instructions.push_back(Instruction);
270 MCCFIInstruction Instruction =
273 CurFrame->Instructions.push_back(Instruction);
278 MCCFIInstruction Instruction =
281 CurFrame->Instructions.push_back(Instruction);
286 MCCFIInstruction Instruction =
289 CurFrame->Instructions.push_back(Instruction);
295 MCCFIInstruction Instruction =
298 CurFrame->Instructions.push_back(Instruction);
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented.
190 fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score
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| /art/runtime/ |
| dex_instruction.h | 35 class Instruction {
174 // Returns the size (in 2 byte code units) of this instruction.
184 // Reads an instruction out of the stream at the specified address.
185 static const Instruction* At(const uint16_t* code) {
187 return reinterpret_cast<const Instruction*>(code);
190 // Reads an instruction out of the stream from the current address plus an offset.
191 const Instruction* RelativeAt(int32_t offset) const WARN_UNUSED {
195 // Returns a pointer to the next instruction in the stream.
196 const Instruction* Next() const {
200 // Returns a pointer to the instruction after this 1xx instruction in the stream
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| /external/v8/src/compiler/ |
| instruction.h | 15 #include "src/compiler/instruction-codes.h"
109 // Lifetime of operand inside the instruction.
112 // instruction start. Register allocator is free to assign the same register
113 // to some other operand used inside instruction (i.e. temporary or
118 // instruction. This means that register allocator will not reuse it's
119 // register for any other operand inside instruction.
404 class Instruction : public ZoneObject {
438 static Instruction* New(Zone* zone, InstructionCode opcode) {
442 static Instruction* New(Zone* zone, InstructionCode opcode,
452 int size = static_cast<int>(RoundUp(sizeof(Instruction), kPointerSize)
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| /external/vixl/src/vixl/a64/ |
| instructions-a64.h | 44 // This is the nominal page size (as used by the adrp instruction); the actual
151 // the instruction (such as with fcvta). It cannot be set in FPCR.
163 class Instruction {
286 // does not check that the instruction actually has an Rd field.
315 // does not check that the instruction actually has an Rn field.
342 // Find the target of this instruction. 'this' may be a branch or a
343 // PC-relative addressing instruction.
344 const Instruction* ImmPCOffsetTarget() const;
347 // a PC-relative addressing instruction.
348 void SetImmPCOffsetTarget(const Instruction* target)
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| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 150 | Invalid (* not an instruction *)
283 | Instruction of Opcode.t
[all...] |
| llvm_ocaml.c | 496 Instruction
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| /external/v8/src/arm/ |
| constants-arm.h | 17 // Use UDF, the permanently undefined instruction.
122 // Instruction objects are pointers to 32bit values, and provide methods to
162 // Instruction encoding bits and masks.
169 A = 1 << 21, // Accumulate in multiply instruction (or not).
196 // Instruction bit masks.
199 kRdMask = 15 << 12, // In str instruction.
211 // Addressing modes and instruction variants.
409 // Instruction abstraction.
411 // The class Instruction enables access to individual fields defined in the ARM
412 // architecture instruction set encoding as described in figure A3-1
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