/external/llvm/lib/Target/R600/ |
SIMachineFunctionInfo.cpp | 49 unsigned Lane = (Offset / 4) % 64; 67 Spill.Lane = Lane;
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SIMachineFunctionInfo.h | 38 int Lane; 39 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } 40 SpilledReg() : VGPR(0), Lane(-1) { } 41 bool hasLane() { return Lane != -1;}
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SIISelLowering.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
A15SDOptimizer.cpp | 72 unsigned Reg, unsigned Lane, 78 unsigned DReg, unsigned Lane, 93 DebugLoc DL, unsigned DReg, unsigned Lane, 433 unsigned Reg, unsigned Lane, bool QPR) { 442 .addImm(Lane)); 447 // Creates a SPR register from a DPR by copying the value in lane 0. 452 unsigned DReg, unsigned Lane, 459 .addReg(DReg, 0, Lane); 503 DebugLoc DL, unsigned DReg, unsigned Lane, 512 .addImm(Lane); [all...] |
ARMExpandPseudoInsts.cpp | 93 // For quad-register load-lane and store-lane pseudo instructors, the 95 // OddDblSpc depending on the lane number operand. 112 uint8_t RegElts; // elements per D register; used for lane ops 511 // The lane operand is always the 3rd from last operand, before the 2 513 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 515 // Adjust the lane and spacing as needed for Q registers. 516 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 517 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 519 Lane -= RegElts [all...] |
ARMISelDAGToDAG.cpp | 230 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should [all...] |
ARMBaseInstrInfo.cpp | 68 bool HasLane; // True if instruction has an extra "lane" operand. [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | [all...] |
/external/clang/lib/CodeGen/ |
CGBuiltin.cpp | [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
SLPVectorizer.cpp | 504 Scalar(S), User(U), Lane(L){}; 509 // Which lane does the scalar belong to. 510 int Lane; 908 // For each lane: 909 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { 910 Value *Scalar = Entry->Scalars[Lane]; [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | [all...] |