/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 290 int NewOpc = getTransformOpcode(OldOpc); 291 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); 345 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
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AArch64LoadStoreOptimizer.cpp | 346 unsigned NewOpc = getMatchingPairOpcode(Opc); 377 I->getDebugLoc(), TII->get(NewOpc)) 655 unsigned NewOpc = getPreIndexedOpcode(I->getOpcode()); 657 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc)) 698 unsigned NewOpc = getPostIndexedOpcode(I->getOpcode()); 700 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc)) [all...] |
AArch64InstrInfo.cpp | 839 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); 840 if (NewOpc == Opc) 842 const MCInstrDesc &MCID = get(NewOpc); 872 unsigned NewOpc = MI->getOpcode(); 885 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break; 886 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break; 887 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break; 888 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break; 889 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break; 890 case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break [all...] |
AArch64ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsLongBranch.cpp | 219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); 220 const MCInstrDesc &NewDesc = TII->get(NewOpc);
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDILISelDAGToDAG.cpp | 166 unsigned int NewOpc = AMDGPU::COPY; 168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
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/external/llvm/lib/Target/X86/Disassembler/ |
X86Disassembler.cpp | 344 unsigned NewOpc; 347 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; 348 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; 349 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; 350 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; 351 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; 352 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; 353 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; 354 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; 355 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break [all...] |
/external/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | [all...] |
ARMConstantIslandPass.cpp | [all...] |
ARMISelDAGToDAG.cpp | [all...] |
ARMLoadStoreOptimizer.cpp | [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/R600/ |
SIInstrInfo.cpp | 432 int NewOpc; 435 NewOpc = AMDGPU::getCommuteRev(Opcode); 437 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1) 438 return NewOpc; 441 NewOpc = AMDGPU::getCommuteOrig(Opcode); 443 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1) 444 return NewOpc; [all...] |
/external/llvm/lib/Target/X86/ |
X86MCInstLower.cpp | 473 unsigned NewOpc; 476 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 477 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 478 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 479 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 480 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 481 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 482 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 483 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 484 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break [all...] |
X86InstrInfo.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
MachineLICM.cpp | [all...] |
TwoAddressInstructionPass.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 457 unsigned NewOpc; 462 NewOpc = ISD::FP_TO_SINT; 466 NewOpc = ISD::FP_TO_UINT; 472 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0)); [all...] |
LegalizeIntegerTypes.cpp | 393 unsigned NewOpc = N->getOpcode(); 403 NewOpc = ISD::FP_TO_SINT; 405 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |