| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 84 unsigned NumRegs = RC->getNumRegs();
87 RCI.Order.reset(new MCPhysReg[NumRegs]);
116 RCI.NumRegs = N + CSRAlias.size();
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
130 if (StressRA && RCI.NumRegs > StressRA)
131 RCI.NumRegs = StressRA;
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
144 for (unsigned I = 0; I != RCI.NumRegs; ++I)
|
| VirtRegMap.cpp | 71 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
72 Virt2PhysMap.resize(NumRegs);
73 Virt2StackSlotMap.resize(NumRegs);
74 Virt2SplitMap.resize(NumRegs);
|
| LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
559 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
615 for (unsigned i = 0; i != NumRegs; ++i)
625 const unsigned NumRegs = TRI->getNumRegs();
626 PhysRegDef.assign(NumRegs, nullptr);
627 PhysRegUse.assign(NumRegs, nullptr);
647 runOnBlock(MBB, NumRegs);
649 PhysRegDef.assign(NumRegs, nullptr);
650 PhysRegUse.assign(NumRegs, nullptr)
[all...] |
| MachineLICM.cpp | 515 unsigned NumRegs = TRI->getNumRegs();
516 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
517 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
552 BitVector TermRegs(NumRegs);
[all...] |
| /art/runtime/verifier/ |
| register_line.h | 178 size_t NumRegs() const {
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 29 unsigned NumRegs;
36 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
40 return makeArrayRef(Order.get(), NumRegs);
87 return get(RC).NumRegs;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 255 unsigned NumRegs =
258 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
259 NumParts = NumRegs; // Silence a compiler warning.
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
625 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
627 for (unsigned i = 0; i != NumRegs; ++i)
630 Reg += NumRegs;
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT)
[all...] |
| FunctionLoweringInfo.cpp | 496 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
497 for (unsigned i = 0; i != NumRegs; ++i) {
|
| LegalizeDAG.cpp | 325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
339 for (unsigned i = 1; i < NumRegs; i++) {
446 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
457 for (unsigned i = 1; i < NumRegs; i++) {
[all...] |
| FastISel.cpp | 295 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
307 for (unsigned i = 0; i < NumRegs; i++)
[all...] |
| LegalizeIntegerTypes.cpp | 776 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
777 // The argument is passed as NumRegs registers of type RegVT.
779 SmallVector<SDValue, 8> Parts(NumRegs);
780 for (unsigned i = 0; i < NumRegs; ++i) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 507 bool NumRegs = false;
523 NumRegs = true;
527 if (NumRegs)
|
| ARMExpandPseudoInsts.cpp | 111 uint8_t NumRegs; // D registers loaded or stored
387 unsigned NumRegs = TableEntry->NumRegs;
398 if (NumRegs > 1 && TableEntry->copyAllListRegs)
400 if (NumRegs > 2 && TableEntry->copyAllListRegs)
402 if (NumRegs > 3 && TableEntry->copyAllListRegs)
452 unsigned NumRegs = TableEntry->NumRegs;
473 if (NumRegs > 1 && TableEntry->copyAllListRegs)
475 if (NumRegs > 2 && TableEntry->copyAllListRegs
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 486 unsigned NumRegs = Regs.size();
487 if (NumRegs <= 1)
502 for (unsigned I = 0; I < NumRegs; ++I)
520 } else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) {
522 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {
533 if (NumRegs <= 2)
545 NewBase = Regs[NumRegs-1].first;
649 UpdateBaseRegUses(MBB, MBBI, dl, Base, NumRegs, Pred, PredReg);
659 for (unsigned i = 0; i != NumRegs; ++i)
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 171 unsigned NumRegs;
175 NumRegs = 1;
178 NumRegs = 1;
181 NumRegs = 2;
184 NumRegs = 2;
187 NumRegs = 4;
190 NumRegs = 4;
193 NumRegs = 3;
196 NumRegs = 8;
199 NumRegs = 8
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 156 unsigned NumRegs; // Number of entries in the array
258 NumRegs = NR;
324 assert(RegNo < NumRegs &&
369 return NumRegs;
419 assert(RegNo < NumRegs &&
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| /external/v8/src/ |
| frames.cc | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/clang/lib/Sema/ |
| SemaDeclAttr.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 860 unsigned NumRegs;
870 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0),
880 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds
882 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds
889 return NumRegs == ~0u;
[all...] |
