1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the AArch64 target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 18 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 19 20 // FIXME: Is it easiest to fix this layering violation by moving the .inc 21 // #includes from AArch64MCTargetDesc.h to here? 22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringSwitch.h" 25 #include "llvm/Support/ErrorHandling.h" 26 27 namespace llvm { 28 29 inline static unsigned getWRegFromXReg(unsigned Reg) { 30 switch (Reg) { 31 case AArch64::X0: return AArch64::W0; 32 case AArch64::X1: return AArch64::W1; 33 case AArch64::X2: return AArch64::W2; 34 case AArch64::X3: return AArch64::W3; 35 case AArch64::X4: return AArch64::W4; 36 case AArch64::X5: return AArch64::W5; 37 case AArch64::X6: return AArch64::W6; 38 case AArch64::X7: return AArch64::W7; 39 case AArch64::X8: return AArch64::W8; 40 case AArch64::X9: return AArch64::W9; 41 case AArch64::X10: return AArch64::W10; 42 case AArch64::X11: return AArch64::W11; 43 case AArch64::X12: return AArch64::W12; 44 case AArch64::X13: return AArch64::W13; 45 case AArch64::X14: return AArch64::W14; 46 case AArch64::X15: return AArch64::W15; 47 case AArch64::X16: return AArch64::W16; 48 case AArch64::X17: return AArch64::W17; 49 case AArch64::X18: return AArch64::W18; 50 case AArch64::X19: return AArch64::W19; 51 case AArch64::X20: return AArch64::W20; 52 case AArch64::X21: return AArch64::W21; 53 case AArch64::X22: return AArch64::W22; 54 case AArch64::X23: return AArch64::W23; 55 case AArch64::X24: return AArch64::W24; 56 case AArch64::X25: return AArch64::W25; 57 case AArch64::X26: return AArch64::W26; 58 case AArch64::X27: return AArch64::W27; 59 case AArch64::X28: return AArch64::W28; 60 case AArch64::FP: return AArch64::W29; 61 case AArch64::LR: return AArch64::W30; 62 case AArch64::SP: return AArch64::WSP; 63 case AArch64::XZR: return AArch64::WZR; 64 } 65 // For anything else, return it unchanged. 66 return Reg; 67 } 68 69 inline static unsigned getXRegFromWReg(unsigned Reg) { 70 switch (Reg) { 71 case AArch64::W0: return AArch64::X0; 72 case AArch64::W1: return AArch64::X1; 73 case AArch64::W2: return AArch64::X2; 74 case AArch64::W3: return AArch64::X3; 75 case AArch64::W4: return AArch64::X4; 76 case AArch64::W5: return AArch64::X5; 77 case AArch64::W6: return AArch64::X6; 78 case AArch64::W7: return AArch64::X7; 79 case AArch64::W8: return AArch64::X8; 80 case AArch64::W9: return AArch64::X9; 81 case AArch64::W10: return AArch64::X10; 82 case AArch64::W11: return AArch64::X11; 83 case AArch64::W12: return AArch64::X12; 84 case AArch64::W13: return AArch64::X13; 85 case AArch64::W14: return AArch64::X14; 86 case AArch64::W15: return AArch64::X15; 87 case AArch64::W16: return AArch64::X16; 88 case AArch64::W17: return AArch64::X17; 89 case AArch64::W18: return AArch64::X18; 90 case AArch64::W19: return AArch64::X19; 91 case AArch64::W20: return AArch64::X20; 92 case AArch64::W21: return AArch64::X21; 93 case AArch64::W22: return AArch64::X22; 94 case AArch64::W23: return AArch64::X23; 95 case AArch64::W24: return AArch64::X24; 96 case AArch64::W25: return AArch64::X25; 97 case AArch64::W26: return AArch64::X26; 98 case AArch64::W27: return AArch64::X27; 99 case AArch64::W28: return AArch64::X28; 100 case AArch64::W29: return AArch64::FP; 101 case AArch64::W30: return AArch64::LR; 102 case AArch64::WSP: return AArch64::SP; 103 case AArch64::WZR: return AArch64::XZR; 104 } 105 // For anything else, return it unchanged. 106 return Reg; 107 } 108 109 static inline unsigned getBRegFromDReg(unsigned Reg) { 110 switch (Reg) { 111 case AArch64::D0: return AArch64::B0; 112 case AArch64::D1: return AArch64::B1; 113 case AArch64::D2: return AArch64::B2; 114 case AArch64::D3: return AArch64::B3; 115 case AArch64::D4: return AArch64::B4; 116 case AArch64::D5: return AArch64::B5; 117 case AArch64::D6: return AArch64::B6; 118 case AArch64::D7: return AArch64::B7; 119 case AArch64::D8: return AArch64::B8; 120 case AArch64::D9: return AArch64::B9; 121 case AArch64::D10: return AArch64::B10; 122 case AArch64::D11: return AArch64::B11; 123 case AArch64::D12: return AArch64::B12; 124 case AArch64::D13: return AArch64::B13; 125 case AArch64::D14: return AArch64::B14; 126 case AArch64::D15: return AArch64::B15; 127 case AArch64::D16: return AArch64::B16; 128 case AArch64::D17: return AArch64::B17; 129 case AArch64::D18: return AArch64::B18; 130 case AArch64::D19: return AArch64::B19; 131 case AArch64::D20: return AArch64::B20; 132 case AArch64::D21: return AArch64::B21; 133 case AArch64::D22: return AArch64::B22; 134 case AArch64::D23: return AArch64::B23; 135 case AArch64::D24: return AArch64::B24; 136 case AArch64::D25: return AArch64::B25; 137 case AArch64::D26: return AArch64::B26; 138 case AArch64::D27: return AArch64::B27; 139 case AArch64::D28: return AArch64::B28; 140 case AArch64::D29: return AArch64::B29; 141 case AArch64::D30: return AArch64::B30; 142 case AArch64::D31: return AArch64::B31; 143 } 144 // For anything else, return it unchanged. 145 return Reg; 146 } 147 148 149 static inline unsigned getDRegFromBReg(unsigned Reg) { 150 switch (Reg) { 151 case AArch64::B0: return AArch64::D0; 152 case AArch64::B1: return AArch64::D1; 153 case AArch64::B2: return AArch64::D2; 154 case AArch64::B3: return AArch64::D3; 155 case AArch64::B4: return AArch64::D4; 156 case AArch64::B5: return AArch64::D5; 157 case AArch64::B6: return AArch64::D6; 158 case AArch64::B7: return AArch64::D7; 159 case AArch64::B8: return AArch64::D8; 160 case AArch64::B9: return AArch64::D9; 161 case AArch64::B10: return AArch64::D10; 162 case AArch64::B11: return AArch64::D11; 163 case AArch64::B12: return AArch64::D12; 164 case AArch64::B13: return AArch64::D13; 165 case AArch64::B14: return AArch64::D14; 166 case AArch64::B15: return AArch64::D15; 167 case AArch64::B16: return AArch64::D16; 168 case AArch64::B17: return AArch64::D17; 169 case AArch64::B18: return AArch64::D18; 170 case AArch64::B19: return AArch64::D19; 171 case AArch64::B20: return AArch64::D20; 172 case AArch64::B21: return AArch64::D21; 173 case AArch64::B22: return AArch64::D22; 174 case AArch64::B23: return AArch64::D23; 175 case AArch64::B24: return AArch64::D24; 176 case AArch64::B25: return AArch64::D25; 177 case AArch64::B26: return AArch64::D26; 178 case AArch64::B27: return AArch64::D27; 179 case AArch64::B28: return AArch64::D28; 180 case AArch64::B29: return AArch64::D29; 181 case AArch64::B30: return AArch64::D30; 182 case AArch64::B31: return AArch64::D31; 183 } 184 // For anything else, return it unchanged. 185 return Reg; 186 } 187 188 namespace AArch64CC { 189 190 // The CondCodes constants map directly to the 4-bit encoding of the condition 191 // field for predicated instructions. 192 enum CondCode { // Meaning (integer) Meaning (floating-point) 193 EQ = 0x0, // Equal Equal 194 NE = 0x1, // Not equal Not equal, or unordered 195 HS = 0x2, // Unsigned higher or same >, ==, or unordered 196 LO = 0x3, // Unsigned lower Less than 197 MI = 0x4, // Minus, negative Less than 198 PL = 0x5, // Plus, positive or zero >, ==, or unordered 199 VS = 0x6, // Overflow Unordered 200 VC = 0x7, // No overflow Not unordered 201 HI = 0x8, // Unsigned higher Greater than, or unordered 202 LS = 0x9, // Unsigned lower or same Less than or equal 203 GE = 0xa, // Greater than or equal Greater than or equal 204 LT = 0xb, // Less than Less than, or unordered 205 GT = 0xc, // Greater than Greater than 206 LE = 0xd, // Less than or equal <, ==, or unordered 207 AL = 0xe, // Always (unconditional) Always (unconditional) 208 NV = 0xf, // Always (unconditional) Always (unconditional) 209 // Note the NV exists purely to disassemble 0b1111. Execution is "always". 210 Invalid 211 }; 212 213 inline static const char *getCondCodeName(CondCode Code) { 214 switch (Code) { 215 default: llvm_unreachable("Unknown condition code"); 216 case EQ: return "eq"; 217 case NE: return "ne"; 218 case HS: return "hs"; 219 case LO: return "lo"; 220 case MI: return "mi"; 221 case PL: return "pl"; 222 case VS: return "vs"; 223 case VC: return "vc"; 224 case HI: return "hi"; 225 case LS: return "ls"; 226 case GE: return "ge"; 227 case LT: return "lt"; 228 case GT: return "gt"; 229 case LE: return "le"; 230 case AL: return "al"; 231 case NV: return "nv"; 232 } 233 } 234 235 inline static CondCode getInvertedCondCode(CondCode Code) { 236 // To reverse a condition it's necessary to only invert the low bit: 237 238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 239 } 240 241 /// Given a condition code, return NZCV flags that would satisfy that condition. 242 /// The flag bits are in the format expected by the ccmp instructions. 243 /// Note that many different flag settings can satisfy a given condition code, 244 /// this function just returns one of them. 245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { 246 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 247 enum { N = 8, Z = 4, C = 2, V = 1 }; 248 switch (Code) { 249 default: llvm_unreachable("Unknown condition code"); 250 case EQ: return Z; // Z == 1 251 case NE: return 0; // Z == 0 252 case HS: return C; // C == 1 253 case LO: return 0; // C == 0 254 case MI: return N; // N == 1 255 case PL: return 0; // N == 0 256 case VS: return V; // V == 1 257 case VC: return 0; // V == 0 258 case HI: return C; // C == 1 && Z == 0 259 case LS: return 0; // C == 0 || Z == 1 260 case GE: return 0; // N == V 261 case LT: return N; // N != V 262 case GT: return 0; // Z == 0 && N == V 263 case LE: return Z; // Z == 1 || N != V 264 } 265 } 266 } // end namespace AArch64CC 267 268 /// Instances of this class can perform bidirectional mapping from random 269 /// identifier strings to operand encodings. For example "MSR" takes a named 270 /// system-register which must be encoded somehow and decoded for printing. This 271 /// central location means that the information for those transformations is not 272 /// duplicated and remains in sync. 273 /// 274 /// FIXME: currently the algorithm is a completely unoptimised linear 275 /// search. Obviously this could be improved, but we would probably want to work 276 /// out just how often these instructions are emitted before working on it. It 277 /// might even be optimal to just reorder the tables for the common instructions 278 /// rather than changing the algorithm. 279 struct AArch64NamedImmMapper { 280 struct Mapping { 281 const char *Name; 282 uint32_t Value; 283 uint64_t AvailableForFeatures; 284 // empty AvailableForFeatures means "always-on" 285 bool isNameEqual(std::string Other, uint64_t FeatureBits=~0ULL) const { 286 if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits)) 287 return false; 288 return Name == Other; 289 } 290 bool isValueEqual(uint32_t Other, uint64_t FeatureBits=~0ULL) const { 291 if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits)) 292 return false; 293 return Value == Other; 294 } 295 }; 296 297 template<int N> 298 AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm) 299 : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {} 300 301 StringRef toString(uint32_t Value, uint64_t FeatureBits, bool &Valid) const; 302 uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const; 303 304 /// Many of the instructions allow an alternative assembly form consisting of 305 /// a simple immediate. Currently the only valid forms are ranges [0, N) where 306 /// N being 0 indicates no immediate syntax-form is allowed. 307 bool validImm(uint32_t Value) const; 308 protected: 309 const Mapping *Mappings; 310 size_t NumMappings; 311 uint32_t TooBigImm; 312 }; 313 314 namespace AArch64AT { 315 enum ATValues { 316 Invalid = -1, // Op0 Op1 CRn CRm Op2 317 S1E1R = 0x43c0, // 01 000 0111 1000 000 318 S1E2R = 0x63c0, // 01 100 0111 1000 000 319 S1E3R = 0x73c0, // 01 110 0111 1000 000 320 S1E1W = 0x43c1, // 01 000 0111 1000 001 321 S1E2W = 0x63c1, // 01 100 0111 1000 001 322 S1E3W = 0x73c1, // 01 110 0111 1000 001 323 S1E0R = 0x43c2, // 01 000 0111 1000 010 324 S1E0W = 0x43c3, // 01 000 0111 1000 011 325 S12E1R = 0x63c4, // 01 100 0111 1000 100 326 S12E1W = 0x63c5, // 01 100 0111 1000 101 327 S12E0R = 0x63c6, // 01 100 0111 1000 110 328 S12E0W = 0x63c7 // 01 100 0111 1000 111 329 }; 330 331 struct ATMapper : AArch64NamedImmMapper { 332 const static Mapping ATMappings[]; 333 334 ATMapper(); 335 }; 336 337 } 338 namespace AArch64DB { 339 enum DBValues { 340 Invalid = -1, 341 OSHLD = 0x1, 342 OSHST = 0x2, 343 OSH = 0x3, 344 NSHLD = 0x5, 345 NSHST = 0x6, 346 NSH = 0x7, 347 ISHLD = 0x9, 348 ISHST = 0xa, 349 ISH = 0xb, 350 LD = 0xd, 351 ST = 0xe, 352 SY = 0xf 353 }; 354 355 struct DBarrierMapper : AArch64NamedImmMapper { 356 const static Mapping DBarrierMappings[]; 357 358 DBarrierMapper(); 359 }; 360 } 361 362 namespace AArch64DC { 363 enum DCValues { 364 Invalid = -1, // Op1 CRn CRm Op2 365 ZVA = 0x5ba1, // 01 011 0111 0100 001 366 IVAC = 0x43b1, // 01 000 0111 0110 001 367 ISW = 0x43b2, // 01 000 0111 0110 010 368 CVAC = 0x5bd1, // 01 011 0111 1010 001 369 CSW = 0x43d2, // 01 000 0111 1010 010 370 CVAU = 0x5bd9, // 01 011 0111 1011 001 371 CIVAC = 0x5bf1, // 01 011 0111 1110 001 372 CISW = 0x43f2 // 01 000 0111 1110 010 373 }; 374 375 struct DCMapper : AArch64NamedImmMapper { 376 const static Mapping DCMappings[]; 377 378 DCMapper(); 379 }; 380 381 } 382 383 namespace AArch64IC { 384 enum ICValues { 385 Invalid = -1, // Op1 CRn CRm Op2 386 IALLUIS = 0x0388, // 000 0111 0001 000 387 IALLU = 0x03a8, // 000 0111 0101 000 388 IVAU = 0x1ba9 // 011 0111 0101 001 389 }; 390 391 392 struct ICMapper : AArch64NamedImmMapper { 393 const static Mapping ICMappings[]; 394 395 ICMapper(); 396 }; 397 398 static inline bool NeedsRegister(ICValues Val) { 399 return Val == IVAU; 400 } 401 } 402 403 namespace AArch64ISB { 404 enum ISBValues { 405 Invalid = -1, 406 SY = 0xf 407 }; 408 struct ISBMapper : AArch64NamedImmMapper { 409 const static Mapping ISBMappings[]; 410 411 ISBMapper(); 412 }; 413 } 414 415 namespace AArch64PRFM { 416 enum PRFMValues { 417 Invalid = -1, 418 PLDL1KEEP = 0x00, 419 PLDL1STRM = 0x01, 420 PLDL2KEEP = 0x02, 421 PLDL2STRM = 0x03, 422 PLDL3KEEP = 0x04, 423 PLDL3STRM = 0x05, 424 PLIL1KEEP = 0x08, 425 PLIL1STRM = 0x09, 426 PLIL2KEEP = 0x0a, 427 PLIL2STRM = 0x0b, 428 PLIL3KEEP = 0x0c, 429 PLIL3STRM = 0x0d, 430 PSTL1KEEP = 0x10, 431 PSTL1STRM = 0x11, 432 PSTL2KEEP = 0x12, 433 PSTL2STRM = 0x13, 434 PSTL3KEEP = 0x14, 435 PSTL3STRM = 0x15 436 }; 437 438 struct PRFMMapper : AArch64NamedImmMapper { 439 const static Mapping PRFMMappings[]; 440 441 PRFMMapper(); 442 }; 443 } 444 445 namespace AArch64PState { 446 enum PStateValues { 447 Invalid = -1, 448 SPSel = 0x05, 449 DAIFSet = 0x1e, 450 DAIFClr = 0x1f, 451 452 // v8.1a "Privileged Access Never" extension-specific PStates 453 PAN = 0x04, 454 }; 455 456 struct PStateMapper : AArch64NamedImmMapper { 457 const static Mapping PStateMappings[]; 458 459 PStateMapper(); 460 }; 461 462 } 463 464 namespace AArch64SE { 465 enum ShiftExtSpecifiers { 466 Invalid = -1, 467 LSL, 468 MSL, 469 LSR, 470 ASR, 471 ROR, 472 473 UXTB, 474 UXTH, 475 UXTW, 476 UXTX, 477 478 SXTB, 479 SXTH, 480 SXTW, 481 SXTX 482 }; 483 } 484 485 namespace AArch64Layout { 486 enum VectorLayout { 487 Invalid = -1, 488 VL_8B, 489 VL_4H, 490 VL_2S, 491 VL_1D, 492 493 VL_16B, 494 VL_8H, 495 VL_4S, 496 VL_2D, 497 498 // Bare layout for the 128-bit vector 499 // (only show ".b", ".h", ".s", ".d" without vector number) 500 VL_B, 501 VL_H, 502 VL_S, 503 VL_D 504 }; 505 } 506 507 inline static const char * 508 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) { 509 switch (Layout) { 510 case AArch64Layout::VL_8B: return ".8b"; 511 case AArch64Layout::VL_4H: return ".4h"; 512 case AArch64Layout::VL_2S: return ".2s"; 513 case AArch64Layout::VL_1D: return ".1d"; 514 case AArch64Layout::VL_16B: return ".16b"; 515 case AArch64Layout::VL_8H: return ".8h"; 516 case AArch64Layout::VL_4S: return ".4s"; 517 case AArch64Layout::VL_2D: return ".2d"; 518 case AArch64Layout::VL_B: return ".b"; 519 case AArch64Layout::VL_H: return ".h"; 520 case AArch64Layout::VL_S: return ".s"; 521 case AArch64Layout::VL_D: return ".d"; 522 default: llvm_unreachable("Unknown Vector Layout"); 523 } 524 } 525 526 inline static AArch64Layout::VectorLayout 527 AArch64StringToVectorLayout(StringRef LayoutStr) { 528 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr) 529 .Case(".8b", AArch64Layout::VL_8B) 530 .Case(".4h", AArch64Layout::VL_4H) 531 .Case(".2s", AArch64Layout::VL_2S) 532 .Case(".1d", AArch64Layout::VL_1D) 533 .Case(".16b", AArch64Layout::VL_16B) 534 .Case(".8h", AArch64Layout::VL_8H) 535 .Case(".4s", AArch64Layout::VL_4S) 536 .Case(".2d", AArch64Layout::VL_2D) 537 .Case(".b", AArch64Layout::VL_B) 538 .Case(".h", AArch64Layout::VL_H) 539 .Case(".s", AArch64Layout::VL_S) 540 .Case(".d", AArch64Layout::VL_D) 541 .Default(AArch64Layout::Invalid); 542 } 543 544 namespace AArch64SysReg { 545 enum SysRegROValues { 546 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 547 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 548 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 549 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 550 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 551 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 552 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 553 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 554 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 555 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 556 CTR_EL0 = 0xd801, // 11 011 0000 0000 001 557 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 558 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 559 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 560 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 561 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 562 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 563 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 564 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 565 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 566 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 567 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 568 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 569 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 570 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 571 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 572 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 573 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 574 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 575 ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 576 ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 577 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 578 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 579 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 580 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 581 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 582 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 583 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 584 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 585 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 586 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 587 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 588 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 589 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 590 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 591 ISR_EL1 = 0xc608, // 11 000 1100 0001 000 592 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 593 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 594 595 // Trace registers 596 TRCSTATR = 0x8818, // 10 001 0000 0011 000 597 TRCIDR8 = 0x8806, // 10 001 0000 0000 110 598 TRCIDR9 = 0x880e, // 10 001 0000 0001 110 599 TRCIDR10 = 0x8816, // 10 001 0000 0010 110 600 TRCIDR11 = 0x881e, // 10 001 0000 0011 110 601 TRCIDR12 = 0x8826, // 10 001 0000 0100 110 602 TRCIDR13 = 0x882e, // 10 001 0000 0101 110 603 TRCIDR0 = 0x8847, // 10 001 0000 1000 111 604 TRCIDR1 = 0x884f, // 10 001 0000 1001 111 605 TRCIDR2 = 0x8857, // 10 001 0000 1010 111 606 TRCIDR3 = 0x885f, // 10 001 0000 1011 111 607 TRCIDR4 = 0x8867, // 10 001 0000 1100 111 608 TRCIDR5 = 0x886f, // 10 001 0000 1101 111 609 TRCIDR6 = 0x8877, // 10 001 0000 1110 111 610 TRCIDR7 = 0x887f, // 10 001 0000 1111 111 611 TRCOSLSR = 0x888c, // 10 001 0001 0001 100 612 TRCPDSR = 0x88ac, // 10 001 0001 0101 100 613 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 614 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 615 TRCLSR = 0x8bee, // 10 001 0111 1101 110 616 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 617 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 618 TRCDEVID = 0x8b97, // 10 001 0111 0010 111 619 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 620 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 621 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 622 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 623 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 624 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 625 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 626 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 627 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 628 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 629 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 630 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 631 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 632 633 // GICv3 registers 634 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 635 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 636 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 637 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 638 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 639 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 640 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 641 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 642 }; 643 644 enum SysRegWOValues { 645 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 646 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 647 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 648 649 // Trace Registers 650 TRCOSLAR = 0x8884, // 10 001 0001 0000 100 651 TRCLAR = 0x8be6, // 10 001 0111 1100 110 652 653 // GICv3 registers 654 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 655 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 656 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 657 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 658 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 659 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 660 }; 661 662 enum SysRegValues { 663 Invalid = -1, // Op0 Op1 CRn CRm Op2 664 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 665 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 666 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 667 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 668 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 669 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 670 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 671 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 672 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 673 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 674 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 675 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 676 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 677 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 678 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 679 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 680 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 681 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 682 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 683 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 684 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 685 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 686 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 687 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 688 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 689 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 690 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 691 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 692 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 693 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 694 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 695 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 696 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 697 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 698 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 699 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 700 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 701 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 702 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 703 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 704 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 705 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 706 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 707 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 708 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 709 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 710 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 711 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 712 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 713 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 714 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 715 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 716 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 717 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 718 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 719 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 720 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 721 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 722 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 723 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 724 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 725 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 726 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 727 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 728 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 729 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 730 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 731 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 732 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 733 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 734 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 735 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 736 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 737 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 738 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 739 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 740 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 741 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 742 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 743 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 744 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 745 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 746 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 747 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 748 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 749 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 750 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 751 HCR_EL2 = 0xe088, // 11 100 0001 0001 000 752 SCR_EL3 = 0xf088, // 11 110 0001 0001 000 753 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 754 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 755 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 756 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 757 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 758 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 759 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 760 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 761 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 762 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 763 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 764 TCR_EL1 = 0xc102, // 11 000 0010 0000 010 765 TCR_EL2 = 0xe102, // 11 100 0010 0000 010 766 TCR_EL3 = 0xf102, // 11 110 0010 0000 010 767 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 768 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 769 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 770 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 771 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 772 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 773 ELR_EL1 = 0xc201, // 11 000 0100 0000 001 774 ELR_EL2 = 0xe201, // 11 100 0100 0000 001 775 ELR_EL3 = 0xf201, // 11 110 0100 0000 001 776 SP_EL0 = 0xc208, // 11 000 0100 0001 000 777 SP_EL1 = 0xe208, // 11 100 0100 0001 000 778 SP_EL2 = 0xf208, // 11 110 0100 0001 000 779 SPSel = 0xc210, // 11 000 0100 0010 000 780 NZCV = 0xda10, // 11 011 0100 0010 000 781 DAIF = 0xda11, // 11 011 0100 0010 001 782 CurrentEL = 0xc212, // 11 000 0100 0010 010 783 SPSR_irq = 0xe218, // 11 100 0100 0011 000 784 SPSR_abt = 0xe219, // 11 100 0100 0011 001 785 SPSR_und = 0xe21a, // 11 100 0100 0011 010 786 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 787 FPCR = 0xda20, // 11 011 0100 0100 000 788 FPSR = 0xda21, // 11 011 0100 0100 001 789 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 790 DLR_EL0 = 0xda29, // 11 011 0100 0101 001 791 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 792 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 793 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 794 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 795 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 796 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 797 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 798 ESR_EL1 = 0xc290, // 11 000 0101 0010 000 799 ESR_EL2 = 0xe290, // 11 100 0101 0010 000 800 ESR_EL3 = 0xf290, // 11 110 0101 0010 000 801 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 802 FAR_EL1 = 0xc300, // 11 000 0110 0000 000 803 FAR_EL2 = 0xe300, // 11 100 0110 0000 000 804 FAR_EL3 = 0xf300, // 11 110 0110 0000 000 805 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 806 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 807 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 808 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 809 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 810 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 811 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 812 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 813 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 814 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 815 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 816 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 817 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 818 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 819 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 820 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 821 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 822 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 823 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 824 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 825 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 826 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 827 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 828 RMR_EL1 = 0xc602, // 11 000 1100 0000 010 829 RMR_EL2 = 0xe602, // 11 100 1100 0000 010 830 RMR_EL3 = 0xf602, // 11 110 1100 0000 010 831 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 832 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 833 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 834 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 835 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 836 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 837 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 838 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 839 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 840 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 841 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 842 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 843 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 844 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 845 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 846 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 847 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 848 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 849 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 850 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 851 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 852 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 853 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 854 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 855 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 856 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 857 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 858 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 859 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 860 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 861 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 862 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 863 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 864 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 865 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 866 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 867 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 868 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 869 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 870 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 871 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 872 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 873 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 874 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 875 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 876 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 877 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 878 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 879 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 880 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 881 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 882 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 883 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 884 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 885 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 886 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 887 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 888 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 889 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 890 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 891 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 892 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 893 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 894 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 895 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 896 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 897 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 898 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 899 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 900 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 901 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 902 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 903 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 904 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 905 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 906 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 907 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 908 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 909 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 910 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 911 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 912 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 913 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 914 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 915 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 916 917 // Trace registers 918 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 919 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 920 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 921 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 922 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 923 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 924 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 925 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 926 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 927 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 928 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 929 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 930 TRCQCTLR = 0x8809, // 10 001 0000 0001 001 931 TRCVICTLR = 0x8802, // 10 001 0000 0000 010 932 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 933 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 934 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 935 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 936 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 937 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 938 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 939 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 940 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 941 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 942 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 943 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 944 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 945 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 946 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 947 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 948 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 949 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 950 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 951 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 952 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 953 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 954 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 955 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 956 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 957 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 958 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 959 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 960 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 961 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 962 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 963 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 964 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 965 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 966 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 967 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 968 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 969 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 970 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 971 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 972 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 973 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 974 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 975 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 976 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 977 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 978 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 979 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 980 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 981 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 982 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 983 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 984 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 985 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 986 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 987 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 988 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 989 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 990 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 991 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 992 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 993 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 994 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 995 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 996 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 997 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 998 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 999 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 1000 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 1001 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 1002 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 1003 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 1004 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 1005 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 1006 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 1007 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 1008 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 1009 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 1010 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 1011 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 1012 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 1013 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 1014 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 1015 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 1016 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 1017 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 1018 TRCPDCR = 0x88a4, // 10 001 0001 0100 100 1019 TRCACVR0 = 0x8900, // 10 001 0010 0000 000 1020 TRCACVR1 = 0x8910, // 10 001 0010 0010 000 1021 TRCACVR2 = 0x8920, // 10 001 0010 0100 000 1022 TRCACVR3 = 0x8930, // 10 001 0010 0110 000 1023 TRCACVR4 = 0x8940, // 10 001 0010 1000 000 1024 TRCACVR5 = 0x8950, // 10 001 0010 1010 000 1025 TRCACVR6 = 0x8960, // 10 001 0010 1100 000 1026 TRCACVR7 = 0x8970, // 10 001 0010 1110 000 1027 TRCACVR8 = 0x8901, // 10 001 0010 0000 001 1028 TRCACVR9 = 0x8911, // 10 001 0010 0010 001 1029 TRCACVR10 = 0x8921, // 10 001 0010 0100 001 1030 TRCACVR11 = 0x8931, // 10 001 0010 0110 001 1031 TRCACVR12 = 0x8941, // 10 001 0010 1000 001 1032 TRCACVR13 = 0x8951, // 10 001 0010 1010 001 1033 TRCACVR14 = 0x8961, // 10 001 0010 1100 001 1034 TRCACVR15 = 0x8971, // 10 001 0010 1110 001 1035 TRCACATR0 = 0x8902, // 10 001 0010 0000 010 1036 TRCACATR1 = 0x8912, // 10 001 0010 0010 010 1037 TRCACATR2 = 0x8922, // 10 001 0010 0100 010 1038 TRCACATR3 = 0x8932, // 10 001 0010 0110 010 1039 TRCACATR4 = 0x8942, // 10 001 0010 1000 010 1040 TRCACATR5 = 0x8952, // 10 001 0010 1010 010 1041 TRCACATR6 = 0x8962, // 10 001 0010 1100 010 1042 TRCACATR7 = 0x8972, // 10 001 0010 1110 010 1043 TRCACATR8 = 0x8903, // 10 001 0010 0000 011 1044 TRCACATR9 = 0x8913, // 10 001 0010 0010 011 1045 TRCACATR10 = 0x8923, // 10 001 0010 0100 011 1046 TRCACATR11 = 0x8933, // 10 001 0010 0110 011 1047 TRCACATR12 = 0x8943, // 10 001 0010 1000 011 1048 TRCACATR13 = 0x8953, // 10 001 0010 1010 011 1049 TRCACATR14 = 0x8963, // 10 001 0010 1100 011 1050 TRCACATR15 = 0x8973, // 10 001 0010 1110 011 1051 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 1052 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 1053 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 1054 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 1055 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 1056 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 1057 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 1058 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 1059 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 1060 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 1061 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 1062 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 1063 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 1064 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 1065 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 1066 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 1067 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 1068 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 1069 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 1070 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 1071 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 1072 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 1073 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 1074 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 1075 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 1076 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 1077 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 1078 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 1079 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 1080 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 1081 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 1082 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 1083 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 1084 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 1085 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 1086 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 1087 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 1088 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 1089 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 1090 1091 // GICv3 registers 1092 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 1093 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 1094 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 1095 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 1096 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 1097 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 1098 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 1099 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 1100 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 1101 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 1102 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 1103 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 1104 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 1105 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 1106 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 1107 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 1108 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 1109 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 1110 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 1111 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 1112 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 1113 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 1114 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 1115 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 1116 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 1117 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 1118 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 1119 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 1120 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 1121 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 1122 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 1123 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 1124 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 1125 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 1126 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 1127 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 1128 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 1129 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 1130 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 1131 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 1132 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 1133 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 1134 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 1135 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 1136 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 1137 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 1138 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 1139 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 1140 1141 // v8.1a "Privileged Access Never" extension-specific system registers 1142 PAN = 0xc213, // 11 000 0100 0010 011 1143 1144 // v8.1a "Limited Ordering Regions" extension-specific system registers 1145 LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 1146 LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 1147 LORN_EL1 = 0xc522, // 11 000 1010 0100 010 1148 LORC_EL1 = 0xc523, // 11 000 1010 0100 011 1149 LORID_EL1 = 0xc527, // 11 000 1010 0100 111 1150 1151 // v8.1a "Virtualization host extensions" system registers 1152 TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001 1153 CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001 1154 CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000 1155 CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010 1156 CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001 1157 SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000 1158 CPACR_EL12 = 0xe882, // 11 101 0001 0000 010 1159 TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000 1160 TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001 1161 TCR_EL12 = 0xe902, // 11 101 0010 0000 010 1162 AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000 1163 AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001 1164 ESR_EL12 = 0xea90, // 11 101 0101 0010 000 1165 FAR_EL12 = 0xeb00, // 11 101 0110 0000 000 1166 MAIR_EL12 = 0xed10, // 11 101 1010 0010 000 1167 AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000 1168 VBAR_EL12 = 0xee00, // 11 101 1100 0000 000 1169 CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001 1170 CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000 1171 CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000 1172 CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001 1173 CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010 1174 CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000 1175 CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001 1176 CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010 1177 SPSR_EL12 = 0xea00, // 11 101 0100 0000 000 1178 ELR_EL12 = 0xea01, // 11 101 0100 0000 001 1179 1180 // Cyclone specific system registers 1181 CPM_IOACC_CTL_EL3 = 0xff90, 1182 }; 1183 1184 // Note that these do not inherit from AArch64NamedImmMapper. This class is 1185 // sufficiently different in its behaviour that I don't believe it's worth 1186 // burdening the common AArch64NamedImmMapper with abstractions only needed in 1187 // this one case. 1188 struct SysRegMapper { 1189 static const AArch64NamedImmMapper::Mapping SysRegMappings[]; 1190 1191 const AArch64NamedImmMapper::Mapping *InstMappings; 1192 size_t NumInstMappings; 1193 1194 SysRegMapper() { } 1195 uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const; 1196 std::string toString(uint32_t Bits, uint64_t FeatureBits) const; 1197 }; 1198 1199 struct MSRMapper : SysRegMapper { 1200 static const AArch64NamedImmMapper::Mapping MSRMappings[]; 1201 MSRMapper(); 1202 }; 1203 1204 struct MRSMapper : SysRegMapper { 1205 static const AArch64NamedImmMapper::Mapping MRSMappings[]; 1206 MRSMapper(); 1207 }; 1208 1209 uint32_t ParseGenericRegister(StringRef Name, bool &Valid); 1210 } 1211 1212 namespace AArch64TLBI { 1213 enum TLBIValues { 1214 Invalid = -1, // Op0 Op1 CRn CRm Op2 1215 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 1216 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 1217 VMALLE1IS = 0x4418, // 01 000 1000 0011 000 1218 ALLE2IS = 0x6418, // 01 100 1000 0011 000 1219 ALLE3IS = 0x7418, // 01 110 1000 0011 000 1220 VAE1IS = 0x4419, // 01 000 1000 0011 001 1221 VAE2IS = 0x6419, // 01 100 1000 0011 001 1222 VAE3IS = 0x7419, // 01 110 1000 0011 001 1223 ASIDE1IS = 0x441a, // 01 000 1000 0011 010 1224 VAAE1IS = 0x441b, // 01 000 1000 0011 011 1225 ALLE1IS = 0x641c, // 01 100 1000 0011 100 1226 VALE1IS = 0x441d, // 01 000 1000 0011 101 1227 VALE2IS = 0x641d, // 01 100 1000 0011 101 1228 VALE3IS = 0x741d, // 01 110 1000 0011 101 1229 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 1230 VAALE1IS = 0x441f, // 01 000 1000 0011 111 1231 IPAS2E1 = 0x6421, // 01 100 1000 0100 001 1232 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 1233 VMALLE1 = 0x4438, // 01 000 1000 0111 000 1234 ALLE2 = 0x6438, // 01 100 1000 0111 000 1235 ALLE3 = 0x7438, // 01 110 1000 0111 000 1236 VAE1 = 0x4439, // 01 000 1000 0111 001 1237 VAE2 = 0x6439, // 01 100 1000 0111 001 1238 VAE3 = 0x7439, // 01 110 1000 0111 001 1239 ASIDE1 = 0x443a, // 01 000 1000 0111 010 1240 VAAE1 = 0x443b, // 01 000 1000 0111 011 1241 ALLE1 = 0x643c, // 01 100 1000 0111 100 1242 VALE1 = 0x443d, // 01 000 1000 0111 101 1243 VALE2 = 0x643d, // 01 100 1000 0111 101 1244 VALE3 = 0x743d, // 01 110 1000 0111 101 1245 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 1246 VAALE1 = 0x443f // 01 000 1000 0111 111 1247 }; 1248 1249 struct TLBIMapper : AArch64NamedImmMapper { 1250 const static Mapping TLBIMappings[]; 1251 1252 TLBIMapper(); 1253 }; 1254 1255 static inline bool NeedsRegister(TLBIValues Val) { 1256 switch (Val) { 1257 case VMALLE1IS: 1258 case ALLE2IS: 1259 case ALLE3IS: 1260 case ALLE1IS: 1261 case VMALLS12E1IS: 1262 case VMALLE1: 1263 case ALLE2: 1264 case ALLE3: 1265 case ALLE1: 1266 case VMALLS12E1: 1267 return false; 1268 default: 1269 return true; 1270 } 1271 } 1272 } 1273 1274 namespace AArch64II { 1275 /// Target Operand Flag enum. 1276 enum TOF { 1277 //===------------------------------------------------------------------===// 1278 // AArch64 Specific MachineOperand flags. 1279 1280 MO_NO_FLAG, 1281 1282 MO_FRAGMENT = 0xf, 1283 1284 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 1285 /// offset of the 4K page containing the symbol. This is used with the 1286 /// ADRP instruction. 1287 MO_PAGE = 1, 1288 1289 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 1290 /// that symbol within a 4K page. This offset is added to the page address 1291 /// to produce the complete address. 1292 MO_PAGEOFF = 2, 1293 1294 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 1295 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 1296 MO_G3 = 3, 1297 1298 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 1299 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 1300 MO_G2 = 4, 1301 1302 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 1303 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 1304 MO_G1 = 5, 1305 1306 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 1307 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 1308 MO_G0 = 6, 1309 1310 /// MO_HI12 - This flag indicates that a symbol operand represents the bits 1311 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- 1312 /// by-12-bits instruction. 1313 MO_HI12 = 7, 1314 1315 /// MO_GOT - This flag indicates that a symbol operand represents the 1316 /// address of the GOT entry for the symbol, rather than the address of 1317 /// the symbol itself. 1318 MO_GOT = 0x10, 1319 1320 /// MO_NC - Indicates whether the linker is expected to check the symbol 1321 /// reference for overflow. For example in an ADRP/ADD pair of relocations 1322 /// the ADRP usually does check, but not the ADD. 1323 MO_NC = 0x20, 1324 1325 /// MO_TLS - Indicates that the operand being accessed is some kind of 1326 /// thread-local symbol. On Darwin, only one type of thread-local access 1327 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 1328 /// referee will affect interpretation. 1329 MO_TLS = 0x40, 1330 1331 /// MO_CONSTPOOL - This flag indicates that a symbol operand represents 1332 /// the address of a constant pool entry for the symbol, rather than the 1333 /// address of the symbol itself. 1334 MO_CONSTPOOL = 0x80 1335 }; 1336 } // end namespace AArch64II 1337 1338 } // end namespace llvm 1339 1340 #endif 1341
