| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
108 unsigned PredReg = 0;
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
223 ARMCC::CondCodes Pred, unsigned PredReg,
228 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
252 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
261 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
267 .addImm((unsigned)Pred).addReg(PredReg).addReg(0
[all...] |
| MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg();
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 171 unsigned PredReg = 0;
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 396 unsigned PredReg, unsigned MIFlags) const {
407 .addImm(0).addImm(Pred).addReg(PredReg)
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
755 Offset, Pred, PredReg, TII);
759 Offset, Pred, PredReg, TII);
|
| ARMExpandPseudoInsts.cpp | [all...] |
| Thumb2SizeReduction.cpp | 581 unsigned PredReg = 0;
582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
685 unsigned PredReg = 0;
686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
782 unsigned PredReg = 0;
783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMFrameLowering.cpp | 120 unsigned PredReg = 0) {
123 Pred, PredReg, TII, MIFlags);
126 Pred, PredReg, TII, MIFlags);
134 unsigned PredReg = 0) {
136 MIFlags, Pred, PredReg);
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 104 ARMCC::CondCodes Pred, unsigned PredReg);
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
121 unsigned PredReg,
127 ARMCC::CondCodes Pred, unsigned PredReg,
382 ARMCC::CondCodes Pred, unsigned PredReg) {
451 .addImm(Pred).addReg(PredReg);
470 .addImm(Pred).addReg(PredReg);
482 unsigned PredReg, unsigned Scratch, DebugLoc dl,
590 .addImm(Pred).addReg(PredReg);
600 .addImm(Pred).addReg(PredReg);
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 495 unsigned PredReg = Cond[Cond.size()-1].getReg();
496 MachineInstr *CondI = MRI->getVRegDef(PredReg);
[all...] |
