| /external/v8/test/mjsunit/compiler/ |
| rotate.js | 47 function ROR(x, sa) {
67 assertEquals(1 << ((2 % 32)), ROR(1, 30));
68 assertEquals(1 << ((2 % 32)), ROR(1, 30));
69 %OptimizeFunctionOnNextCall(ROR);
70 assertEquals(1 << ((2 % 32)), ROR(1, 30));
|
| /art/compiler/utils/arm/ |
| assembler_arm32_test.cc | 165 arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR, arm::Shift::ROR, arm::Shift::RRX
201 arm::Shift::ROR };
|
| constants_arm.h | 154 ROR = 3, // Rotate right
|
| /external/lldb/source/Plugins/Process/Utility/ |
| ARMUtils.h | 190 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, bool *success)
283 static uint32_t ror(uint32_t val, uint32_t N, uint32_t shift) function in namespace:lldb_private
302 imm32 = ror(imm, 32, amt);
350 imm32 = ror(unrotated_value, 32, bits(imm12, 11, 7));
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 37 ROR,
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
94 /// 011 ==> ror
107 case AArch64_AM::ROR: STEnc = 3; break;
205 static inline uint64_t ror(uint64_t elt, unsigned size) { function in namespace:llvm::AArch64_AM
307 pattern = ror(pattern, size);
|
| /external/v8/src/arm/ |
| constants-arm.h | 232 ROR = 3 << 5, // Rotate right.
234 // RRX is encoded as ROR with shift_imm == 0.
237 // detect it and emit the correct ROR shift operand with shift_imm == 0.
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 471 ROR,
[all...] |
| /external/v8/src/arm64/ |
| constants-arm64.h | 337 ROR = 0x3
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 64 (ror x12, x12, #3; ror x12, x12, #13
65 ror x12, x12, #51; ror x12, x12, #61)
[all...] |
| /external/vixl/src/vixl/a64/ |
| constants-a64.h | 270 ROR = 0x3,
[all...] |
