| /external/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
22 unsigned SlotSize = RegInfo->getSlotSize();
24 RegInfo->X86RegisterInfo::getCalleeSavedRegs(MF);
|
| X86FrameLowering.cpp | 77 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
80 RegInfo->needsStackRealignment(MF) ||
472 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
473 unsigned SlotSize = RegInfo->getSlotSize();
574 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
591 unsigned SlotSize = RegInfo->getSlotSize();
592 unsigned FramePtr = RegInfo->getFrameRegister(MF);
597 unsigned StackPtr = RegInfo->getStackRegister();
598 unsigned BasePtr = RegInfo->getBaseRegister();
626 !RegInfo->needsStackRealignment(MF) &
[all...] |
| X86CallFrameOptimization.cpp | 246 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
248 unsigned StackPtr = RegInfo.getStackRegister();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo;
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
|
| NVPTXPrologEpilogPass.cpp | 113 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
213 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CleanupLocalDynamicTLSPass.cpp | 116 MachineRegisterInfo &RegInfo = MF->getRegInfo();
117 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
|
| AArch64FrameLowering.cpp | 142 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
145 MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF));
258 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
392 if (RegInfo->hasBasePointer(MF)) {
393 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
400 unsigned FramePtr = RegInfo->getFrameRegister(MF);
469 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
477 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
537 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
599 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZLDCleanup.cpp | 132 MachineRegisterInfo &RegInfo = MF->getRegInfo();
133 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 173 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
174 unsigned Reg = RegInfo.createVirtualRegister(RC);
|
| Mips16ISelDAGToDAG.cpp | 74 MachineRegisterInfo &RegInfo = MF.getRegInfo();
80 V0 = RegInfo.createVirtualRegister(RC);
81 V1 = RegInfo.createVirtualRegister(RC);
82 V2 = RegInfo.createVirtualRegister(RC);
|
| MipsSEFrameLowering.cpp | 76 const MipsRegisterInfo &RegInfo;
84 RegInfo(*Subtarget.getRegisterInfo()) {}
155 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
176 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
192 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
193 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0)
[all...] |
| MipsSEInstrInfo.cpp | 386 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
403 unsigned Reg = RegInfo.createVirtualRegister(RC);
|
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 58 MachineRegisterInfo *RegInfo;
|
| MachineFunction.h | 93 // RegInfo - Information about each register in use in the function.
94 MachineRegisterInfo *RegInfo;
188 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
189 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
|
| SelectionDAGISel.h | 48 MachineRegisterInfo *RegInfo;
|
| /external/llvm/lib/CodeGen/ |
| GCRootLowering.cpp | 341 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
343 RegInfo->needsStackRealignment(MF);
|
| StackMaps.cpp | 328 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
330 RegInfo->needsStackRealignment(*(AP.MF));
|
| MachineBasicBlock.cpp | 81 // Make sure the instructions have their operands in the reginfo lists.
82 MachineRegisterInfo &RegInfo = MF.getRegInfo();
85 I->AddRegOperandsToUseLists(RegInfo);
[all...] |
| MachineFunction.cpp | 60 RegInfo = new (Allocator) MachineRegisterInfo(this);
62 RegInfo = nullptr;
96 if (RegInfo) {
97 RegInfo->~MachineRegisterInfo();
98 Allocator.Deallocate(RegInfo);
336 if (RegInfo) {
337 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
338 if (!RegInfo->tracksLiveness())
355 if (RegInfo && !RegInfo->livein_empty())
[all...] |
| PrologEpilogInserter.cpp | 291 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
296 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
320 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) {
335 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
338 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
567 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
570 RegInfo->useFPForScavengingIndex(Fn) &&
571 !RegInfo->needsStackRealignment(Fn));
699 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 56 const ThumbRegisterInfo *RegInfo =
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
92 const ThumbRegisterInfo *RegInfo =
103 unsigned FramePtr = RegInfo->getFrameRegister(MF);
104 unsigned BasePtr = RegInfo->getBaseRegister();
117 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
265 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
287 if (RegInfo->needsStackRealignment(MF)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 434 MachineRegisterInfo &RegInfo = MF->getRegInfo();
438 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 72 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
73 return *(RegInfo->getRegClass(RC).begin() + RegNo);
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 203 MachineRegisterInfo &RegInfo = MF.getRegInfo();
221 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
222 RegInfo.addLiveIn(VA.getLocReg(), VReg);
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 454 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
455 return *(RegInfo->getRegClass(RC).begin() + RegNo);
[all...] |
