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      1 //===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the CCState and CCValAssign classes, used for lowering
     11 // and implementing calling conventions.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
     16 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
     17 
     18 #include "llvm/ADT/SmallVector.h"
     19 #include "llvm/CodeGen/MachineFrameInfo.h"
     20 #include "llvm/CodeGen/MachineFunction.h"
     21 #include "llvm/IR/CallingConv.h"
     22 #include "llvm/Target/TargetCallingConv.h"
     23 
     24 namespace llvm {
     25 class CCState;
     26 class MVT;
     27 class TargetMachine;
     28 class TargetRegisterInfo;
     29 
     30 /// CCValAssign - Represent assignment of one arg/retval to a location.
     31 class CCValAssign {
     32 public:
     33   enum LocInfo {
     34     Full,      // The value fills the full location.
     35     SExt,      // The value is sign extended in the location.
     36     ZExt,      // The value is zero extended in the location.
     37     AExt,      // The value is extended with undefined upper bits.
     38     SExtUpper, // The value is in the upper bits of the location and should be
     39                // sign extended when retrieved.
     40     ZExtUpper, // The value is in the upper bits of the location and should be
     41                // zero extended when retrieved.
     42     AExtUpper, // The value is in the upper bits of the location and should be
     43                // extended with undefined upper bits when retrieved.
     44     BCvt,      // The value is bit-converted in the location.
     45     VExt,      // The value is vector-widened in the location.
     46                // FIXME: Not implemented yet. Code that uses AExt to mean
     47                // vector-widen should be fixed to use VExt instead.
     48     FPExt,     // The floating-point value is fp-extended in the location.
     49     Indirect   // The location contains pointer to the value.
     50     // TODO: a subset of the value is in the location.
     51   };
     52 
     53 private:
     54   /// ValNo - This is the value number begin assigned (e.g. an argument number).
     55   unsigned ValNo;
     56 
     57   /// Loc is either a stack offset or a register number.
     58   unsigned Loc;
     59 
     60   /// isMem - True if this is a memory loc, false if it is a register loc.
     61   unsigned isMem : 1;
     62 
     63   /// isCustom - True if this arg/retval requires special handling.
     64   unsigned isCustom : 1;
     65 
     66   /// Information about how the value is assigned.
     67   LocInfo HTP : 6;
     68 
     69   /// ValVT - The type of the value being assigned.
     70   MVT ValVT;
     71 
     72   /// LocVT - The type of the location being assigned to.
     73   MVT LocVT;
     74 public:
     75 
     76   static CCValAssign getReg(unsigned ValNo, MVT ValVT,
     77                             unsigned RegNo, MVT LocVT,
     78                             LocInfo HTP) {
     79     CCValAssign Ret;
     80     Ret.ValNo = ValNo;
     81     Ret.Loc = RegNo;
     82     Ret.isMem = false;
     83     Ret.isCustom = false;
     84     Ret.HTP = HTP;
     85     Ret.ValVT = ValVT;
     86     Ret.LocVT = LocVT;
     87     return Ret;
     88   }
     89 
     90   static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
     91                                   unsigned RegNo, MVT LocVT,
     92                                   LocInfo HTP) {
     93     CCValAssign Ret;
     94     Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
     95     Ret.isCustom = true;
     96     return Ret;
     97   }
     98 
     99   static CCValAssign getMem(unsigned ValNo, MVT ValVT,
    100                             unsigned Offset, MVT LocVT,
    101                             LocInfo HTP) {
    102     CCValAssign Ret;
    103     Ret.ValNo = ValNo;
    104     Ret.Loc = Offset;
    105     Ret.isMem = true;
    106     Ret.isCustom = false;
    107     Ret.HTP = HTP;
    108     Ret.ValVT = ValVT;
    109     Ret.LocVT = LocVT;
    110     return Ret;
    111   }
    112 
    113   static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
    114                                   unsigned Offset, MVT LocVT,
    115                                   LocInfo HTP) {
    116     CCValAssign Ret;
    117     Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
    118     Ret.isCustom = true;
    119     return Ret;
    120   }
    121 
    122   // There is no need to differentiate between a pending CCValAssign and other
    123   // kinds, as they are stored in a different list.
    124   static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
    125                                 LocInfo HTP, unsigned ExtraInfo = 0) {
    126     return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
    127   }
    128 
    129   void convertToReg(unsigned RegNo) {
    130     Loc = RegNo;
    131     isMem = false;
    132   }
    133 
    134   void convertToMem(unsigned Offset) {
    135     Loc = Offset;
    136     isMem = true;
    137   }
    138 
    139   unsigned getValNo() const { return ValNo; }
    140   MVT getValVT() const { return ValVT; }
    141 
    142   bool isRegLoc() const { return !isMem; }
    143   bool isMemLoc() const { return isMem; }
    144 
    145   bool needsCustom() const { return isCustom; }
    146 
    147   unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
    148   unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
    149   unsigned getExtraInfo() const { return Loc; }
    150   MVT getLocVT() const { return LocVT; }
    151 
    152   LocInfo getLocInfo() const { return HTP; }
    153   bool isExtInLoc() const {
    154     return (HTP == AExt || HTP == SExt || HTP == ZExt);
    155   }
    156 
    157   bool isUpperBitsInLoc() const {
    158     return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
    159   }
    160 };
    161 
    162 /// Describes a register that needs to be forwarded from the prologue to a
    163 /// musttail call.
    164 struct ForwardedRegister {
    165   ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
    166       : VReg(VReg), PReg(PReg), VT(VT) {}
    167   unsigned VReg;
    168   MCPhysReg PReg;
    169   MVT VT;
    170 };
    171 
    172 /// CCAssignFn - This function assigns a location for Val, updating State to
    173 /// reflect the change.  It returns 'true' if it failed to handle Val.
    174 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
    175                         MVT LocVT, CCValAssign::LocInfo LocInfo,
    176                         ISD::ArgFlagsTy ArgFlags, CCState &State);
    177 
    178 /// CCCustomFn - This function assigns a location for Val, possibly updating
    179 /// all args to reflect changes and indicates if it handled it. It must set
    180 /// isCustom if it handles the arg and returns true.
    181 typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
    182                         MVT &LocVT, CCValAssign::LocInfo &LocInfo,
    183                         ISD::ArgFlagsTy &ArgFlags, CCState &State);
    184 
    185 /// ParmContext - This enum tracks whether calling convention lowering is in
    186 /// the context of prologue or call generation. Not all backends make use of
    187 /// this information.
    188 typedef enum { Unknown, Prologue, Call } ParmContext;
    189 
    190 /// CCState - This class holds information needed while lowering arguments and
    191 /// return values.  It captures which registers are already assigned and which
    192 /// stack slots are used.  It provides accessors to allocate these values.
    193 class CCState {
    194 private:
    195   CallingConv::ID CallingConv;
    196   bool IsVarArg;
    197   MachineFunction &MF;
    198   const TargetRegisterInfo &TRI;
    199   SmallVectorImpl<CCValAssign> &Locs;
    200   LLVMContext &Context;
    201 
    202   unsigned StackOffset;
    203   SmallVector<uint32_t, 16> UsedRegs;
    204   SmallVector<CCValAssign, 4> PendingLocs;
    205 
    206   // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
    207   //
    208   // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
    209   // tracking.
    210   // Or, in another words it tracks byval parameters that are stored in
    211   // general purpose registers.
    212   //
    213   // For 4 byte stack alignment,
    214   // instance index means byval parameter number in formal
    215   // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
    216   // then, for function "foo":
    217   //
    218   // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
    219   //
    220   // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
    221   // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
    222   //
    223   // In case of 8 bytes stack alignment,
    224   // ByValRegs may also contain information about wasted registers.
    225   // In function shown above, r3 would be wasted according to AAPCS rules.
    226   // And in that case ByValRegs[1].Waste would be "true".
    227   // ByValRegs vector size still would be 2,
    228   // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
    229   //
    230   // Supposed use-case for this collection:
    231   // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
    232   // 2. HandleByVal fillups ByValRegs.
    233   // 3. Argument analysis (LowerFormatArguments, for example). After
    234   // some byval argument was analyzed, InRegsParamsProcessed is increased.
    235   struct ByValInfo {
    236     ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
    237       Begin(B), End(E), Waste(IsWaste) {}
    238     // First register allocated for current parameter.
    239     unsigned Begin;
    240 
    241     // First after last register allocated for current parameter.
    242     unsigned End;
    243 
    244     // Means that current range of registers doesn't belong to any
    245     // parameters. It was wasted due to stack alignment rules.
    246     // For more information see:
    247     // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
    248     bool Waste;
    249   };
    250   SmallVector<ByValInfo, 4 > ByValRegs;
    251 
    252   // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
    253   // during argument analysis.
    254   unsigned InRegsParamsProcessed;
    255 
    256 protected:
    257   ParmContext CallOrPrologue;
    258 
    259 public:
    260   CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
    261           SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
    262 
    263   void addLoc(const CCValAssign &V) {
    264     Locs.push_back(V);
    265   }
    266 
    267   LLVMContext &getContext() const { return Context; }
    268   MachineFunction &getMachineFunction() const { return MF; }
    269   CallingConv::ID getCallingConv() const { return CallingConv; }
    270   bool isVarArg() const { return IsVarArg; }
    271 
    272   unsigned getNextStackOffset() const { return StackOffset; }
    273 
    274   /// isAllocated - Return true if the specified register (or an alias) is
    275   /// allocated.
    276   bool isAllocated(unsigned Reg) const {
    277     return UsedRegs[Reg/32] & (1 << (Reg&31));
    278   }
    279 
    280   /// AnalyzeFormalArguments - Analyze an array of argument values,
    281   /// incorporating info about the formals into this state.
    282   void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
    283                               CCAssignFn Fn);
    284 
    285   /// AnalyzeReturn - Analyze the returned values of a return,
    286   /// incorporating info about the result values into this state.
    287   void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
    288                      CCAssignFn Fn);
    289 
    290   /// CheckReturn - Analyze the return values of a function, returning
    291   /// true if the return can be performed without sret-demotion, and
    292   /// false otherwise.
    293   bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
    294                    CCAssignFn Fn);
    295 
    296   /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
    297   /// incorporating info about the passed values into this state.
    298   void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
    299                            CCAssignFn Fn);
    300 
    301   /// AnalyzeCallOperands - Same as above except it takes vectors of types
    302   /// and argument flags.
    303   void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
    304                            SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
    305                            CCAssignFn Fn);
    306 
    307   /// AnalyzeCallResult - Analyze the return values of a call,
    308   /// incorporating info about the passed values into this state.
    309   void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
    310                          CCAssignFn Fn);
    311 
    312   /// AnalyzeCallResult - Same as above except it's specialized for calls which
    313   /// produce a single value.
    314   void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
    315 
    316   /// getFirstUnallocated - Return the index of the first unallocated register
    317   /// in the set, or Regs.size() if they are all allocated.
    318   unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
    319     for (unsigned i = 0; i < Regs.size(); ++i)
    320       if (!isAllocated(Regs[i]))
    321         return i;
    322     return Regs.size();
    323   }
    324 
    325   /// AllocateReg - Attempt to allocate one register.  If it is not available,
    326   /// return zero.  Otherwise, return the register, marking it and any aliases
    327   /// as allocated.
    328   unsigned AllocateReg(unsigned Reg) {
    329     if (isAllocated(Reg)) return 0;
    330     MarkAllocated(Reg);
    331     return Reg;
    332   }
    333 
    334   /// Version of AllocateReg with extra register to be shadowed.
    335   unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
    336     if (isAllocated(Reg)) return 0;
    337     MarkAllocated(Reg);
    338     MarkAllocated(ShadowReg);
    339     return Reg;
    340   }
    341 
    342   /// AllocateReg - Attempt to allocate one of the specified registers.  If none
    343   /// are available, return zero.  Otherwise, return the first one available,
    344   /// marking it and any aliases as allocated.
    345   unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
    346     unsigned FirstUnalloc = getFirstUnallocated(Regs);
    347     if (FirstUnalloc == Regs.size())
    348       return 0;    // Didn't find the reg.
    349 
    350     // Mark the register and any aliases as allocated.
    351     unsigned Reg = Regs[FirstUnalloc];
    352     MarkAllocated(Reg);
    353     return Reg;
    354   }
    355 
    356   /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
    357   /// registers. If this is not possible, return zero. Otherwise, return the first
    358   /// register of the block that were allocated, marking the entire block as allocated.
    359   unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) {
    360     if (RegsRequired > Regs.size())
    361       return 0;
    362 
    363     for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
    364          ++StartIdx) {
    365       bool BlockAvailable = true;
    366       // Check for already-allocated regs in this block
    367       for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
    368         if (isAllocated(Regs[StartIdx + BlockIdx])) {
    369           BlockAvailable = false;
    370           break;
    371         }
    372       }
    373       if (BlockAvailable) {
    374         // Mark the entire block as allocated
    375         for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
    376           MarkAllocated(Regs[StartIdx + BlockIdx]);
    377         }
    378         return Regs[StartIdx];
    379       }
    380     }
    381     // No block was available
    382     return 0;
    383   }
    384 
    385   /// Version of AllocateReg with list of registers to be shadowed.
    386   unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
    387     unsigned FirstUnalloc = getFirstUnallocated(Regs);
    388     if (FirstUnalloc == Regs.size())
    389       return 0;    // Didn't find the reg.
    390 
    391     // Mark the register and any aliases as allocated.
    392     unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
    393     MarkAllocated(Reg);
    394     MarkAllocated(ShadowReg);
    395     return Reg;
    396   }
    397 
    398   /// AllocateStack - Allocate a chunk of stack space with the specified size
    399   /// and alignment.
    400   unsigned AllocateStack(unsigned Size, unsigned Align) {
    401     assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
    402     StackOffset = ((StackOffset + Align - 1) & ~(Align - 1));
    403     unsigned Result = StackOffset;
    404     StackOffset += Size;
    405     MF.getFrameInfo()->ensureMaxAlignment(Align);
    406     return Result;
    407   }
    408 
    409   /// Version of AllocateStack with extra register to be shadowed.
    410   unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
    411     MarkAllocated(ShadowReg);
    412     return AllocateStack(Size, Align);
    413   }
    414 
    415   /// Version of AllocateStack with list of extra registers to be shadowed.
    416   /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
    417   unsigned AllocateStack(unsigned Size, unsigned Align,
    418                          ArrayRef<MCPhysReg> ShadowRegs) {
    419     for (unsigned i = 0; i < ShadowRegs.size(); ++i)
    420       MarkAllocated(ShadowRegs[i]);
    421     return AllocateStack(Size, Align);
    422   }
    423 
    424   // HandleByVal - Allocate a stack slot large enough to pass an argument by
    425   // value. The size and alignment information of the argument is encoded in its
    426   // parameter attribute.
    427   void HandleByVal(unsigned ValNo, MVT ValVT,
    428                    MVT LocVT, CCValAssign::LocInfo LocInfo,
    429                    int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
    430 
    431   // Returns count of byval arguments that are to be stored (even partly)
    432   // in registers.
    433   unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
    434 
    435   // Returns count of byval in-regs arguments proceed.
    436   unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
    437 
    438   // Get information about N-th byval parameter that is stored in registers.
    439   // Here "ByValParamIndex" is N.
    440   void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
    441                           unsigned& BeginReg, unsigned& EndReg) const {
    442     assert(InRegsParamRecordIndex < ByValRegs.size() &&
    443            "Wrong ByVal parameter index");
    444 
    445     const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
    446     BeginReg = info.Begin;
    447     EndReg = info.End;
    448   }
    449 
    450   // Add information about parameter that is kept in registers.
    451   void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
    452     ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
    453   }
    454 
    455   // Goes either to next byval parameter (excluding "waste" record), or
    456   // to the end of collection.
    457   // Returns false, if end is reached.
    458   bool nextInRegsParam() {
    459     unsigned e = ByValRegs.size();
    460     if (InRegsParamsProcessed < e)
    461       ++InRegsParamsProcessed;
    462     return InRegsParamsProcessed < e;
    463   }
    464 
    465   // Clear byval registers tracking info.
    466   void clearByValRegsInfo() {
    467     InRegsParamsProcessed = 0;
    468     ByValRegs.clear();
    469   }
    470 
    471   // Rewind byval registers tracking info.
    472   void rewindByValRegsInfo() {
    473     InRegsParamsProcessed = 0;
    474   }
    475 
    476   ParmContext getCallOrPrologue() const { return CallOrPrologue; }
    477 
    478   // Get list of pending assignments
    479   SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() {
    480     return PendingLocs;
    481   }
    482 
    483   /// Compute the remaining unused register parameters that would be used for
    484   /// the given value type. This is useful when varargs are passed in the
    485   /// registers that normal prototyped parameters would be passed in, or for
    486   /// implementing perfect forwarding.
    487   void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
    488                                    CCAssignFn Fn);
    489 
    490   /// Compute the set of registers that need to be preserved and forwarded to
    491   /// any musttail calls.
    492   void analyzeMustTailForwardedRegisters(
    493       SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
    494       CCAssignFn Fn);
    495 
    496 private:
    497   /// MarkAllocated - Mark a register and all of its aliases as allocated.
    498   void MarkAllocated(unsigned Reg);
    499 };
    500 
    501 
    502 
    503 } // end namespace llvm
    504 
    505 #endif
    506