1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Sparc uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 17 18 #include "Sparc.h" 19 #include "llvm/Target/TargetLowering.h" 20 21 namespace llvm { 22 class SparcSubtarget; 23 24 namespace SPISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 CMPICC, // Compare two GPR operands, set icc+xcc. 28 CMPFCC, // Compare two FP operands, set fcc. 29 BRICC, // Branch to dest on icc condition 30 BRXCC, // Branch to dest on xcc condition (64-bit only). 31 BRFCC, // Branch to dest on fcc condition 32 SELECT_ICC, // Select between two values using the current ICC flags. 33 SELECT_XCC, // Select between two values using the current XCC flags. 34 SELECT_FCC, // Select between two values using the current FCC flags. 35 36 Hi, Lo, // Hi/Lo operations, typically on a global address. 37 38 FTOI, // FP to Int within a FP register. 39 ITOF, // Int to FP within a FP register. 40 FTOX, // FP to Int64 within a FP register. 41 XTOF, // Int64 to FP within a FP register. 42 43 CALL, // A call instruction. 44 RET_FLAG, // Return with a flag operand. 45 GLOBAL_BASE_REG, // Global base reg for PIC. 46 FLUSHW, // FLUSH register windows to stack. 47 48 TLS_ADD, // For Thread Local Storage (TLS). 49 TLS_LD, 50 TLS_CALL 51 }; 52 } 53 54 class SparcTargetLowering : public TargetLowering { 55 const SparcSubtarget *Subtarget; 56 public: 57 SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI); 58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 59 60 /// computeKnownBitsForTargetNode - Determine which of the bits specified 61 /// in Mask are known to be either zero or one and return them in the 62 /// KnownZero/KnownOne bitsets. 63 void computeKnownBitsForTargetNode(const SDValue Op, 64 APInt &KnownZero, 65 APInt &KnownOne, 66 const SelectionDAG &DAG, 67 unsigned Depth = 0) const override; 68 69 MachineBasicBlock * 70 EmitInstrWithCustomInserter(MachineInstr *MI, 71 MachineBasicBlock *MBB) const override; 72 73 const char *getTargetNodeName(unsigned Opcode) const override; 74 75 ConstraintType getConstraintType(const std::string &Constraint) const override; 76 ConstraintWeight 77 getSingleConstraintMatchWeight(AsmOperandInfo &info, 78 const char *constraint) const override; 79 void LowerAsmOperandForConstraint(SDValue Op, 80 std::string &Constraint, 81 std::vector<SDValue> &Ops, 82 SelectionDAG &DAG) const override; 83 std::pair<unsigned, const TargetRegisterClass *> 84 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 85 const std::string &Constraint, 86 MVT VT) const override; 87 88 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 89 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 90 91 /// getSetCCResultType - Return the ISD::SETCC ValueType 92 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 93 94 SDValue 95 LowerFormalArguments(SDValue Chain, 96 CallingConv::ID CallConv, 97 bool isVarArg, 98 const SmallVectorImpl<ISD::InputArg> &Ins, 99 SDLoc dl, SelectionDAG &DAG, 100 SmallVectorImpl<SDValue> &InVals) const override; 101 SDValue LowerFormalArguments_32(SDValue Chain, 102 CallingConv::ID CallConv, 103 bool isVarArg, 104 const SmallVectorImpl<ISD::InputArg> &Ins, 105 SDLoc dl, SelectionDAG &DAG, 106 SmallVectorImpl<SDValue> &InVals) const; 107 SDValue LowerFormalArguments_64(SDValue Chain, 108 CallingConv::ID CallConv, 109 bool isVarArg, 110 const SmallVectorImpl<ISD::InputArg> &Ins, 111 SDLoc dl, SelectionDAG &DAG, 112 SmallVectorImpl<SDValue> &InVals) const; 113 114 SDValue 115 LowerCall(TargetLowering::CallLoweringInfo &CLI, 116 SmallVectorImpl<SDValue> &InVals) const override; 117 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 118 SmallVectorImpl<SDValue> &InVals) const; 119 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 120 SmallVectorImpl<SDValue> &InVals) const; 121 122 SDValue 123 LowerReturn(SDValue Chain, 124 CallingConv::ID CallConv, bool isVarArg, 125 const SmallVectorImpl<ISD::OutputArg> &Outs, 126 const SmallVectorImpl<SDValue> &OutVals, 127 SDLoc dl, SelectionDAG &DAG) const override; 128 SDValue LowerReturn_32(SDValue Chain, 129 CallingConv::ID CallConv, bool IsVarArg, 130 const SmallVectorImpl<ISD::OutputArg> &Outs, 131 const SmallVectorImpl<SDValue> &OutVals, 132 SDLoc DL, SelectionDAG &DAG) const; 133 SDValue LowerReturn_64(SDValue Chain, 134 CallingConv::ID CallConv, bool IsVarArg, 135 const SmallVectorImpl<ISD::OutputArg> &Outs, 136 const SmallVectorImpl<SDValue> &OutVals, 137 SDLoc DL, SelectionDAG &DAG) const; 138 139 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 141 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 142 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 143 144 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 145 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 146 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 147 SelectionDAG &DAG) const; 148 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 149 150 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 151 SDValue Arg, SDLoc DL, 152 SelectionDAG &DAG) const; 153 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 154 const char *LibFuncName, 155 unsigned numArgs) const; 156 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, 157 unsigned &SPCC, 158 SDLoc DL, 159 SelectionDAG &DAG) const; 160 161 bool ShouldShrinkFPConstant(EVT VT) const override { 162 // Do not shrink FP constpool if VT == MVT::f128. 163 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 164 return VT != MVT::f128; 165 } 166 167 void ReplaceNodeResults(SDNode *N, 168 SmallVectorImpl<SDValue>& Results, 169 SelectionDAG &DAG) const override; 170 171 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, 172 unsigned BROpcode) const; 173 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI, 174 MachineBasicBlock *BB, 175 unsigned Opcode, 176 unsigned CondCode = 0) const; 177 }; 178 } // end namespace llvm 179 180 #endif // SPARC_ISELLOWERING_H 181
