1 /* 2 * Southern Islands Register documentation 3 * 4 * Copyright (C) 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef SID_H 25 #define SID_H 26 27 /* si values */ 28 #define SI_CONFIG_REG_OFFSET 0x00008000 29 #define SI_CONFIG_REG_END 0x0000B000 30 #define SI_SH_REG_OFFSET 0x0000B000 31 #define SI_SH_REG_END 0x0000C000 32 #define SI_CONTEXT_REG_OFFSET 0x00028000 33 #define SI_CONTEXT_REG_END 0x00029000 34 35 #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 36 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 37 #define EVENT_TYPE_ZPASS_DONE 0x15 38 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 39 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f 40 #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 41 #define EVENT_TYPE(x) ((x) << 0) 42 #define EVENT_INDEX(x) ((x) << 8) 43 /* 0 - any non-TS event 44 * 1 - ZPASS_DONE 45 * 2 - SAMPLE_PIPELINESTAT 46 * 3 - SAMPLE_STREAMOUTSTAT* 47 * 4 - *S_PARTIAL_FLUSH 48 * 5 - TS events 49 */ 50 51 #define PREDICATION_OP_CLEAR 0x0 52 #define PREDICATION_OP_ZPASS 0x1 53 #define PREDICATION_OP_PRIMCOUNT 0x2 54 55 #define PRED_OP(x) ((x) << 16) 56 57 #define PREDICATION_CONTINUE (1 << 31) 58 59 #define PREDICATION_HINT_WAIT (0 << 12) 60 #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) 61 62 #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) 63 #define PREDICATION_DRAW_VISIBLE (1 << 8) 64 65 #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 66 67 #define PKT3_NOP 0x10 68 #define PKT3_SET_PREDICATION 0x20 69 #define PKT3_COND_EXEC 0x22 70 #define PKT3_PRED_EXEC 0x23 71 #define PKT3_START_3D_CMDBUF 0x24 72 #define PKT3_DRAW_INDEX_2 0x27 73 #define PKT3_CONTEXT_CONTROL 0x28 74 #define PKT3_INDEX_TYPE 0x2A 75 #define PKT3_DRAW_INDEX 0x2B 76 #define PKT3_DRAW_INDEX_AUTO 0x2D 77 #define PKT3_DRAW_INDEX_IMMD 0x2E 78 #define PKT3_NUM_INSTANCES 0x2F 79 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34 80 #define PKT3_MEM_SEMAPHORE 0x39 81 #define PKT3_MPEG_INDEX 0x3A 82 #define PKT3_WAIT_REG_MEM 0x3C 83 #define WAIT_REG_MEM_EQUAL 3 84 #define PKT3_MEM_WRITE 0x3D 85 #define PKT3_INDIRECT_BUFFER 0x32 86 #define PKT3_SURFACE_SYNC 0x43 87 #define PKT3_ME_INITIALIZE 0x44 88 #define PKT3_COND_WRITE 0x45 89 #define PKT3_EVENT_WRITE 0x46 90 #define PKT3_EVENT_WRITE_EOP 0x47 91 #define PKT3_EVENT_WRITE_EOS 0x48 92 #define PKT3_ONE_REG_WRITE 0x57 93 #define PKT3_SET_CONFIG_REG 0x68 94 #define PKT3_SET_CONTEXT_REG 0x69 95 #define PKT3_SET_SH_REG 0x76 96 #define PKT3_SET_SH_REG_OFFSET 0x77 97 98 #define PKT_TYPE_S(x) (((x) & 0x3) << 30) 99 #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) 100 #define PKT_TYPE_C 0x3FFFFFFF 101 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 102 #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) 103 #define PKT_COUNT_C 0xC000FFFF 104 #define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) 105 #define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) 106 #define PKT0_BASE_INDEX_C 0xFFFF0000 107 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 108 #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) 109 #define PKT3_IT_OPCODE_C 0xFFFF00FF 110 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 111 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) 112 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate)) 113 114 #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC 115 #define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) 116 #define R_0085F0_CP_COHER_CNTL 0x0085F0 117 #define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) 118 #define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) 119 #define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE 120 #define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) 121 #define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) 122 #define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD 123 #define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6 124 #define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) 125 #define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) 126 #define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF 127 #define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) 128 #define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) 129 #define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F 130 #define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) 131 #define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) 132 #define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF 133 #define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) 134 #define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) 135 #define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF 136 #define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) 137 #define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) 138 #define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF 139 #define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) 140 #define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) 141 #define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF 142 #define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) 143 #define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) 144 #define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF 145 #define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) 146 #define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) 147 #define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF 148 #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) 149 #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) 150 #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF 151 #define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19) 152 #define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1) 153 #define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF 154 #define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21) 155 #define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1) 156 #define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF 157 #define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22) 158 #define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1) 159 #define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF 160 #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) 161 #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) 162 #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF 163 #define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) 164 #define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) 165 #define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF 166 #define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) 167 #define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) 168 #define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF 169 #define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27) 170 #define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1) 171 #define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF 172 #define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29) 173 #define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1) 174 #define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF 175 #define R_0085F4_CP_COHER_SIZE 0x0085F4 176 #define R_0085F8_CP_COHER_BASE 0x0085F8 177 #define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0 178 #define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0) 179 #define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF) 180 #define C_0088B0_PRIM_COUNT 0xFFFFFC00 181 #define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4 182 #define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5) 183 #define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1) 184 #define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF 185 #define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13) 186 #define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1) 187 #define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF 188 #define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16) 189 #define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F) 190 #define C_0088C4_ES_LIMIT 0xFFE0FFFF 191 #define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8 192 #define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC 193 #define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4 194 #define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0) 195 #define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F) 196 #define C_0088D4_VERT_REUSE 0xFFFFFFE0 197 #define R_008958_VGT_PRIMITIVE_TYPE 0x008958 198 #define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) 199 #define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) 200 #define C_008958_PRIM_TYPE 0xFFFFFFC0 201 #define V_008958_DI_PT_NONE 0x00 202 #define V_008958_DI_PT_POINTLIST 0x01 203 #define V_008958_DI_PT_LINELIST 0x02 204 #define V_008958_DI_PT_LINESTRIP 0x03 205 #define V_008958_DI_PT_TRILIST 0x04 206 #define V_008958_DI_PT_TRIFAN 0x05 207 #define V_008958_DI_PT_TRISTRIP 0x06 208 #define V_008958_DI_PT_UNUSED_0 0x07 209 #define V_008958_DI_PT_UNUSED_1 0x08 210 #define V_008958_DI_PT_PATCH 0x09 211 #define V_008958_DI_PT_LINELIST_ADJ 0x0A 212 #define V_008958_DI_PT_LINESTRIP_ADJ 0x0B 213 #define V_008958_DI_PT_TRILIST_ADJ 0x0C 214 #define V_008958_DI_PT_TRISTRIP_ADJ 0x0D 215 #define V_008958_DI_PT_UNUSED_3 0x0E 216 #define V_008958_DI_PT_UNUSED_4 0x0F 217 #define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10 218 #define V_008958_DI_PT_RECTLIST 0x11 219 #define V_008958_DI_PT_LINELOOP 0x12 220 #define V_008958_DI_PT_QUADLIST 0x13 221 #define V_008958_DI_PT_QUADSTRIP 0x14 222 #define V_008958_DI_PT_POLYGON 0x15 223 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16 224 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17 225 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18 226 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19 227 #define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A 228 #define V_008958_DI_PT_2D_LINE_STRIP 0x1B 229 #define V_008958_DI_PT_2D_TRI_STRIP 0x1C 230 #define R_00895C_VGT_INDEX_TYPE 0x00895C 231 #define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0) 232 #define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03) 233 #define C_00895C_INDEX_TYPE 0xFFFFFFFC 234 #define V_00895C_DI_INDEX_SIZE_16_BIT 0x00 235 #define V_00895C_DI_INDEX_SIZE_32_BIT 0x01 236 #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 237 #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 238 #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 239 #define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C 240 #define R_008970_VGT_NUM_INDICES 0x008970 241 #define R_008974_VGT_NUM_INSTANCES 0x008974 242 #define R_008988_VGT_TF_RING_SIZE 0x008988 243 #define S_008988_SIZE(x) (((x) & 0xFFFF) << 0) 244 #define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF) 245 #define C_008988_SIZE 0xFFFF0000 246 #define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0 247 #define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0) 248 #define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F) 249 #define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80 250 #define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8 251 #define R_008A14_PA_CL_ENHANCE 0x008A14 252 #define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0) 253 #define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1) 254 #define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE 255 #define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1) 256 #define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03) 257 #define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9 258 #define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3) 259 #define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1) 260 #define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7 261 #define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4) 262 #define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1) 263 #define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF 264 #define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60 265 #define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0) 266 #define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF) 267 #define C_008A60_LINE_STIPPLE_VALUE 0xFF000000 268 #define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10 269 #define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0) 270 #define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F) 271 #define C_008B10_CURRENT_PTR 0xFFFFFFF0 272 #define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8) 273 #define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF) 274 #define C_008B10_CURRENT_COUNT 0xFFFF00FF 275 #define R_008BF0_PA_SC_ENHANCE 0x008BF0 276 #define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0) 277 #define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1) 278 #define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE 279 #define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1) 280 #define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1) 281 #define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD 282 #define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2) 283 #define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1) 284 #define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB 285 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3) 286 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1) 287 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7 288 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4) 289 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1) 290 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF 291 #define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5) 292 #define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1) 293 #define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF 294 #define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6) 295 #define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03) 296 #define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F 297 #define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8) 298 #define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1) 299 #define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF 300 #define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9) 301 #define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1) 302 #define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF 303 #define R_008C08_SQC_CACHES 0x008C08 304 #define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0) 305 #define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1) 306 #define C_008C08_INST_INVALIDATE 0xFFFFFFFE 307 #define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1) 308 #define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1) 309 #define C_008C08_DATA_INVALIDATE 0xFFFFFFFD 310 #define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C 311 #define S_008C0C_RET(x) (((x) & 0x7F) << 0) 312 #define G_008C0C_RET(x) (((x) >> 0) & 0x7F) 313 #define C_008C0C_RET 0xFFFFFF80 314 #define S_008C0C_RUI(x) (((x) & 0x07) << 7) 315 #define G_008C0C_RUI(x) (((x) >> 7) & 0x07) 316 #define C_008C0C_RUI 0xFFFFFC7F 317 #define S_008C0C_RNG(x) (((x) & 0x7FF) << 10) 318 #define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF) 319 #define C_008C0C_RNG 0xFFE003FF 320 #if 0 321 #define R_008DFC_SQ_INST 0x008DFC 322 #define R_008DFC_SQ_VOP1 0x008DFC 323 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) 324 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) 325 #define C_008DFC_SRC0 0xFFFFFE00 326 #define V_008DFC_SQ_SGPR 0x00 327 #define V_008DFC_SQ_VCC_LO 0x6A 328 #define V_008DFC_SQ_VCC_HI 0x6B 329 #define V_008DFC_SQ_TBA_LO 0x6C 330 #define V_008DFC_SQ_TBA_HI 0x6D 331 #define V_008DFC_SQ_TMA_LO 0x6E 332 #define V_008DFC_SQ_TMA_HI 0x6F 333 #define V_008DFC_SQ_TTMP0 0x70 334 #define V_008DFC_SQ_TTMP1 0x71 335 #define V_008DFC_SQ_TTMP2 0x72 336 #define V_008DFC_SQ_TTMP3 0x73 337 #define V_008DFC_SQ_TTMP4 0x74 338 #define V_008DFC_SQ_TTMP5 0x75 339 #define V_008DFC_SQ_TTMP6 0x76 340 #define V_008DFC_SQ_TTMP7 0x77 341 #define V_008DFC_SQ_TTMP8 0x78 342 #define V_008DFC_SQ_TTMP9 0x79 343 #define V_008DFC_SQ_TTMP10 0x7A 344 #define V_008DFC_SQ_TTMP11 0x7B 345 #define V_008DFC_SQ_M0 0x7C 346 #define V_008DFC_SQ_EXEC_LO 0x7E 347 #define V_008DFC_SQ_EXEC_HI 0x7F 348 #define V_008DFC_SQ_SRC_0 0x80 349 #define V_008DFC_SQ_SRC_1_INT 0x81 350 #define V_008DFC_SQ_SRC_2_INT 0x82 351 #define V_008DFC_SQ_SRC_3_INT 0x83 352 #define V_008DFC_SQ_SRC_4_INT 0x84 353 #define V_008DFC_SQ_SRC_5_INT 0x85 354 #define V_008DFC_SQ_SRC_6_INT 0x86 355 #define V_008DFC_SQ_SRC_7_INT 0x87 356 #define V_008DFC_SQ_SRC_8_INT 0x88 357 #define V_008DFC_SQ_SRC_9_INT 0x89 358 #define V_008DFC_SQ_SRC_10_INT 0x8A 359 #define V_008DFC_SQ_SRC_11_INT 0x8B 360 #define V_008DFC_SQ_SRC_12_INT 0x8C 361 #define V_008DFC_SQ_SRC_13_INT 0x8D 362 #define V_008DFC_SQ_SRC_14_INT 0x8E 363 #define V_008DFC_SQ_SRC_15_INT 0x8F 364 #define V_008DFC_SQ_SRC_16_INT 0x90 365 #define V_008DFC_SQ_SRC_17_INT 0x91 366 #define V_008DFC_SQ_SRC_18_INT 0x92 367 #define V_008DFC_SQ_SRC_19_INT 0x93 368 #define V_008DFC_SQ_SRC_20_INT 0x94 369 #define V_008DFC_SQ_SRC_21_INT 0x95 370 #define V_008DFC_SQ_SRC_22_INT 0x96 371 #define V_008DFC_SQ_SRC_23_INT 0x97 372 #define V_008DFC_SQ_SRC_24_INT 0x98 373 #define V_008DFC_SQ_SRC_25_INT 0x99 374 #define V_008DFC_SQ_SRC_26_INT 0x9A 375 #define V_008DFC_SQ_SRC_27_INT 0x9B 376 #define V_008DFC_SQ_SRC_28_INT 0x9C 377 #define V_008DFC_SQ_SRC_29_INT 0x9D 378 #define V_008DFC_SQ_SRC_30_INT 0x9E 379 #define V_008DFC_SQ_SRC_31_INT 0x9F 380 #define V_008DFC_SQ_SRC_32_INT 0xA0 381 #define V_008DFC_SQ_SRC_33_INT 0xA1 382 #define V_008DFC_SQ_SRC_34_INT 0xA2 383 #define V_008DFC_SQ_SRC_35_INT 0xA3 384 #define V_008DFC_SQ_SRC_36_INT 0xA4 385 #define V_008DFC_SQ_SRC_37_INT 0xA5 386 #define V_008DFC_SQ_SRC_38_INT 0xA6 387 #define V_008DFC_SQ_SRC_39_INT 0xA7 388 #define V_008DFC_SQ_SRC_40_INT 0xA8 389 #define V_008DFC_SQ_SRC_41_INT 0xA9 390 #define V_008DFC_SQ_SRC_42_INT 0xAA 391 #define V_008DFC_SQ_SRC_43_INT 0xAB 392 #define V_008DFC_SQ_SRC_44_INT 0xAC 393 #define V_008DFC_SQ_SRC_45_INT 0xAD 394 #define V_008DFC_SQ_SRC_46_INT 0xAE 395 #define V_008DFC_SQ_SRC_47_INT 0xAF 396 #define V_008DFC_SQ_SRC_48_INT 0xB0 397 #define V_008DFC_SQ_SRC_49_INT 0xB1 398 #define V_008DFC_SQ_SRC_50_INT 0xB2 399 #define V_008DFC_SQ_SRC_51_INT 0xB3 400 #define V_008DFC_SQ_SRC_52_INT 0xB4 401 #define V_008DFC_SQ_SRC_53_INT 0xB5 402 #define V_008DFC_SQ_SRC_54_INT 0xB6 403 #define V_008DFC_SQ_SRC_55_INT 0xB7 404 #define V_008DFC_SQ_SRC_56_INT 0xB8 405 #define V_008DFC_SQ_SRC_57_INT 0xB9 406 #define V_008DFC_SQ_SRC_58_INT 0xBA 407 #define V_008DFC_SQ_SRC_59_INT 0xBB 408 #define V_008DFC_SQ_SRC_60_INT 0xBC 409 #define V_008DFC_SQ_SRC_61_INT 0xBD 410 #define V_008DFC_SQ_SRC_62_INT 0xBE 411 #define V_008DFC_SQ_SRC_63_INT 0xBF 412 #define V_008DFC_SQ_SRC_64_INT 0xC0 413 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 414 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 415 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 416 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 417 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 418 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 419 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 420 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 421 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 422 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 423 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 424 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 425 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 426 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 427 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 428 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 429 #define V_008DFC_SQ_SRC_0_5 0xF0 430 #define V_008DFC_SQ_SRC_M_0_5 0xF1 431 #define V_008DFC_SQ_SRC_1 0xF2 432 #define V_008DFC_SQ_SRC_M_1 0xF3 433 #define V_008DFC_SQ_SRC_2 0xF4 434 #define V_008DFC_SQ_SRC_M_2 0xF5 435 #define V_008DFC_SQ_SRC_4 0xF6 436 #define V_008DFC_SQ_SRC_M_4 0xF7 437 #define V_008DFC_SQ_SRC_VCCZ 0xFB 438 #define V_008DFC_SQ_SRC_EXECZ 0xFC 439 #define V_008DFC_SQ_SRC_SCC 0xFD 440 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 441 #define V_008DFC_SQ_SRC_VGPR 0x100 442 #define S_008DFC_OP(x) (((x) & 0xFF) << 9) 443 #define G_008DFC_OP(x) (((x) >> 9) & 0xFF) 444 #define C_008DFC_OP 0xFFFE01FF 445 #define V_008DFC_SQ_V_NOP 0x00 446 #define V_008DFC_SQ_V_MOV_B32 0x01 447 #define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02 448 #define V_008DFC_SQ_V_CVT_I32_F64 0x03 449 #define V_008DFC_SQ_V_CVT_F64_I32 0x04 450 #define V_008DFC_SQ_V_CVT_F32_I32 0x05 451 #define V_008DFC_SQ_V_CVT_F32_U32 0x06 452 #define V_008DFC_SQ_V_CVT_U32_F32 0x07 453 #define V_008DFC_SQ_V_CVT_I32_F32 0x08 454 #define V_008DFC_SQ_V_MOV_FED_B32 0x09 455 #define V_008DFC_SQ_V_CVT_F16_F32 0x0A 456 #define V_008DFC_SQ_V_CVT_F32_F16 0x0B 457 #define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C 458 #define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D 459 #define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E 460 #define V_008DFC_SQ_V_CVT_F32_F64 0x0F 461 #define V_008DFC_SQ_V_CVT_F64_F32 0x10 462 #define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11 463 #define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12 464 #define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13 465 #define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14 466 #define V_008DFC_SQ_V_CVT_U32_F64 0x15 467 #define V_008DFC_SQ_V_CVT_F64_U32 0x16 468 #define V_008DFC_SQ_V_FRACT_F32 0x20 469 #define V_008DFC_SQ_V_TRUNC_F32 0x21 470 #define V_008DFC_SQ_V_CEIL_F32 0x22 471 #define V_008DFC_SQ_V_RNDNE_F32 0x23 472 #define V_008DFC_SQ_V_FLOOR_F32 0x24 473 #define V_008DFC_SQ_V_EXP_F32 0x25 474 #define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26 475 #define V_008DFC_SQ_V_LOG_F32 0x27 476 #define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28 477 #define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29 478 #define V_008DFC_SQ_V_RCP_F32 0x2A 479 #define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B 480 #define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C 481 #define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D 482 #define V_008DFC_SQ_V_RSQ_F32 0x2E 483 #define V_008DFC_SQ_V_RCP_F64 0x2F 484 #define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30 485 #define V_008DFC_SQ_V_RSQ_F64 0x31 486 #define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32 487 #define V_008DFC_SQ_V_SQRT_F32 0x33 488 #define V_008DFC_SQ_V_SQRT_F64 0x34 489 #define V_008DFC_SQ_V_SIN_F32 0x35 490 #define V_008DFC_SQ_V_COS_F32 0x36 491 #define V_008DFC_SQ_V_NOT_B32 0x37 492 #define V_008DFC_SQ_V_BFREV_B32 0x38 493 #define V_008DFC_SQ_V_FFBH_U32 0x39 494 #define V_008DFC_SQ_V_FFBL_B32 0x3A 495 #define V_008DFC_SQ_V_FFBH_I32 0x3B 496 #define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C 497 #define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D 498 #define V_008DFC_SQ_V_FRACT_F64 0x3E 499 #define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F 500 #define V_008DFC_SQ_V_FREXP_MANT_F32 0x40 501 #define V_008DFC_SQ_V_CLREXCP 0x41 502 #define V_008DFC_SQ_V_MOVRELD_B32 0x42 503 #define V_008DFC_SQ_V_MOVRELS_B32 0x43 504 #define V_008DFC_SQ_V_MOVRELSD_B32 0x44 505 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17) 506 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) 507 #define C_008DFC_VDST 0xFE01FFFF 508 #define V_008DFC_SQ_VGPR 0x00 509 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) 510 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) 511 #define C_008DFC_ENCODING 0x01FFFFFF 512 #define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F 513 #define R_008DFC_SQ_MIMG_1 0x008DFC 514 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) 515 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) 516 #define C_008DFC_VADDR 0xFFFFFF00 517 #define V_008DFC_SQ_VGPR 0x00 518 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) 519 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) 520 #define C_008DFC_VDATA 0xFFFF00FF 521 #define V_008DFC_SQ_VGPR 0x00 522 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) 523 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) 524 #define C_008DFC_SRSRC 0xFFE0FFFF 525 #define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21) 526 #define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F) 527 #define C_008DFC_SSAMP 0xFC1FFFFF 528 #define R_008DFC_SQ_VOP3_1 0x008DFC 529 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) 530 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) 531 #define C_008DFC_SRC0 0xFFFFFE00 532 #define V_008DFC_SQ_SGPR 0x00 533 #define V_008DFC_SQ_VCC_LO 0x6A 534 #define V_008DFC_SQ_VCC_HI 0x6B 535 #define V_008DFC_SQ_TBA_LO 0x6C 536 #define V_008DFC_SQ_TBA_HI 0x6D 537 #define V_008DFC_SQ_TMA_LO 0x6E 538 #define V_008DFC_SQ_TMA_HI 0x6F 539 #define V_008DFC_SQ_TTMP0 0x70 540 #define V_008DFC_SQ_TTMP1 0x71 541 #define V_008DFC_SQ_TTMP2 0x72 542 #define V_008DFC_SQ_TTMP3 0x73 543 #define V_008DFC_SQ_TTMP4 0x74 544 #define V_008DFC_SQ_TTMP5 0x75 545 #define V_008DFC_SQ_TTMP6 0x76 546 #define V_008DFC_SQ_TTMP7 0x77 547 #define V_008DFC_SQ_TTMP8 0x78 548 #define V_008DFC_SQ_TTMP9 0x79 549 #define V_008DFC_SQ_TTMP10 0x7A 550 #define V_008DFC_SQ_TTMP11 0x7B 551 #define V_008DFC_SQ_M0 0x7C 552 #define V_008DFC_SQ_EXEC_LO 0x7E 553 #define V_008DFC_SQ_EXEC_HI 0x7F 554 #define V_008DFC_SQ_SRC_0 0x80 555 #define V_008DFC_SQ_SRC_1_INT 0x81 556 #define V_008DFC_SQ_SRC_2_INT 0x82 557 #define V_008DFC_SQ_SRC_3_INT 0x83 558 #define V_008DFC_SQ_SRC_4_INT 0x84 559 #define V_008DFC_SQ_SRC_5_INT 0x85 560 #define V_008DFC_SQ_SRC_6_INT 0x86 561 #define V_008DFC_SQ_SRC_7_INT 0x87 562 #define V_008DFC_SQ_SRC_8_INT 0x88 563 #define V_008DFC_SQ_SRC_9_INT 0x89 564 #define V_008DFC_SQ_SRC_10_INT 0x8A 565 #define V_008DFC_SQ_SRC_11_INT 0x8B 566 #define V_008DFC_SQ_SRC_12_INT 0x8C 567 #define V_008DFC_SQ_SRC_13_INT 0x8D 568 #define V_008DFC_SQ_SRC_14_INT 0x8E 569 #define V_008DFC_SQ_SRC_15_INT 0x8F 570 #define V_008DFC_SQ_SRC_16_INT 0x90 571 #define V_008DFC_SQ_SRC_17_INT 0x91 572 #define V_008DFC_SQ_SRC_18_INT 0x92 573 #define V_008DFC_SQ_SRC_19_INT 0x93 574 #define V_008DFC_SQ_SRC_20_INT 0x94 575 #define V_008DFC_SQ_SRC_21_INT 0x95 576 #define V_008DFC_SQ_SRC_22_INT 0x96 577 #define V_008DFC_SQ_SRC_23_INT 0x97 578 #define V_008DFC_SQ_SRC_24_INT 0x98 579 #define V_008DFC_SQ_SRC_25_INT 0x99 580 #define V_008DFC_SQ_SRC_26_INT 0x9A 581 #define V_008DFC_SQ_SRC_27_INT 0x9B 582 #define V_008DFC_SQ_SRC_28_INT 0x9C 583 #define V_008DFC_SQ_SRC_29_INT 0x9D 584 #define V_008DFC_SQ_SRC_30_INT 0x9E 585 #define V_008DFC_SQ_SRC_31_INT 0x9F 586 #define V_008DFC_SQ_SRC_32_INT 0xA0 587 #define V_008DFC_SQ_SRC_33_INT 0xA1 588 #define V_008DFC_SQ_SRC_34_INT 0xA2 589 #define V_008DFC_SQ_SRC_35_INT 0xA3 590 #define V_008DFC_SQ_SRC_36_INT 0xA4 591 #define V_008DFC_SQ_SRC_37_INT 0xA5 592 #define V_008DFC_SQ_SRC_38_INT 0xA6 593 #define V_008DFC_SQ_SRC_39_INT 0xA7 594 #define V_008DFC_SQ_SRC_40_INT 0xA8 595 #define V_008DFC_SQ_SRC_41_INT 0xA9 596 #define V_008DFC_SQ_SRC_42_INT 0xAA 597 #define V_008DFC_SQ_SRC_43_INT 0xAB 598 #define V_008DFC_SQ_SRC_44_INT 0xAC 599 #define V_008DFC_SQ_SRC_45_INT 0xAD 600 #define V_008DFC_SQ_SRC_46_INT 0xAE 601 #define V_008DFC_SQ_SRC_47_INT 0xAF 602 #define V_008DFC_SQ_SRC_48_INT 0xB0 603 #define V_008DFC_SQ_SRC_49_INT 0xB1 604 #define V_008DFC_SQ_SRC_50_INT 0xB2 605 #define V_008DFC_SQ_SRC_51_INT 0xB3 606 #define V_008DFC_SQ_SRC_52_INT 0xB4 607 #define V_008DFC_SQ_SRC_53_INT 0xB5 608 #define V_008DFC_SQ_SRC_54_INT 0xB6 609 #define V_008DFC_SQ_SRC_55_INT 0xB7 610 #define V_008DFC_SQ_SRC_56_INT 0xB8 611 #define V_008DFC_SQ_SRC_57_INT 0xB9 612 #define V_008DFC_SQ_SRC_58_INT 0xBA 613 #define V_008DFC_SQ_SRC_59_INT 0xBB 614 #define V_008DFC_SQ_SRC_60_INT 0xBC 615 #define V_008DFC_SQ_SRC_61_INT 0xBD 616 #define V_008DFC_SQ_SRC_62_INT 0xBE 617 #define V_008DFC_SQ_SRC_63_INT 0xBF 618 #define V_008DFC_SQ_SRC_64_INT 0xC0 619 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 620 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 621 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 622 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 623 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 624 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 625 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 626 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 627 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 628 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 629 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 630 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 631 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 632 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 633 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 634 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 635 #define V_008DFC_SQ_SRC_0_5 0xF0 636 #define V_008DFC_SQ_SRC_M_0_5 0xF1 637 #define V_008DFC_SQ_SRC_1 0xF2 638 #define V_008DFC_SQ_SRC_M_1 0xF3 639 #define V_008DFC_SQ_SRC_2 0xF4 640 #define V_008DFC_SQ_SRC_M_2 0xF5 641 #define V_008DFC_SQ_SRC_4 0xF6 642 #define V_008DFC_SQ_SRC_M_4 0xF7 643 #define V_008DFC_SQ_SRC_VCCZ 0xFB 644 #define V_008DFC_SQ_SRC_EXECZ 0xFC 645 #define V_008DFC_SQ_SRC_SCC 0xFD 646 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 647 #define V_008DFC_SQ_SRC_VGPR 0x100 648 #define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9) 649 #define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF) 650 #define C_008DFC_SRC1 0xFFFC01FF 651 #define V_008DFC_SQ_SGPR 0x00 652 #define V_008DFC_SQ_VCC_LO 0x6A 653 #define V_008DFC_SQ_VCC_HI 0x6B 654 #define V_008DFC_SQ_TBA_LO 0x6C 655 #define V_008DFC_SQ_TBA_HI 0x6D 656 #define V_008DFC_SQ_TMA_LO 0x6E 657 #define V_008DFC_SQ_TMA_HI 0x6F 658 #define V_008DFC_SQ_TTMP0 0x70 659 #define V_008DFC_SQ_TTMP1 0x71 660 #define V_008DFC_SQ_TTMP2 0x72 661 #define V_008DFC_SQ_TTMP3 0x73 662 #define V_008DFC_SQ_TTMP4 0x74 663 #define V_008DFC_SQ_TTMP5 0x75 664 #define V_008DFC_SQ_TTMP6 0x76 665 #define V_008DFC_SQ_TTMP7 0x77 666 #define V_008DFC_SQ_TTMP8 0x78 667 #define V_008DFC_SQ_TTMP9 0x79 668 #define V_008DFC_SQ_TTMP10 0x7A 669 #define V_008DFC_SQ_TTMP11 0x7B 670 #define V_008DFC_SQ_M0 0x7C 671 #define V_008DFC_SQ_EXEC_LO 0x7E 672 #define V_008DFC_SQ_EXEC_HI 0x7F 673 #define V_008DFC_SQ_SRC_0 0x80 674 #define V_008DFC_SQ_SRC_1_INT 0x81 675 #define V_008DFC_SQ_SRC_2_INT 0x82 676 #define V_008DFC_SQ_SRC_3_INT 0x83 677 #define V_008DFC_SQ_SRC_4_INT 0x84 678 #define V_008DFC_SQ_SRC_5_INT 0x85 679 #define V_008DFC_SQ_SRC_6_INT 0x86 680 #define V_008DFC_SQ_SRC_7_INT 0x87 681 #define V_008DFC_SQ_SRC_8_INT 0x88 682 #define V_008DFC_SQ_SRC_9_INT 0x89 683 #define V_008DFC_SQ_SRC_10_INT 0x8A 684 #define V_008DFC_SQ_SRC_11_INT 0x8B 685 #define V_008DFC_SQ_SRC_12_INT 0x8C 686 #define V_008DFC_SQ_SRC_13_INT 0x8D 687 #define V_008DFC_SQ_SRC_14_INT 0x8E 688 #define V_008DFC_SQ_SRC_15_INT 0x8F 689 #define V_008DFC_SQ_SRC_16_INT 0x90 690 #define V_008DFC_SQ_SRC_17_INT 0x91 691 #define V_008DFC_SQ_SRC_18_INT 0x92 692 #define V_008DFC_SQ_SRC_19_INT 0x93 693 #define V_008DFC_SQ_SRC_20_INT 0x94 694 #define V_008DFC_SQ_SRC_21_INT 0x95 695 #define V_008DFC_SQ_SRC_22_INT 0x96 696 #define V_008DFC_SQ_SRC_23_INT 0x97 697 #define V_008DFC_SQ_SRC_24_INT 0x98 698 #define V_008DFC_SQ_SRC_25_INT 0x99 699 #define V_008DFC_SQ_SRC_26_INT 0x9A 700 #define V_008DFC_SQ_SRC_27_INT 0x9B 701 #define V_008DFC_SQ_SRC_28_INT 0x9C 702 #define V_008DFC_SQ_SRC_29_INT 0x9D 703 #define V_008DFC_SQ_SRC_30_INT 0x9E 704 #define V_008DFC_SQ_SRC_31_INT 0x9F 705 #define V_008DFC_SQ_SRC_32_INT 0xA0 706 #define V_008DFC_SQ_SRC_33_INT 0xA1 707 #define V_008DFC_SQ_SRC_34_INT 0xA2 708 #define V_008DFC_SQ_SRC_35_INT 0xA3 709 #define V_008DFC_SQ_SRC_36_INT 0xA4 710 #define V_008DFC_SQ_SRC_37_INT 0xA5 711 #define V_008DFC_SQ_SRC_38_INT 0xA6 712 #define V_008DFC_SQ_SRC_39_INT 0xA7 713 #define V_008DFC_SQ_SRC_40_INT 0xA8 714 #define V_008DFC_SQ_SRC_41_INT 0xA9 715 #define V_008DFC_SQ_SRC_42_INT 0xAA 716 #define V_008DFC_SQ_SRC_43_INT 0xAB 717 #define V_008DFC_SQ_SRC_44_INT 0xAC 718 #define V_008DFC_SQ_SRC_45_INT 0xAD 719 #define V_008DFC_SQ_SRC_46_INT 0xAE 720 #define V_008DFC_SQ_SRC_47_INT 0xAF 721 #define V_008DFC_SQ_SRC_48_INT 0xB0 722 #define V_008DFC_SQ_SRC_49_INT 0xB1 723 #define V_008DFC_SQ_SRC_50_INT 0xB2 724 #define V_008DFC_SQ_SRC_51_INT 0xB3 725 #define V_008DFC_SQ_SRC_52_INT 0xB4 726 #define V_008DFC_SQ_SRC_53_INT 0xB5 727 #define V_008DFC_SQ_SRC_54_INT 0xB6 728 #define V_008DFC_SQ_SRC_55_INT 0xB7 729 #define V_008DFC_SQ_SRC_56_INT 0xB8 730 #define V_008DFC_SQ_SRC_57_INT 0xB9 731 #define V_008DFC_SQ_SRC_58_INT 0xBA 732 #define V_008DFC_SQ_SRC_59_INT 0xBB 733 #define V_008DFC_SQ_SRC_60_INT 0xBC 734 #define V_008DFC_SQ_SRC_61_INT 0xBD 735 #define V_008DFC_SQ_SRC_62_INT 0xBE 736 #define V_008DFC_SQ_SRC_63_INT 0xBF 737 #define V_008DFC_SQ_SRC_64_INT 0xC0 738 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 739 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 740 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 741 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 742 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 743 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 744 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 745 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 746 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 747 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 748 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 749 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 750 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 751 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 752 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 753 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 754 #define V_008DFC_SQ_SRC_0_5 0xF0 755 #define V_008DFC_SQ_SRC_M_0_5 0xF1 756 #define V_008DFC_SQ_SRC_1 0xF2 757 #define V_008DFC_SQ_SRC_M_1 0xF3 758 #define V_008DFC_SQ_SRC_2 0xF4 759 #define V_008DFC_SQ_SRC_M_2 0xF5 760 #define V_008DFC_SQ_SRC_4 0xF6 761 #define V_008DFC_SQ_SRC_M_4 0xF7 762 #define V_008DFC_SQ_SRC_VCCZ 0xFB 763 #define V_008DFC_SQ_SRC_EXECZ 0xFC 764 #define V_008DFC_SQ_SRC_SCC 0xFD 765 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 766 #define V_008DFC_SQ_SRC_VGPR 0x100 767 #define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18) 768 #define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF) 769 #define C_008DFC_SRC2 0xF803FFFF 770 #define V_008DFC_SQ_SGPR 0x00 771 #define V_008DFC_SQ_VCC_LO 0x6A 772 #define V_008DFC_SQ_VCC_HI 0x6B 773 #define V_008DFC_SQ_TBA_LO 0x6C 774 #define V_008DFC_SQ_TBA_HI 0x6D 775 #define V_008DFC_SQ_TMA_LO 0x6E 776 #define V_008DFC_SQ_TMA_HI 0x6F 777 #define V_008DFC_SQ_TTMP0 0x70 778 #define V_008DFC_SQ_TTMP1 0x71 779 #define V_008DFC_SQ_TTMP2 0x72 780 #define V_008DFC_SQ_TTMP3 0x73 781 #define V_008DFC_SQ_TTMP4 0x74 782 #define V_008DFC_SQ_TTMP5 0x75 783 #define V_008DFC_SQ_TTMP6 0x76 784 #define V_008DFC_SQ_TTMP7 0x77 785 #define V_008DFC_SQ_TTMP8 0x78 786 #define V_008DFC_SQ_TTMP9 0x79 787 #define V_008DFC_SQ_TTMP10 0x7A 788 #define V_008DFC_SQ_TTMP11 0x7B 789 #define V_008DFC_SQ_M0 0x7C 790 #define V_008DFC_SQ_EXEC_LO 0x7E 791 #define V_008DFC_SQ_EXEC_HI 0x7F 792 #define V_008DFC_SQ_SRC_0 0x80 793 #define V_008DFC_SQ_SRC_1_INT 0x81 794 #define V_008DFC_SQ_SRC_2_INT 0x82 795 #define V_008DFC_SQ_SRC_3_INT 0x83 796 #define V_008DFC_SQ_SRC_4_INT 0x84 797 #define V_008DFC_SQ_SRC_5_INT 0x85 798 #define V_008DFC_SQ_SRC_6_INT 0x86 799 #define V_008DFC_SQ_SRC_7_INT 0x87 800 #define V_008DFC_SQ_SRC_8_INT 0x88 801 #define V_008DFC_SQ_SRC_9_INT 0x89 802 #define V_008DFC_SQ_SRC_10_INT 0x8A 803 #define V_008DFC_SQ_SRC_11_INT 0x8B 804 #define V_008DFC_SQ_SRC_12_INT 0x8C 805 #define V_008DFC_SQ_SRC_13_INT 0x8D 806 #define V_008DFC_SQ_SRC_14_INT 0x8E 807 #define V_008DFC_SQ_SRC_15_INT 0x8F 808 #define V_008DFC_SQ_SRC_16_INT 0x90 809 #define V_008DFC_SQ_SRC_17_INT 0x91 810 #define V_008DFC_SQ_SRC_18_INT 0x92 811 #define V_008DFC_SQ_SRC_19_INT 0x93 812 #define V_008DFC_SQ_SRC_20_INT 0x94 813 #define V_008DFC_SQ_SRC_21_INT 0x95 814 #define V_008DFC_SQ_SRC_22_INT 0x96 815 #define V_008DFC_SQ_SRC_23_INT 0x97 816 #define V_008DFC_SQ_SRC_24_INT 0x98 817 #define V_008DFC_SQ_SRC_25_INT 0x99 818 #define V_008DFC_SQ_SRC_26_INT 0x9A 819 #define V_008DFC_SQ_SRC_27_INT 0x9B 820 #define V_008DFC_SQ_SRC_28_INT 0x9C 821 #define V_008DFC_SQ_SRC_29_INT 0x9D 822 #define V_008DFC_SQ_SRC_30_INT 0x9E 823 #define V_008DFC_SQ_SRC_31_INT 0x9F 824 #define V_008DFC_SQ_SRC_32_INT 0xA0 825 #define V_008DFC_SQ_SRC_33_INT 0xA1 826 #define V_008DFC_SQ_SRC_34_INT 0xA2 827 #define V_008DFC_SQ_SRC_35_INT 0xA3 828 #define V_008DFC_SQ_SRC_36_INT 0xA4 829 #define V_008DFC_SQ_SRC_37_INT 0xA5 830 #define V_008DFC_SQ_SRC_38_INT 0xA6 831 #define V_008DFC_SQ_SRC_39_INT 0xA7 832 #define V_008DFC_SQ_SRC_40_INT 0xA8 833 #define V_008DFC_SQ_SRC_41_INT 0xA9 834 #define V_008DFC_SQ_SRC_42_INT 0xAA 835 #define V_008DFC_SQ_SRC_43_INT 0xAB 836 #define V_008DFC_SQ_SRC_44_INT 0xAC 837 #define V_008DFC_SQ_SRC_45_INT 0xAD 838 #define V_008DFC_SQ_SRC_46_INT 0xAE 839 #define V_008DFC_SQ_SRC_47_INT 0xAF 840 #define V_008DFC_SQ_SRC_48_INT 0xB0 841 #define V_008DFC_SQ_SRC_49_INT 0xB1 842 #define V_008DFC_SQ_SRC_50_INT 0xB2 843 #define V_008DFC_SQ_SRC_51_INT 0xB3 844 #define V_008DFC_SQ_SRC_52_INT 0xB4 845 #define V_008DFC_SQ_SRC_53_INT 0xB5 846 #define V_008DFC_SQ_SRC_54_INT 0xB6 847 #define V_008DFC_SQ_SRC_55_INT 0xB7 848 #define V_008DFC_SQ_SRC_56_INT 0xB8 849 #define V_008DFC_SQ_SRC_57_INT 0xB9 850 #define V_008DFC_SQ_SRC_58_INT 0xBA 851 #define V_008DFC_SQ_SRC_59_INT 0xBB 852 #define V_008DFC_SQ_SRC_60_INT 0xBC 853 #define V_008DFC_SQ_SRC_61_INT 0xBD 854 #define V_008DFC_SQ_SRC_62_INT 0xBE 855 #define V_008DFC_SQ_SRC_63_INT 0xBF 856 #define V_008DFC_SQ_SRC_64_INT 0xC0 857 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 858 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 859 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 860 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 861 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 862 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 863 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 864 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 865 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 866 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 867 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 868 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 869 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 870 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 871 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 872 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 873 #define V_008DFC_SQ_SRC_0_5 0xF0 874 #define V_008DFC_SQ_SRC_M_0_5 0xF1 875 #define V_008DFC_SQ_SRC_1 0xF2 876 #define V_008DFC_SQ_SRC_M_1 0xF3 877 #define V_008DFC_SQ_SRC_2 0xF4 878 #define V_008DFC_SQ_SRC_M_2 0xF5 879 #define V_008DFC_SQ_SRC_4 0xF6 880 #define V_008DFC_SQ_SRC_M_4 0xF7 881 #define V_008DFC_SQ_SRC_VCCZ 0xFB 882 #define V_008DFC_SQ_SRC_EXECZ 0xFC 883 #define V_008DFC_SQ_SRC_SCC 0xFD 884 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 885 #define V_008DFC_SQ_SRC_VGPR 0x100 886 #define S_008DFC_OMOD(x) (((x) & 0x03) << 27) 887 #define G_008DFC_OMOD(x) (((x) >> 27) & 0x03) 888 #define C_008DFC_OMOD 0xE7FFFFFF 889 #define V_008DFC_SQ_OMOD_OFF 0x00 890 #define V_008DFC_SQ_OMOD_M2 0x01 891 #define V_008DFC_SQ_OMOD_M4 0x02 892 #define V_008DFC_SQ_OMOD_D2 0x03 893 #define S_008DFC_NEG(x) (((x) & 0x07) << 29) 894 #define G_008DFC_NEG(x) (((x) >> 29) & 0x07) 895 #define C_008DFC_NEG 0x1FFFFFFF 896 #define R_008DFC_SQ_MUBUF_1 0x008DFC 897 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) 898 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) 899 #define C_008DFC_VADDR 0xFFFFFF00 900 #define V_008DFC_SQ_VGPR 0x00 901 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) 902 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) 903 #define C_008DFC_VDATA 0xFFFF00FF 904 #define V_008DFC_SQ_VGPR 0x00 905 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) 906 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) 907 #define C_008DFC_SRSRC 0xFFE0FFFF 908 #define S_008DFC_SLC(x) (((x) & 0x1) << 22) 909 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1) 910 #define C_008DFC_SLC 0xFFBFFFFF 911 #define S_008DFC_TFE(x) (((x) & 0x1) << 23) 912 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1) 913 #define C_008DFC_TFE 0xFF7FFFFF 914 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) 915 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) 916 #define C_008DFC_SOFFSET 0x00FFFFFF 917 #define V_008DFC_SQ_SGPR 0x00 918 #define V_008DFC_SQ_VCC_LO 0x6A 919 #define V_008DFC_SQ_VCC_HI 0x6B 920 #define V_008DFC_SQ_TBA_LO 0x6C 921 #define V_008DFC_SQ_TBA_HI 0x6D 922 #define V_008DFC_SQ_TMA_LO 0x6E 923 #define V_008DFC_SQ_TMA_HI 0x6F 924 #define V_008DFC_SQ_TTMP0 0x70 925 #define V_008DFC_SQ_TTMP1 0x71 926 #define V_008DFC_SQ_TTMP2 0x72 927 #define V_008DFC_SQ_TTMP3 0x73 928 #define V_008DFC_SQ_TTMP4 0x74 929 #define V_008DFC_SQ_TTMP5 0x75 930 #define V_008DFC_SQ_TTMP6 0x76 931 #define V_008DFC_SQ_TTMP7 0x77 932 #define V_008DFC_SQ_TTMP8 0x78 933 #define V_008DFC_SQ_TTMP9 0x79 934 #define V_008DFC_SQ_TTMP10 0x7A 935 #define V_008DFC_SQ_TTMP11 0x7B 936 #define V_008DFC_SQ_M0 0x7C 937 #define V_008DFC_SQ_EXEC_LO 0x7E 938 #define V_008DFC_SQ_EXEC_HI 0x7F 939 #define V_008DFC_SQ_SRC_0 0x80 940 #define V_008DFC_SQ_SRC_1_INT 0x81 941 #define V_008DFC_SQ_SRC_2_INT 0x82 942 #define V_008DFC_SQ_SRC_3_INT 0x83 943 #define V_008DFC_SQ_SRC_4_INT 0x84 944 #define V_008DFC_SQ_SRC_5_INT 0x85 945 #define V_008DFC_SQ_SRC_6_INT 0x86 946 #define V_008DFC_SQ_SRC_7_INT 0x87 947 #define V_008DFC_SQ_SRC_8_INT 0x88 948 #define V_008DFC_SQ_SRC_9_INT 0x89 949 #define V_008DFC_SQ_SRC_10_INT 0x8A 950 #define V_008DFC_SQ_SRC_11_INT 0x8B 951 #define V_008DFC_SQ_SRC_12_INT 0x8C 952 #define V_008DFC_SQ_SRC_13_INT 0x8D 953 #define V_008DFC_SQ_SRC_14_INT 0x8E 954 #define V_008DFC_SQ_SRC_15_INT 0x8F 955 #define V_008DFC_SQ_SRC_16_INT 0x90 956 #define V_008DFC_SQ_SRC_17_INT 0x91 957 #define V_008DFC_SQ_SRC_18_INT 0x92 958 #define V_008DFC_SQ_SRC_19_INT 0x93 959 #define V_008DFC_SQ_SRC_20_INT 0x94 960 #define V_008DFC_SQ_SRC_21_INT 0x95 961 #define V_008DFC_SQ_SRC_22_INT 0x96 962 #define V_008DFC_SQ_SRC_23_INT 0x97 963 #define V_008DFC_SQ_SRC_24_INT 0x98 964 #define V_008DFC_SQ_SRC_25_INT 0x99 965 #define V_008DFC_SQ_SRC_26_INT 0x9A 966 #define V_008DFC_SQ_SRC_27_INT 0x9B 967 #define V_008DFC_SQ_SRC_28_INT 0x9C 968 #define V_008DFC_SQ_SRC_29_INT 0x9D 969 #define V_008DFC_SQ_SRC_30_INT 0x9E 970 #define V_008DFC_SQ_SRC_31_INT 0x9F 971 #define V_008DFC_SQ_SRC_32_INT 0xA0 972 #define V_008DFC_SQ_SRC_33_INT 0xA1 973 #define V_008DFC_SQ_SRC_34_INT 0xA2 974 #define V_008DFC_SQ_SRC_35_INT 0xA3 975 #define V_008DFC_SQ_SRC_36_INT 0xA4 976 #define V_008DFC_SQ_SRC_37_INT 0xA5 977 #define V_008DFC_SQ_SRC_38_INT 0xA6 978 #define V_008DFC_SQ_SRC_39_INT 0xA7 979 #define V_008DFC_SQ_SRC_40_INT 0xA8 980 #define V_008DFC_SQ_SRC_41_INT 0xA9 981 #define V_008DFC_SQ_SRC_42_INT 0xAA 982 #define V_008DFC_SQ_SRC_43_INT 0xAB 983 #define V_008DFC_SQ_SRC_44_INT 0xAC 984 #define V_008DFC_SQ_SRC_45_INT 0xAD 985 #define V_008DFC_SQ_SRC_46_INT 0xAE 986 #define V_008DFC_SQ_SRC_47_INT 0xAF 987 #define V_008DFC_SQ_SRC_48_INT 0xB0 988 #define V_008DFC_SQ_SRC_49_INT 0xB1 989 #define V_008DFC_SQ_SRC_50_INT 0xB2 990 #define V_008DFC_SQ_SRC_51_INT 0xB3 991 #define V_008DFC_SQ_SRC_52_INT 0xB4 992 #define V_008DFC_SQ_SRC_53_INT 0xB5 993 #define V_008DFC_SQ_SRC_54_INT 0xB6 994 #define V_008DFC_SQ_SRC_55_INT 0xB7 995 #define V_008DFC_SQ_SRC_56_INT 0xB8 996 #define V_008DFC_SQ_SRC_57_INT 0xB9 997 #define V_008DFC_SQ_SRC_58_INT 0xBA 998 #define V_008DFC_SQ_SRC_59_INT 0xBB 999 #define V_008DFC_SQ_SRC_60_INT 0xBC 1000 #define V_008DFC_SQ_SRC_61_INT 0xBD 1001 #define V_008DFC_SQ_SRC_62_INT 0xBE 1002 #define V_008DFC_SQ_SRC_63_INT 0xBF 1003 #define V_008DFC_SQ_SRC_64_INT 0xC0 1004 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 1005 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 1006 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 1007 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 1008 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 1009 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 1010 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 1011 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 1012 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 1013 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 1014 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 1015 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 1016 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 1017 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 1018 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 1019 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 1020 #define V_008DFC_SQ_SRC_0_5 0xF0 1021 #define V_008DFC_SQ_SRC_M_0_5 0xF1 1022 #define V_008DFC_SQ_SRC_1 0xF2 1023 #define V_008DFC_SQ_SRC_M_1 0xF3 1024 #define V_008DFC_SQ_SRC_2 0xF4 1025 #define V_008DFC_SQ_SRC_M_2 0xF5 1026 #define V_008DFC_SQ_SRC_4 0xF6 1027 #define V_008DFC_SQ_SRC_M_4 0xF7 1028 #define V_008DFC_SQ_SRC_VCCZ 0xFB 1029 #define V_008DFC_SQ_SRC_EXECZ 0xFC 1030 #define V_008DFC_SQ_SRC_SCC 0xFD 1031 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 1032 #define R_008DFC_SQ_DS_0 0x008DFC 1033 #define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0) 1034 #define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF) 1035 #define C_008DFC_OFFSET0 0xFFFFFF00 1036 #define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8) 1037 #define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF) 1038 #define C_008DFC_OFFSET1 0xFFFF00FF 1039 #define S_008DFC_GDS(x) (((x) & 0x1) << 17) 1040 #define G_008DFC_GDS(x) (((x) >> 17) & 0x1) 1041 #define C_008DFC_GDS 0xFFFDFFFF 1042 #define S_008DFC_OP(x) (((x) & 0xFF) << 18) 1043 #define G_008DFC_OP(x) (((x) >> 18) & 0xFF) 1044 #define C_008DFC_OP 0xFC03FFFF 1045 #define V_008DFC_SQ_DS_ADD_U32 0x00 1046 #define V_008DFC_SQ_DS_SUB_U32 0x01 1047 #define V_008DFC_SQ_DS_RSUB_U32 0x02 1048 #define V_008DFC_SQ_DS_INC_U32 0x03 1049 #define V_008DFC_SQ_DS_DEC_U32 0x04 1050 #define V_008DFC_SQ_DS_MIN_I32 0x05 1051 #define V_008DFC_SQ_DS_MAX_I32 0x06 1052 #define V_008DFC_SQ_DS_MIN_U32 0x07 1053 #define V_008DFC_SQ_DS_MAX_U32 0x08 1054 #define V_008DFC_SQ_DS_AND_B32 0x09 1055 #define V_008DFC_SQ_DS_OR_B32 0x0A 1056 #define V_008DFC_SQ_DS_XOR_B32 0x0B 1057 #define V_008DFC_SQ_DS_MSKOR_B32 0x0C 1058 #define V_008DFC_SQ_DS_WRITE_B32 0x0D 1059 #define V_008DFC_SQ_DS_WRITE2_B32 0x0E 1060 #define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F 1061 #define V_008DFC_SQ_DS_CMPST_B32 0x10 1062 #define V_008DFC_SQ_DS_CMPST_F32 0x11 1063 #define V_008DFC_SQ_DS_MIN_F32 0x12 1064 #define V_008DFC_SQ_DS_MAX_F32 0x13 1065 #define V_008DFC_SQ_DS_GWS_INIT 0x19 1066 #define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A 1067 #define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B 1068 #define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C 1069 #define V_008DFC_SQ_DS_GWS_BARRIER 0x1D 1070 #define V_008DFC_SQ_DS_WRITE_B8 0x1E 1071 #define V_008DFC_SQ_DS_WRITE_B16 0x1F 1072 #define V_008DFC_SQ_DS_ADD_RTN_U32 0x20 1073 #define V_008DFC_SQ_DS_SUB_RTN_U32 0x21 1074 #define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22 1075 #define V_008DFC_SQ_DS_INC_RTN_U32 0x23 1076 #define V_008DFC_SQ_DS_DEC_RTN_U32 0x24 1077 #define V_008DFC_SQ_DS_MIN_RTN_I32 0x25 1078 #define V_008DFC_SQ_DS_MAX_RTN_I32 0x26 1079 #define V_008DFC_SQ_DS_MIN_RTN_U32 0x27 1080 #define V_008DFC_SQ_DS_MAX_RTN_U32 0x28 1081 #define V_008DFC_SQ_DS_AND_RTN_B32 0x29 1082 #define V_008DFC_SQ_DS_OR_RTN_B32 0x2A 1083 #define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B 1084 #define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C 1085 #define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D 1086 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E 1087 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F 1088 #define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30 1089 #define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31 1090 #define V_008DFC_SQ_DS_MIN_RTN_F32 0x32 1091 #define V_008DFC_SQ_DS_MAX_RTN_F32 0x33 1092 #define V_008DFC_SQ_DS_SWIZZLE_B32 0x35 1093 #define V_008DFC_SQ_DS_READ_B32 0x36 1094 #define V_008DFC_SQ_DS_READ2_B32 0x37 1095 #define V_008DFC_SQ_DS_READ2ST64_B32 0x38 1096 #define V_008DFC_SQ_DS_READ_I8 0x39 1097 #define V_008DFC_SQ_DS_READ_U8 0x3A 1098 #define V_008DFC_SQ_DS_READ_I16 0x3B 1099 #define V_008DFC_SQ_DS_READ_U16 0x3C 1100 #define V_008DFC_SQ_DS_CONSUME 0x3D 1101 #define V_008DFC_SQ_DS_APPEND 0x3E 1102 #define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F 1103 #define V_008DFC_SQ_DS_ADD_U64 0x40 1104 #define V_008DFC_SQ_DS_SUB_U64 0x41 1105 #define V_008DFC_SQ_DS_RSUB_U64 0x42 1106 #define V_008DFC_SQ_DS_INC_U64 0x43 1107 #define V_008DFC_SQ_DS_DEC_U64 0x44 1108 #define V_008DFC_SQ_DS_MIN_I64 0x45 1109 #define V_008DFC_SQ_DS_MAX_I64 0x46 1110 #define V_008DFC_SQ_DS_MIN_U64 0x47 1111 #define V_008DFC_SQ_DS_MAX_U64 0x48 1112 #define V_008DFC_SQ_DS_AND_B64 0x49 1113 #define V_008DFC_SQ_DS_OR_B64 0x4A 1114 #define V_008DFC_SQ_DS_XOR_B64 0x4B 1115 #define V_008DFC_SQ_DS_MSKOR_B64 0x4C 1116 #define V_008DFC_SQ_DS_WRITE_B64 0x4D 1117 #define V_008DFC_SQ_DS_WRITE2_B64 0x4E 1118 #define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F 1119 #define V_008DFC_SQ_DS_CMPST_B64 0x50 1120 #define V_008DFC_SQ_DS_CMPST_F64 0x51 1121 #define V_008DFC_SQ_DS_MIN_F64 0x52 1122 #define V_008DFC_SQ_DS_MAX_F64 0x53 1123 #define V_008DFC_SQ_DS_ADD_RTN_U64 0x60 1124 #define V_008DFC_SQ_DS_SUB_RTN_U64 0x61 1125 #define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62 1126 #define V_008DFC_SQ_DS_INC_RTN_U64 0x63 1127 #define V_008DFC_SQ_DS_DEC_RTN_U64 0x64 1128 #define V_008DFC_SQ_DS_MIN_RTN_I64 0x65 1129 #define V_008DFC_SQ_DS_MAX_RTN_I64 0x66 1130 #define V_008DFC_SQ_DS_MIN_RTN_U64 0x67 1131 #define V_008DFC_SQ_DS_MAX_RTN_U64 0x68 1132 #define V_008DFC_SQ_DS_AND_RTN_B64 0x69 1133 #define V_008DFC_SQ_DS_OR_RTN_B64 0x6A 1134 #define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B 1135 #define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C 1136 #define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D 1137 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E 1138 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F 1139 #define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70 1140 #define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71 1141 #define V_008DFC_SQ_DS_MIN_RTN_F64 0x72 1142 #define V_008DFC_SQ_DS_MAX_RTN_F64 0x73 1143 #define V_008DFC_SQ_DS_READ_B64 0x76 1144 #define V_008DFC_SQ_DS_READ2_B64 0x77 1145 #define V_008DFC_SQ_DS_READ2ST64_B64 0x78 1146 #define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80 1147 #define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81 1148 #define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82 1149 #define V_008DFC_SQ_DS_INC_SRC2_U32 0x83 1150 #define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84 1151 #define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85 1152 #define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86 1153 #define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87 1154 #define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88 1155 #define V_008DFC_SQ_DS_AND_SRC2_B32 0x89 1156 #define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A 1157 #define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B 1158 #define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D 1159 #define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92 1160 #define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93 1161 #define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0 1162 #define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1 1163 #define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2 1164 #define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3 1165 #define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4 1166 #define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5 1167 #define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6 1168 #define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7 1169 #define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8 1170 #define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9 1171 #define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA 1172 #define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB 1173 #define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD 1174 #define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2 1175 #define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3 1176 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 1177 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 1178 #define C_008DFC_ENCODING 0x03FFFFFF 1179 #define V_008DFC_SQ_ENC_DS_FIELD 0x36 1180 #define R_008DFC_SQ_SOPC 0x008DFC 1181 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) 1182 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) 1183 #define C_008DFC_SSRC0 0xFFFFFF00 1184 #define V_008DFC_SQ_SGPR 0x00 1185 #define V_008DFC_SQ_VCC_LO 0x6A 1186 #define V_008DFC_SQ_VCC_HI 0x6B 1187 #define V_008DFC_SQ_TBA_LO 0x6C 1188 #define V_008DFC_SQ_TBA_HI 0x6D 1189 #define V_008DFC_SQ_TMA_LO 0x6E 1190 #define V_008DFC_SQ_TMA_HI 0x6F 1191 #define V_008DFC_SQ_TTMP0 0x70 1192 #define V_008DFC_SQ_TTMP1 0x71 1193 #define V_008DFC_SQ_TTMP2 0x72 1194 #define V_008DFC_SQ_TTMP3 0x73 1195 #define V_008DFC_SQ_TTMP4 0x74 1196 #define V_008DFC_SQ_TTMP5 0x75 1197 #define V_008DFC_SQ_TTMP6 0x76 1198 #define V_008DFC_SQ_TTMP7 0x77 1199 #define V_008DFC_SQ_TTMP8 0x78 1200 #define V_008DFC_SQ_TTMP9 0x79 1201 #define V_008DFC_SQ_TTMP10 0x7A 1202 #define V_008DFC_SQ_TTMP11 0x7B 1203 #define V_008DFC_SQ_M0 0x7C 1204 #define V_008DFC_SQ_EXEC_LO 0x7E 1205 #define V_008DFC_SQ_EXEC_HI 0x7F 1206 #define V_008DFC_SQ_SRC_0 0x80 1207 #define V_008DFC_SQ_SRC_1_INT 0x81 1208 #define V_008DFC_SQ_SRC_2_INT 0x82 1209 #define V_008DFC_SQ_SRC_3_INT 0x83 1210 #define V_008DFC_SQ_SRC_4_INT 0x84 1211 #define V_008DFC_SQ_SRC_5_INT 0x85 1212 #define V_008DFC_SQ_SRC_6_INT 0x86 1213 #define V_008DFC_SQ_SRC_7_INT 0x87 1214 #define V_008DFC_SQ_SRC_8_INT 0x88 1215 #define V_008DFC_SQ_SRC_9_INT 0x89 1216 #define V_008DFC_SQ_SRC_10_INT 0x8A 1217 #define V_008DFC_SQ_SRC_11_INT 0x8B 1218 #define V_008DFC_SQ_SRC_12_INT 0x8C 1219 #define V_008DFC_SQ_SRC_13_INT 0x8D 1220 #define V_008DFC_SQ_SRC_14_INT 0x8E 1221 #define V_008DFC_SQ_SRC_15_INT 0x8F 1222 #define V_008DFC_SQ_SRC_16_INT 0x90 1223 #define V_008DFC_SQ_SRC_17_INT 0x91 1224 #define V_008DFC_SQ_SRC_18_INT 0x92 1225 #define V_008DFC_SQ_SRC_19_INT 0x93 1226 #define V_008DFC_SQ_SRC_20_INT 0x94 1227 #define V_008DFC_SQ_SRC_21_INT 0x95 1228 #define V_008DFC_SQ_SRC_22_INT 0x96 1229 #define V_008DFC_SQ_SRC_23_INT 0x97 1230 #define V_008DFC_SQ_SRC_24_INT 0x98 1231 #define V_008DFC_SQ_SRC_25_INT 0x99 1232 #define V_008DFC_SQ_SRC_26_INT 0x9A 1233 #define V_008DFC_SQ_SRC_27_INT 0x9B 1234 #define V_008DFC_SQ_SRC_28_INT 0x9C 1235 #define V_008DFC_SQ_SRC_29_INT 0x9D 1236 #define V_008DFC_SQ_SRC_30_INT 0x9E 1237 #define V_008DFC_SQ_SRC_31_INT 0x9F 1238 #define V_008DFC_SQ_SRC_32_INT 0xA0 1239 #define V_008DFC_SQ_SRC_33_INT 0xA1 1240 #define V_008DFC_SQ_SRC_34_INT 0xA2 1241 #define V_008DFC_SQ_SRC_35_INT 0xA3 1242 #define V_008DFC_SQ_SRC_36_INT 0xA4 1243 #define V_008DFC_SQ_SRC_37_INT 0xA5 1244 #define V_008DFC_SQ_SRC_38_INT 0xA6 1245 #define V_008DFC_SQ_SRC_39_INT 0xA7 1246 #define V_008DFC_SQ_SRC_40_INT 0xA8 1247 #define V_008DFC_SQ_SRC_41_INT 0xA9 1248 #define V_008DFC_SQ_SRC_42_INT 0xAA 1249 #define V_008DFC_SQ_SRC_43_INT 0xAB 1250 #define V_008DFC_SQ_SRC_44_INT 0xAC 1251 #define V_008DFC_SQ_SRC_45_INT 0xAD 1252 #define V_008DFC_SQ_SRC_46_INT 0xAE 1253 #define V_008DFC_SQ_SRC_47_INT 0xAF 1254 #define V_008DFC_SQ_SRC_48_INT 0xB0 1255 #define V_008DFC_SQ_SRC_49_INT 0xB1 1256 #define V_008DFC_SQ_SRC_50_INT 0xB2 1257 #define V_008DFC_SQ_SRC_51_INT 0xB3 1258 #define V_008DFC_SQ_SRC_52_INT 0xB4 1259 #define V_008DFC_SQ_SRC_53_INT 0xB5 1260 #define V_008DFC_SQ_SRC_54_INT 0xB6 1261 #define V_008DFC_SQ_SRC_55_INT 0xB7 1262 #define V_008DFC_SQ_SRC_56_INT 0xB8 1263 #define V_008DFC_SQ_SRC_57_INT 0xB9 1264 #define V_008DFC_SQ_SRC_58_INT 0xBA 1265 #define V_008DFC_SQ_SRC_59_INT 0xBB 1266 #define V_008DFC_SQ_SRC_60_INT 0xBC 1267 #define V_008DFC_SQ_SRC_61_INT 0xBD 1268 #define V_008DFC_SQ_SRC_62_INT 0xBE 1269 #define V_008DFC_SQ_SRC_63_INT 0xBF 1270 #define V_008DFC_SQ_SRC_64_INT 0xC0 1271 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 1272 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 1273 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 1274 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 1275 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 1276 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 1277 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 1278 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 1279 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 1280 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 1281 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 1282 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 1283 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 1284 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 1285 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 1286 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 1287 #define V_008DFC_SQ_SRC_0_5 0xF0 1288 #define V_008DFC_SQ_SRC_M_0_5 0xF1 1289 #define V_008DFC_SQ_SRC_1 0xF2 1290 #define V_008DFC_SQ_SRC_M_1 0xF3 1291 #define V_008DFC_SQ_SRC_2 0xF4 1292 #define V_008DFC_SQ_SRC_M_2 0xF5 1293 #define V_008DFC_SQ_SRC_4 0xF6 1294 #define V_008DFC_SQ_SRC_M_4 0xF7 1295 #define V_008DFC_SQ_SRC_VCCZ 0xFB 1296 #define V_008DFC_SQ_SRC_EXECZ 0xFC 1297 #define V_008DFC_SQ_SRC_SCC 0xFD 1298 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 1299 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) 1300 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) 1301 #define C_008DFC_SSRC1 0xFFFF00FF 1302 #define V_008DFC_SQ_SGPR 0x00 1303 #define V_008DFC_SQ_VCC_LO 0x6A 1304 #define V_008DFC_SQ_VCC_HI 0x6B 1305 #define V_008DFC_SQ_TBA_LO 0x6C 1306 #define V_008DFC_SQ_TBA_HI 0x6D 1307 #define V_008DFC_SQ_TMA_LO 0x6E 1308 #define V_008DFC_SQ_TMA_HI 0x6F 1309 #define V_008DFC_SQ_TTMP0 0x70 1310 #define V_008DFC_SQ_TTMP1 0x71 1311 #define V_008DFC_SQ_TTMP2 0x72 1312 #define V_008DFC_SQ_TTMP3 0x73 1313 #define V_008DFC_SQ_TTMP4 0x74 1314 #define V_008DFC_SQ_TTMP5 0x75 1315 #define V_008DFC_SQ_TTMP6 0x76 1316 #define V_008DFC_SQ_TTMP7 0x77 1317 #define V_008DFC_SQ_TTMP8 0x78 1318 #define V_008DFC_SQ_TTMP9 0x79 1319 #define V_008DFC_SQ_TTMP10 0x7A 1320 #define V_008DFC_SQ_TTMP11 0x7B 1321 #define V_008DFC_SQ_M0 0x7C 1322 #define V_008DFC_SQ_EXEC_LO 0x7E 1323 #define V_008DFC_SQ_EXEC_HI 0x7F 1324 #define V_008DFC_SQ_SRC_0 0x80 1325 #define V_008DFC_SQ_SRC_1_INT 0x81 1326 #define V_008DFC_SQ_SRC_2_INT 0x82 1327 #define V_008DFC_SQ_SRC_3_INT 0x83 1328 #define V_008DFC_SQ_SRC_4_INT 0x84 1329 #define V_008DFC_SQ_SRC_5_INT 0x85 1330 #define V_008DFC_SQ_SRC_6_INT 0x86 1331 #define V_008DFC_SQ_SRC_7_INT 0x87 1332 #define V_008DFC_SQ_SRC_8_INT 0x88 1333 #define V_008DFC_SQ_SRC_9_INT 0x89 1334 #define V_008DFC_SQ_SRC_10_INT 0x8A 1335 #define V_008DFC_SQ_SRC_11_INT 0x8B 1336 #define V_008DFC_SQ_SRC_12_INT 0x8C 1337 #define V_008DFC_SQ_SRC_13_INT 0x8D 1338 #define V_008DFC_SQ_SRC_14_INT 0x8E 1339 #define V_008DFC_SQ_SRC_15_INT 0x8F 1340 #define V_008DFC_SQ_SRC_16_INT 0x90 1341 #define V_008DFC_SQ_SRC_17_INT 0x91 1342 #define V_008DFC_SQ_SRC_18_INT 0x92 1343 #define V_008DFC_SQ_SRC_19_INT 0x93 1344 #define V_008DFC_SQ_SRC_20_INT 0x94 1345 #define V_008DFC_SQ_SRC_21_INT 0x95 1346 #define V_008DFC_SQ_SRC_22_INT 0x96 1347 #define V_008DFC_SQ_SRC_23_INT 0x97 1348 #define V_008DFC_SQ_SRC_24_INT 0x98 1349 #define V_008DFC_SQ_SRC_25_INT 0x99 1350 #define V_008DFC_SQ_SRC_26_INT 0x9A 1351 #define V_008DFC_SQ_SRC_27_INT 0x9B 1352 #define V_008DFC_SQ_SRC_28_INT 0x9C 1353 #define V_008DFC_SQ_SRC_29_INT 0x9D 1354 #define V_008DFC_SQ_SRC_30_INT 0x9E 1355 #define V_008DFC_SQ_SRC_31_INT 0x9F 1356 #define V_008DFC_SQ_SRC_32_INT 0xA0 1357 #define V_008DFC_SQ_SRC_33_INT 0xA1 1358 #define V_008DFC_SQ_SRC_34_INT 0xA2 1359 #define V_008DFC_SQ_SRC_35_INT 0xA3 1360 #define V_008DFC_SQ_SRC_36_INT 0xA4 1361 #define V_008DFC_SQ_SRC_37_INT 0xA5 1362 #define V_008DFC_SQ_SRC_38_INT 0xA6 1363 #define V_008DFC_SQ_SRC_39_INT 0xA7 1364 #define V_008DFC_SQ_SRC_40_INT 0xA8 1365 #define V_008DFC_SQ_SRC_41_INT 0xA9 1366 #define V_008DFC_SQ_SRC_42_INT 0xAA 1367 #define V_008DFC_SQ_SRC_43_INT 0xAB 1368 #define V_008DFC_SQ_SRC_44_INT 0xAC 1369 #define V_008DFC_SQ_SRC_45_INT 0xAD 1370 #define V_008DFC_SQ_SRC_46_INT 0xAE 1371 #define V_008DFC_SQ_SRC_47_INT 0xAF 1372 #define V_008DFC_SQ_SRC_48_INT 0xB0 1373 #define V_008DFC_SQ_SRC_49_INT 0xB1 1374 #define V_008DFC_SQ_SRC_50_INT 0xB2 1375 #define V_008DFC_SQ_SRC_51_INT 0xB3 1376 #define V_008DFC_SQ_SRC_52_INT 0xB4 1377 #define V_008DFC_SQ_SRC_53_INT 0xB5 1378 #define V_008DFC_SQ_SRC_54_INT 0xB6 1379 #define V_008DFC_SQ_SRC_55_INT 0xB7 1380 #define V_008DFC_SQ_SRC_56_INT 0xB8 1381 #define V_008DFC_SQ_SRC_57_INT 0xB9 1382 #define V_008DFC_SQ_SRC_58_INT 0xBA 1383 #define V_008DFC_SQ_SRC_59_INT 0xBB 1384 #define V_008DFC_SQ_SRC_60_INT 0xBC 1385 #define V_008DFC_SQ_SRC_61_INT 0xBD 1386 #define V_008DFC_SQ_SRC_62_INT 0xBE 1387 #define V_008DFC_SQ_SRC_63_INT 0xBF 1388 #define V_008DFC_SQ_SRC_64_INT 0xC0 1389 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 1390 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 1391 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 1392 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 1393 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 1394 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 1395 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 1396 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 1397 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 1398 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 1399 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 1400 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 1401 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 1402 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 1403 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 1404 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 1405 #define V_008DFC_SQ_SRC_0_5 0xF0 1406 #define V_008DFC_SQ_SRC_M_0_5 0xF1 1407 #define V_008DFC_SQ_SRC_1 0xF2 1408 #define V_008DFC_SQ_SRC_M_1 0xF3 1409 #define V_008DFC_SQ_SRC_2 0xF4 1410 #define V_008DFC_SQ_SRC_M_2 0xF5 1411 #define V_008DFC_SQ_SRC_4 0xF6 1412 #define V_008DFC_SQ_SRC_M_4 0xF7 1413 #define V_008DFC_SQ_SRC_VCCZ 0xFB 1414 #define V_008DFC_SQ_SRC_EXECZ 0xFC 1415 #define V_008DFC_SQ_SRC_SCC 0xFD 1416 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 1417 #define S_008DFC_OP(x) (((x) & 0x7F) << 16) 1418 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F) 1419 #define C_008DFC_OP 0xFF80FFFF 1420 #define V_008DFC_SQ_S_CMP_EQ_I32 0x00 1421 #define V_008DFC_SQ_S_CMP_LG_I32 0x01 1422 #define V_008DFC_SQ_S_CMP_GT_I32 0x02 1423 #define V_008DFC_SQ_S_CMP_GE_I32 0x03 1424 #define V_008DFC_SQ_S_CMP_LT_I32 0x04 1425 #define V_008DFC_SQ_S_CMP_LE_I32 0x05 1426 #define V_008DFC_SQ_S_CMP_EQ_U32 0x06 1427 #define V_008DFC_SQ_S_CMP_LG_U32 0x07 1428 #define V_008DFC_SQ_S_CMP_GT_U32 0x08 1429 #define V_008DFC_SQ_S_CMP_GE_U32 0x09 1430 #define V_008DFC_SQ_S_CMP_LT_U32 0x0A 1431 #define V_008DFC_SQ_S_CMP_LE_U32 0x0B 1432 #define V_008DFC_SQ_S_BITCMP0_B32 0x0C 1433 #define V_008DFC_SQ_S_BITCMP1_B32 0x0D 1434 #define V_008DFC_SQ_S_BITCMP0_B64 0x0E 1435 #define V_008DFC_SQ_S_BITCMP1_B64 0x0F 1436 #define V_008DFC_SQ_S_SETVSKIP 0x10 1437 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) 1438 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) 1439 #define C_008DFC_ENCODING 0x007FFFFF 1440 #define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E 1441 #endif 1442 #define R_008DFC_SQ_EXP_0 0x008DFC 1443 #define S_008DFC_EN(x) (((x) & 0x0F) << 0) 1444 #define G_008DFC_EN(x) (((x) >> 0) & 0x0F) 1445 #define C_008DFC_EN 0xFFFFFFF0 1446 #define S_008DFC_TGT(x) (((x) & 0x3F) << 4) 1447 #define G_008DFC_TGT(x) (((x) >> 4) & 0x3F) 1448 #define C_008DFC_TGT 0xFFFFFC0F 1449 #define V_008DFC_SQ_EXP_MRT 0x00 1450 #define V_008DFC_SQ_EXP_MRTZ 0x08 1451 #define V_008DFC_SQ_EXP_NULL 0x09 1452 #define V_008DFC_SQ_EXP_POS 0x0C 1453 #define V_008DFC_SQ_EXP_PARAM 0x20 1454 #define S_008DFC_COMPR(x) (((x) & 0x1) << 10) 1455 #define G_008DFC_COMPR(x) (((x) >> 10) & 0x1) 1456 #define C_008DFC_COMPR 0xFFFFFBFF 1457 #define S_008DFC_DONE(x) (((x) & 0x1) << 11) 1458 #define G_008DFC_DONE(x) (((x) >> 11) & 0x1) 1459 #define C_008DFC_DONE 0xFFFFF7FF 1460 #define S_008DFC_VM(x) (((x) & 0x1) << 12) 1461 #define G_008DFC_VM(x) (((x) >> 12) & 0x1) 1462 #define C_008DFC_VM 0xFFFFEFFF 1463 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 1464 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 1465 #define C_008DFC_ENCODING 0x03FFFFFF 1466 #define V_008DFC_SQ_ENC_EXP_FIELD 0x3E 1467 #if 0 1468 #define R_008DFC_SQ_MIMG_0 0x008DFC 1469 #define S_008DFC_DMASK(x) (((x) & 0x0F) << 8) 1470 #define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F) 1471 #define C_008DFC_DMASK 0xFFFFF0FF 1472 #define S_008DFC_UNORM(x) (((x) & 0x1) << 12) 1473 #define G_008DFC_UNORM(x) (((x) >> 12) & 0x1) 1474 #define C_008DFC_UNORM 0xFFFFEFFF 1475 #define S_008DFC_GLC(x) (((x) & 0x1) << 13) 1476 #define G_008DFC_GLC(x) (((x) >> 13) & 0x1) 1477 #define C_008DFC_GLC 0xFFFFDFFF 1478 #define S_008DFC_DA(x) (((x) & 0x1) << 14) 1479 #define G_008DFC_DA(x) (((x) >> 14) & 0x1) 1480 #define C_008DFC_DA 0xFFFFBFFF 1481 #define S_008DFC_R128(x) (((x) & 0x1) << 15) 1482 #define G_008DFC_R128(x) (((x) >> 15) & 0x1) 1483 #define C_008DFC_R128 0xFFFF7FFF 1484 #define S_008DFC_TFE(x) (((x) & 0x1) << 16) 1485 #define G_008DFC_TFE(x) (((x) >> 16) & 0x1) 1486 #define C_008DFC_TFE 0xFFFEFFFF 1487 #define S_008DFC_LWE(x) (((x) & 0x1) << 17) 1488 #define G_008DFC_LWE(x) (((x) >> 17) & 0x1) 1489 #define C_008DFC_LWE 0xFFFDFFFF 1490 #define S_008DFC_OP(x) (((x) & 0x7F) << 18) 1491 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F) 1492 #define C_008DFC_OP 0xFE03FFFF 1493 #define V_008DFC_SQ_IMAGE_LOAD 0x00 1494 #define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01 1495 #define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02 1496 #define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03 1497 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04 1498 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05 1499 #define V_008DFC_SQ_IMAGE_STORE 0x08 1500 #define V_008DFC_SQ_IMAGE_STORE_MIP 0x09 1501 #define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A 1502 #define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B 1503 #define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E 1504 #define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F 1505 #define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10 1506 #define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11 1507 #define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12 1508 #define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13 1509 #define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14 1510 #define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15 1511 #define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16 1512 #define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17 1513 #define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18 1514 #define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19 1515 #define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A 1516 #define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B 1517 #define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C 1518 #define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D 1519 #define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E 1520 #define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F 1521 #define V_008DFC_SQ_IMAGE_SAMPLE 0x20 1522 #define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21 1523 #define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22 1524 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23 1525 #define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24 1526 #define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25 1527 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26 1528 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27 1529 #define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28 1530 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29 1531 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A 1532 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B 1533 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C 1534 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D 1535 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E 1536 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F 1537 #define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30 1538 #define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31 1539 #define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32 1540 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33 1541 #define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34 1542 #define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35 1543 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36 1544 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37 1545 #define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38 1546 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39 1547 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A 1548 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B 1549 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C 1550 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D 1551 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E 1552 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F 1553 #define V_008DFC_SQ_IMAGE_GATHER4 0x40 1554 #define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41 1555 #define V_008DFC_SQ_IMAGE_GATHER4_L 0x44 1556 #define V_008DFC_SQ_IMAGE_GATHER4_B 0x45 1557 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46 1558 #define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47 1559 #define V_008DFC_SQ_IMAGE_GATHER4_C 0x48 1560 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49 1561 #define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C 1562 #define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D 1563 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E 1564 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F 1565 #define V_008DFC_SQ_IMAGE_GATHER4_O 0x50 1566 #define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51 1567 #define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54 1568 #define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55 1569 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56 1570 #define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57 1571 #define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58 1572 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59 1573 #define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C 1574 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D 1575 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E 1576 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F 1577 #define V_008DFC_SQ_IMAGE_GET_LOD 0x60 1578 #define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68 1579 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69 1580 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A 1581 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B 1582 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C 1583 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D 1584 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E 1585 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F 1586 #define V_008DFC_SQ_IMAGE_RSRC256 0x7E 1587 #define V_008DFC_SQ_IMAGE_SAMPLER 0x7F 1588 #define S_008DFC_SLC(x) (((x) & 0x1) << 25) 1589 #define G_008DFC_SLC(x) (((x) >> 25) & 0x1) 1590 #define C_008DFC_SLC 0xFDFFFFFF 1591 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 1592 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 1593 #define C_008DFC_ENCODING 0x03FFFFFF 1594 #define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C 1595 #define R_008DFC_SQ_SOPP 0x008DFC 1596 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) 1597 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) 1598 #define C_008DFC_SIMM16 0xFFFF0000 1599 #define S_008DFC_OP(x) (((x) & 0x7F) << 16) 1600 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F) 1601 #define C_008DFC_OP 0xFF80FFFF 1602 #define V_008DFC_SQ_S_NOP 0x00 1603 #define V_008DFC_SQ_S_ENDPGM 0x01 1604 #define V_008DFC_SQ_S_BRANCH 0x02 1605 #define V_008DFC_SQ_S_CBRANCH_SCC0 0x04 1606 #define V_008DFC_SQ_S_CBRANCH_SCC1 0x05 1607 #define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06 1608 #define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07 1609 #define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08 1610 #define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09 1611 #define V_008DFC_SQ_S_BARRIER 0x0A 1612 #define V_008DFC_SQ_S_WAITCNT 0x0C 1613 #define V_008DFC_SQ_S_SETHALT 0x0D 1614 #define V_008DFC_SQ_S_SLEEP 0x0E 1615 #define V_008DFC_SQ_S_SETPRIO 0x0F 1616 #define V_008DFC_SQ_S_SENDMSG 0x10 1617 #define V_008DFC_SQ_S_SENDMSGHALT 0x11 1618 #define V_008DFC_SQ_S_TRAP 0x12 1619 #define V_008DFC_SQ_S_ICACHE_INV 0x13 1620 #define V_008DFC_SQ_S_INCPERFLEVEL 0x14 1621 #define V_008DFC_SQ_S_DECPERFLEVEL 0x15 1622 #define V_008DFC_SQ_S_TTRACEDATA 0x16 1623 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) 1624 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) 1625 #define C_008DFC_ENCODING 0x007FFFFF 1626 #define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F 1627 #define R_008DFC_SQ_VINTRP 0x008DFC 1628 #define S_008DFC_VSRC(x) (((x) & 0xFF) << 0) 1629 #define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF) 1630 #define C_008DFC_VSRC 0xFFFFFF00 1631 #define V_008DFC_SQ_VGPR 0x00 1632 #define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8) 1633 #define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03) 1634 #define C_008DFC_ATTRCHAN 0xFFFFFCFF 1635 #define V_008DFC_SQ_CHAN_X 0x00 1636 #define V_008DFC_SQ_CHAN_Y 0x01 1637 #define V_008DFC_SQ_CHAN_Z 0x02 1638 #define V_008DFC_SQ_CHAN_W 0x03 1639 #define S_008DFC_ATTR(x) (((x) & 0x3F) << 10) 1640 #define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F) 1641 #define C_008DFC_ATTR 0xFFFF03FF 1642 #define V_008DFC_SQ_ATTR 0x00 1643 #define S_008DFC_OP(x) (((x) & 0x03) << 16) 1644 #define G_008DFC_OP(x) (((x) >> 16) & 0x03) 1645 #define C_008DFC_OP 0xFFFCFFFF 1646 #define V_008DFC_SQ_V_INTERP_P1_F32 0x00 1647 #define V_008DFC_SQ_V_INTERP_P2_F32 0x01 1648 #define V_008DFC_SQ_V_INTERP_MOV_F32 0x02 1649 #define S_008DFC_VDST(x) (((x) & 0xFF) << 18) 1650 #define G_008DFC_VDST(x) (((x) >> 18) & 0xFF) 1651 #define C_008DFC_VDST 0xFC03FFFF 1652 #define V_008DFC_SQ_VGPR 0x00 1653 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 1654 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 1655 #define C_008DFC_ENCODING 0x03FFFFFF 1656 #define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32 1657 #define R_008DFC_SQ_MTBUF_0 0x008DFC 1658 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) 1659 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) 1660 #define C_008DFC_OFFSET 0xFFFFF000 1661 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) 1662 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) 1663 #define C_008DFC_OFFEN 0xFFFFEFFF 1664 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) 1665 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) 1666 #define C_008DFC_IDXEN 0xFFFFDFFF 1667 #define S_008DFC_GLC(x) (((x) & 0x1) << 14) 1668 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1) 1669 #define C_008DFC_GLC 0xFFFFBFFF 1670 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) 1671 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) 1672 #define C_008DFC_ADDR64 0xFFFF7FFF 1673 #define S_008DFC_OP(x) (((x) & 0x07) << 16) 1674 #define G_008DFC_OP(x) (((x) >> 16) & 0x07) 1675 #define C_008DFC_OP 0xFFF8FFFF 1676 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00 1677 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01 1678 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02 1679 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03 1680 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04 1681 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05 1682 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06 1683 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07 1684 #define S_008DFC_DFMT(x) (((x) & 0x0F) << 19) 1685 #define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F) 1686 #define C_008DFC_DFMT 0xFF87FFFF 1687 #define S_008DFC_NFMT(x) (((x) & 0x07) << 23) 1688 #define G_008DFC_NFMT(x) (((x) >> 23) & 0x07) 1689 #define C_008DFC_NFMT 0xFC7FFFFF 1690 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 1691 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 1692 #define C_008DFC_ENCODING 0x03FFFFFF 1693 #define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A 1694 #define R_008DFC_SQ_SMRD 0x008DFC 1695 #define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0) 1696 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF) 1697 #define C_008DFC_OFFSET 0xFFFFFF00 1698 #define V_008DFC_SQ_SGPR 0x00 1699 #define V_008DFC_SQ_VCC_LO 0x6A 1700 #define V_008DFC_SQ_VCC_HI 0x6B 1701 #define V_008DFC_SQ_TBA_LO 0x6C 1702 #define V_008DFC_SQ_TBA_HI 0x6D 1703 #define V_008DFC_SQ_TMA_LO 0x6E 1704 #define V_008DFC_SQ_TMA_HI 0x6F 1705 #define V_008DFC_SQ_TTMP0 0x70 1706 #define V_008DFC_SQ_TTMP1 0x71 1707 #define V_008DFC_SQ_TTMP2 0x72 1708 #define V_008DFC_SQ_TTMP3 0x73 1709 #define V_008DFC_SQ_TTMP4 0x74 1710 #define V_008DFC_SQ_TTMP5 0x75 1711 #define V_008DFC_SQ_TTMP6 0x76 1712 #define V_008DFC_SQ_TTMP7 0x77 1713 #define V_008DFC_SQ_TTMP8 0x78 1714 #define V_008DFC_SQ_TTMP9 0x79 1715 #define V_008DFC_SQ_TTMP10 0x7A 1716 #define V_008DFC_SQ_TTMP11 0x7B 1717 #define S_008DFC_IMM(x) (((x) & 0x1) << 8) 1718 #define G_008DFC_IMM(x) (((x) >> 8) & 0x1) 1719 #define C_008DFC_IMM 0xFFFFFEFF 1720 #define S_008DFC_SBASE(x) (((x) & 0x3F) << 9) 1721 #define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F) 1722 #define C_008DFC_SBASE 0xFFFF81FF 1723 #define S_008DFC_SDST(x) (((x) & 0x7F) << 15) 1724 #define G_008DFC_SDST(x) (((x) >> 15) & 0x7F) 1725 #define C_008DFC_SDST 0xFFC07FFF 1726 #define V_008DFC_SQ_SGPR 0x00 1727 #define V_008DFC_SQ_VCC_LO 0x6A 1728 #define V_008DFC_SQ_VCC_HI 0x6B 1729 #define V_008DFC_SQ_TBA_LO 0x6C 1730 #define V_008DFC_SQ_TBA_HI 0x6D 1731 #define V_008DFC_SQ_TMA_LO 0x6E 1732 #define V_008DFC_SQ_TMA_HI 0x6F 1733 #define V_008DFC_SQ_TTMP0 0x70 1734 #define V_008DFC_SQ_TTMP1 0x71 1735 #define V_008DFC_SQ_TTMP2 0x72 1736 #define V_008DFC_SQ_TTMP3 0x73 1737 #define V_008DFC_SQ_TTMP4 0x74 1738 #define V_008DFC_SQ_TTMP5 0x75 1739 #define V_008DFC_SQ_TTMP6 0x76 1740 #define V_008DFC_SQ_TTMP7 0x77 1741 #define V_008DFC_SQ_TTMP8 0x78 1742 #define V_008DFC_SQ_TTMP9 0x79 1743 #define V_008DFC_SQ_TTMP10 0x7A 1744 #define V_008DFC_SQ_TTMP11 0x7B 1745 #define V_008DFC_SQ_M0 0x7C 1746 #define V_008DFC_SQ_EXEC_LO 0x7E 1747 #define V_008DFC_SQ_EXEC_HI 0x7F 1748 #define S_008DFC_OP(x) (((x) & 0x1F) << 22) 1749 #define G_008DFC_OP(x) (((x) >> 22) & 0x1F) 1750 #define C_008DFC_OP 0xF83FFFFF 1751 #define V_008DFC_SQ_S_LOAD_DWORD 0x00 1752 #define V_008DFC_SQ_S_LOAD_DWORDX2 0x01 1753 #define V_008DFC_SQ_S_LOAD_DWORDX4 0x02 1754 #define V_008DFC_SQ_S_LOAD_DWORDX8 0x03 1755 #define V_008DFC_SQ_S_LOAD_DWORDX16 0x04 1756 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08 1757 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09 1758 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A 1759 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B 1760 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C 1761 #define V_008DFC_SQ_S_MEMTIME 0x1E 1762 #define V_008DFC_SQ_S_DCACHE_INV 0x1F 1763 #define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27) 1764 #define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F) 1765 #define C_008DFC_ENCODING 0x07FFFFFF 1766 #define V_008DFC_SQ_ENC_SMRD_FIELD 0x18 1767 #define R_008DFC_SQ_EXP_1 0x008DFC 1768 #define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0) 1769 #define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF) 1770 #define C_008DFC_VSRC0 0xFFFFFF00 1771 #define V_008DFC_SQ_VGPR 0x00 1772 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8) 1773 #define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF) 1774 #define C_008DFC_VSRC1 0xFFFF00FF 1775 #define V_008DFC_SQ_VGPR 0x00 1776 #define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16) 1777 #define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF) 1778 #define C_008DFC_VSRC2 0xFF00FFFF 1779 #define V_008DFC_SQ_VGPR 0x00 1780 #define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24) 1781 #define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF) 1782 #define C_008DFC_VSRC3 0x00FFFFFF 1783 #define V_008DFC_SQ_VGPR 0x00 1784 #define R_008DFC_SQ_DS_1 0x008DFC 1785 #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0) 1786 #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF) 1787 #define C_008DFC_ADDR 0xFFFFFF00 1788 #define V_008DFC_SQ_VGPR 0x00 1789 #define S_008DFC_DATA0(x) (((x) & 0xFF) << 8) 1790 #define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF) 1791 #define C_008DFC_DATA0 0xFFFF00FF 1792 #define V_008DFC_SQ_VGPR 0x00 1793 #define S_008DFC_DATA1(x) (((x) & 0xFF) << 16) 1794 #define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF) 1795 #define C_008DFC_DATA1 0xFF00FFFF 1796 #define V_008DFC_SQ_VGPR 0x00 1797 #define S_008DFC_VDST(x) (((x) & 0xFF) << 24) 1798 #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF) 1799 #define C_008DFC_VDST 0x00FFFFFF 1800 #define V_008DFC_SQ_VGPR 0x00 1801 #define R_008DFC_SQ_VOPC 0x008DFC 1802 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) 1803 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) 1804 #define C_008DFC_SRC0 0xFFFFFE00 1805 #define V_008DFC_SQ_SGPR 0x00 1806 #define V_008DFC_SQ_VCC_LO 0x6A 1807 #define V_008DFC_SQ_VCC_HI 0x6B 1808 #define V_008DFC_SQ_TBA_LO 0x6C 1809 #define V_008DFC_SQ_TBA_HI 0x6D 1810 #define V_008DFC_SQ_TMA_LO 0x6E 1811 #define V_008DFC_SQ_TMA_HI 0x6F 1812 #define V_008DFC_SQ_TTMP0 0x70 1813 #define V_008DFC_SQ_TTMP1 0x71 1814 #define V_008DFC_SQ_TTMP2 0x72 1815 #define V_008DFC_SQ_TTMP3 0x73 1816 #define V_008DFC_SQ_TTMP4 0x74 1817 #define V_008DFC_SQ_TTMP5 0x75 1818 #define V_008DFC_SQ_TTMP6 0x76 1819 #define V_008DFC_SQ_TTMP7 0x77 1820 #define V_008DFC_SQ_TTMP8 0x78 1821 #define V_008DFC_SQ_TTMP9 0x79 1822 #define V_008DFC_SQ_TTMP10 0x7A 1823 #define V_008DFC_SQ_TTMP11 0x7B 1824 #define V_008DFC_SQ_M0 0x7C 1825 #define V_008DFC_SQ_EXEC_LO 0x7E 1826 #define V_008DFC_SQ_EXEC_HI 0x7F 1827 #define V_008DFC_SQ_SRC_0 0x80 1828 #define V_008DFC_SQ_SRC_1_INT 0x81 1829 #define V_008DFC_SQ_SRC_2_INT 0x82 1830 #define V_008DFC_SQ_SRC_3_INT 0x83 1831 #define V_008DFC_SQ_SRC_4_INT 0x84 1832 #define V_008DFC_SQ_SRC_5_INT 0x85 1833 #define V_008DFC_SQ_SRC_6_INT 0x86 1834 #define V_008DFC_SQ_SRC_7_INT 0x87 1835 #define V_008DFC_SQ_SRC_8_INT 0x88 1836 #define V_008DFC_SQ_SRC_9_INT 0x89 1837 #define V_008DFC_SQ_SRC_10_INT 0x8A 1838 #define V_008DFC_SQ_SRC_11_INT 0x8B 1839 #define V_008DFC_SQ_SRC_12_INT 0x8C 1840 #define V_008DFC_SQ_SRC_13_INT 0x8D 1841 #define V_008DFC_SQ_SRC_14_INT 0x8E 1842 #define V_008DFC_SQ_SRC_15_INT 0x8F 1843 #define V_008DFC_SQ_SRC_16_INT 0x90 1844 #define V_008DFC_SQ_SRC_17_INT 0x91 1845 #define V_008DFC_SQ_SRC_18_INT 0x92 1846 #define V_008DFC_SQ_SRC_19_INT 0x93 1847 #define V_008DFC_SQ_SRC_20_INT 0x94 1848 #define V_008DFC_SQ_SRC_21_INT 0x95 1849 #define V_008DFC_SQ_SRC_22_INT 0x96 1850 #define V_008DFC_SQ_SRC_23_INT 0x97 1851 #define V_008DFC_SQ_SRC_24_INT 0x98 1852 #define V_008DFC_SQ_SRC_25_INT 0x99 1853 #define V_008DFC_SQ_SRC_26_INT 0x9A 1854 #define V_008DFC_SQ_SRC_27_INT 0x9B 1855 #define V_008DFC_SQ_SRC_28_INT 0x9C 1856 #define V_008DFC_SQ_SRC_29_INT 0x9D 1857 #define V_008DFC_SQ_SRC_30_INT 0x9E 1858 #define V_008DFC_SQ_SRC_31_INT 0x9F 1859 #define V_008DFC_SQ_SRC_32_INT 0xA0 1860 #define V_008DFC_SQ_SRC_33_INT 0xA1 1861 #define V_008DFC_SQ_SRC_34_INT 0xA2 1862 #define V_008DFC_SQ_SRC_35_INT 0xA3 1863 #define V_008DFC_SQ_SRC_36_INT 0xA4 1864 #define V_008DFC_SQ_SRC_37_INT 0xA5 1865 #define V_008DFC_SQ_SRC_38_INT 0xA6 1866 #define V_008DFC_SQ_SRC_39_INT 0xA7 1867 #define V_008DFC_SQ_SRC_40_INT 0xA8 1868 #define V_008DFC_SQ_SRC_41_INT 0xA9 1869 #define V_008DFC_SQ_SRC_42_INT 0xAA 1870 #define V_008DFC_SQ_SRC_43_INT 0xAB 1871 #define V_008DFC_SQ_SRC_44_INT 0xAC 1872 #define V_008DFC_SQ_SRC_45_INT 0xAD 1873 #define V_008DFC_SQ_SRC_46_INT 0xAE 1874 #define V_008DFC_SQ_SRC_47_INT 0xAF 1875 #define V_008DFC_SQ_SRC_48_INT 0xB0 1876 #define V_008DFC_SQ_SRC_49_INT 0xB1 1877 #define V_008DFC_SQ_SRC_50_INT 0xB2 1878 #define V_008DFC_SQ_SRC_51_INT 0xB3 1879 #define V_008DFC_SQ_SRC_52_INT 0xB4 1880 #define V_008DFC_SQ_SRC_53_INT 0xB5 1881 #define V_008DFC_SQ_SRC_54_INT 0xB6 1882 #define V_008DFC_SQ_SRC_55_INT 0xB7 1883 #define V_008DFC_SQ_SRC_56_INT 0xB8 1884 #define V_008DFC_SQ_SRC_57_INT 0xB9 1885 #define V_008DFC_SQ_SRC_58_INT 0xBA 1886 #define V_008DFC_SQ_SRC_59_INT 0xBB 1887 #define V_008DFC_SQ_SRC_60_INT 0xBC 1888 #define V_008DFC_SQ_SRC_61_INT 0xBD 1889 #define V_008DFC_SQ_SRC_62_INT 0xBE 1890 #define V_008DFC_SQ_SRC_63_INT 0xBF 1891 #define V_008DFC_SQ_SRC_64_INT 0xC0 1892 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 1893 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 1894 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 1895 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 1896 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 1897 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 1898 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 1899 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 1900 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 1901 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 1902 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 1903 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 1904 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 1905 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 1906 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 1907 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 1908 #define V_008DFC_SQ_SRC_0_5 0xF0 1909 #define V_008DFC_SQ_SRC_M_0_5 0xF1 1910 #define V_008DFC_SQ_SRC_1 0xF2 1911 #define V_008DFC_SQ_SRC_M_1 0xF3 1912 #define V_008DFC_SQ_SRC_2 0xF4 1913 #define V_008DFC_SQ_SRC_M_2 0xF5 1914 #define V_008DFC_SQ_SRC_4 0xF6 1915 #define V_008DFC_SQ_SRC_M_4 0xF7 1916 #define V_008DFC_SQ_SRC_VCCZ 0xFB 1917 #define V_008DFC_SQ_SRC_EXECZ 0xFC 1918 #define V_008DFC_SQ_SRC_SCC 0xFD 1919 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 1920 #define V_008DFC_SQ_SRC_VGPR 0x100 1921 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) 1922 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) 1923 #define C_008DFC_VSRC1 0xFFFE01FF 1924 #define V_008DFC_SQ_VGPR 0x00 1925 #define S_008DFC_OP(x) (((x) & 0xFF) << 17) 1926 #define G_008DFC_OP(x) (((x) >> 17) & 0xFF) 1927 #define C_008DFC_OP 0xFE01FFFF 1928 #define V_008DFC_SQ_V_CMP_F_F32 0x00 1929 #define V_008DFC_SQ_V_CMP_LT_F32 0x01 1930 #define V_008DFC_SQ_V_CMP_EQ_F32 0x02 1931 #define V_008DFC_SQ_V_CMP_LE_F32 0x03 1932 #define V_008DFC_SQ_V_CMP_GT_F32 0x04 1933 #define V_008DFC_SQ_V_CMP_LG_F32 0x05 1934 #define V_008DFC_SQ_V_CMP_GE_F32 0x06 1935 #define V_008DFC_SQ_V_CMP_O_F32 0x07 1936 #define V_008DFC_SQ_V_CMP_U_F32 0x08 1937 #define V_008DFC_SQ_V_CMP_NGE_F32 0x09 1938 #define V_008DFC_SQ_V_CMP_NLG_F32 0x0A 1939 #define V_008DFC_SQ_V_CMP_NGT_F32 0x0B 1940 #define V_008DFC_SQ_V_CMP_NLE_F32 0x0C 1941 #define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D 1942 #define V_008DFC_SQ_V_CMP_NLT_F32 0x0E 1943 #define V_008DFC_SQ_V_CMP_TRU_F32 0x0F 1944 #define V_008DFC_SQ_V_CMPX_F_F32 0x10 1945 #define V_008DFC_SQ_V_CMPX_LT_F32 0x11 1946 #define V_008DFC_SQ_V_CMPX_EQ_F32 0x12 1947 #define V_008DFC_SQ_V_CMPX_LE_F32 0x13 1948 #define V_008DFC_SQ_V_CMPX_GT_F32 0x14 1949 #define V_008DFC_SQ_V_CMPX_LG_F32 0x15 1950 #define V_008DFC_SQ_V_CMPX_GE_F32 0x16 1951 #define V_008DFC_SQ_V_CMPX_O_F32 0x17 1952 #define V_008DFC_SQ_V_CMPX_U_F32 0x18 1953 #define V_008DFC_SQ_V_CMPX_NGE_F32 0x19 1954 #define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A 1955 #define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B 1956 #define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C 1957 #define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D 1958 #define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E 1959 #define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F 1960 #define V_008DFC_SQ_V_CMP_F_F64 0x20 1961 #define V_008DFC_SQ_V_CMP_LT_F64 0x21 1962 #define V_008DFC_SQ_V_CMP_EQ_F64 0x22 1963 #define V_008DFC_SQ_V_CMP_LE_F64 0x23 1964 #define V_008DFC_SQ_V_CMP_GT_F64 0x24 1965 #define V_008DFC_SQ_V_CMP_LG_F64 0x25 1966 #define V_008DFC_SQ_V_CMP_GE_F64 0x26 1967 #define V_008DFC_SQ_V_CMP_O_F64 0x27 1968 #define V_008DFC_SQ_V_CMP_U_F64 0x28 1969 #define V_008DFC_SQ_V_CMP_NGE_F64 0x29 1970 #define V_008DFC_SQ_V_CMP_NLG_F64 0x2A 1971 #define V_008DFC_SQ_V_CMP_NGT_F64 0x2B 1972 #define V_008DFC_SQ_V_CMP_NLE_F64 0x2C 1973 #define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D 1974 #define V_008DFC_SQ_V_CMP_NLT_F64 0x2E 1975 #define V_008DFC_SQ_V_CMP_TRU_F64 0x2F 1976 #define V_008DFC_SQ_V_CMPX_F_F64 0x30 1977 #define V_008DFC_SQ_V_CMPX_LT_F64 0x31 1978 #define V_008DFC_SQ_V_CMPX_EQ_F64 0x32 1979 #define V_008DFC_SQ_V_CMPX_LE_F64 0x33 1980 #define V_008DFC_SQ_V_CMPX_GT_F64 0x34 1981 #define V_008DFC_SQ_V_CMPX_LG_F64 0x35 1982 #define V_008DFC_SQ_V_CMPX_GE_F64 0x36 1983 #define V_008DFC_SQ_V_CMPX_O_F64 0x37 1984 #define V_008DFC_SQ_V_CMPX_U_F64 0x38 1985 #define V_008DFC_SQ_V_CMPX_NGE_F64 0x39 1986 #define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A 1987 #define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B 1988 #define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C 1989 #define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D 1990 #define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E 1991 #define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F 1992 #define V_008DFC_SQ_V_CMPS_F_F32 0x40 1993 #define V_008DFC_SQ_V_CMPS_LT_F32 0x41 1994 #define V_008DFC_SQ_V_CMPS_EQ_F32 0x42 1995 #define V_008DFC_SQ_V_CMPS_LE_F32 0x43 1996 #define V_008DFC_SQ_V_CMPS_GT_F32 0x44 1997 #define V_008DFC_SQ_V_CMPS_LG_F32 0x45 1998 #define V_008DFC_SQ_V_CMPS_GE_F32 0x46 1999 #define V_008DFC_SQ_V_CMPS_O_F32 0x47 2000 #define V_008DFC_SQ_V_CMPS_U_F32 0x48 2001 #define V_008DFC_SQ_V_CMPS_NGE_F32 0x49 2002 #define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A 2003 #define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B 2004 #define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C 2005 #define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D 2006 #define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E 2007 #define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F 2008 #define V_008DFC_SQ_V_CMPSX_F_F32 0x50 2009 #define V_008DFC_SQ_V_CMPSX_LT_F32 0x51 2010 #define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52 2011 #define V_008DFC_SQ_V_CMPSX_LE_F32 0x53 2012 #define V_008DFC_SQ_V_CMPSX_GT_F32 0x54 2013 #define V_008DFC_SQ_V_CMPSX_LG_F32 0x55 2014 #define V_008DFC_SQ_V_CMPSX_GE_F32 0x56 2015 #define V_008DFC_SQ_V_CMPSX_O_F32 0x57 2016 #define V_008DFC_SQ_V_CMPSX_U_F32 0x58 2017 #define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59 2018 #define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A 2019 #define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B 2020 #define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C 2021 #define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D 2022 #define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E 2023 #define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F 2024 #define V_008DFC_SQ_V_CMPS_F_F64 0x60 2025 #define V_008DFC_SQ_V_CMPS_LT_F64 0x61 2026 #define V_008DFC_SQ_V_CMPS_EQ_F64 0x62 2027 #define V_008DFC_SQ_V_CMPS_LE_F64 0x63 2028 #define V_008DFC_SQ_V_CMPS_GT_F64 0x64 2029 #define V_008DFC_SQ_V_CMPS_LG_F64 0x65 2030 #define V_008DFC_SQ_V_CMPS_GE_F64 0x66 2031 #define V_008DFC_SQ_V_CMPS_O_F64 0x67 2032 #define V_008DFC_SQ_V_CMPS_U_F64 0x68 2033 #define V_008DFC_SQ_V_CMPS_NGE_F64 0x69 2034 #define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A 2035 #define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B 2036 #define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C 2037 #define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D 2038 #define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E 2039 #define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F 2040 #define V_008DFC_SQ_V_CMPSX_F_F64 0x70 2041 #define V_008DFC_SQ_V_CMPSX_LT_F64 0x71 2042 #define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72 2043 #define V_008DFC_SQ_V_CMPSX_LE_F64 0x73 2044 #define V_008DFC_SQ_V_CMPSX_GT_F64 0x74 2045 #define V_008DFC_SQ_V_CMPSX_LG_F64 0x75 2046 #define V_008DFC_SQ_V_CMPSX_GE_F64 0x76 2047 #define V_008DFC_SQ_V_CMPSX_O_F64 0x77 2048 #define V_008DFC_SQ_V_CMPSX_U_F64 0x78 2049 #define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79 2050 #define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A 2051 #define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B 2052 #define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C 2053 #define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D 2054 #define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E 2055 #define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F 2056 #define V_008DFC_SQ_V_CMP_F_I32 0x80 2057 #define V_008DFC_SQ_V_CMP_LT_I32 0x81 2058 #define V_008DFC_SQ_V_CMP_EQ_I32 0x82 2059 #define V_008DFC_SQ_V_CMP_LE_I32 0x83 2060 #define V_008DFC_SQ_V_CMP_GT_I32 0x84 2061 #define V_008DFC_SQ_V_CMP_NE_I32 0x85 2062 #define V_008DFC_SQ_V_CMP_GE_I32 0x86 2063 #define V_008DFC_SQ_V_CMP_T_I32 0x87 2064 #define V_008DFC_SQ_V_CMP_CLASS_F32 0x88 2065 #define V_008DFC_SQ_V_CMPX_F_I32 0x90 2066 #define V_008DFC_SQ_V_CMPX_LT_I32 0x91 2067 #define V_008DFC_SQ_V_CMPX_EQ_I32 0x92 2068 #define V_008DFC_SQ_V_CMPX_LE_I32 0x93 2069 #define V_008DFC_SQ_V_CMPX_GT_I32 0x94 2070 #define V_008DFC_SQ_V_CMPX_NE_I32 0x95 2071 #define V_008DFC_SQ_V_CMPX_GE_I32 0x96 2072 #define V_008DFC_SQ_V_CMPX_T_I32 0x97 2073 #define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98 2074 #define V_008DFC_SQ_V_CMP_F_I64 0xA0 2075 #define V_008DFC_SQ_V_CMP_LT_I64 0xA1 2076 #define V_008DFC_SQ_V_CMP_EQ_I64 0xA2 2077 #define V_008DFC_SQ_V_CMP_LE_I64 0xA3 2078 #define V_008DFC_SQ_V_CMP_GT_I64 0xA4 2079 #define V_008DFC_SQ_V_CMP_NE_I64 0xA5 2080 #define V_008DFC_SQ_V_CMP_GE_I64 0xA6 2081 #define V_008DFC_SQ_V_CMP_T_I64 0xA7 2082 #define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8 2083 #define V_008DFC_SQ_V_CMPX_F_I64 0xB0 2084 #define V_008DFC_SQ_V_CMPX_LT_I64 0xB1 2085 #define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2 2086 #define V_008DFC_SQ_V_CMPX_LE_I64 0xB3 2087 #define V_008DFC_SQ_V_CMPX_GT_I64 0xB4 2088 #define V_008DFC_SQ_V_CMPX_NE_I64 0xB5 2089 #define V_008DFC_SQ_V_CMPX_GE_I64 0xB6 2090 #define V_008DFC_SQ_V_CMPX_T_I64 0xB7 2091 #define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8 2092 #define V_008DFC_SQ_V_CMP_F_U32 0xC0 2093 #define V_008DFC_SQ_V_CMP_LT_U32 0xC1 2094 #define V_008DFC_SQ_V_CMP_EQ_U32 0xC2 2095 #define V_008DFC_SQ_V_CMP_LE_U32 0xC3 2096 #define V_008DFC_SQ_V_CMP_GT_U32 0xC4 2097 #define V_008DFC_SQ_V_CMP_NE_U32 0xC5 2098 #define V_008DFC_SQ_V_CMP_GE_U32 0xC6 2099 #define V_008DFC_SQ_V_CMP_T_U32 0xC7 2100 #define V_008DFC_SQ_V_CMPX_F_U32 0xD0 2101 #define V_008DFC_SQ_V_CMPX_LT_U32 0xD1 2102 #define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2 2103 #define V_008DFC_SQ_V_CMPX_LE_U32 0xD3 2104 #define V_008DFC_SQ_V_CMPX_GT_U32 0xD4 2105 #define V_008DFC_SQ_V_CMPX_NE_U32 0xD5 2106 #define V_008DFC_SQ_V_CMPX_GE_U32 0xD6 2107 #define V_008DFC_SQ_V_CMPX_T_U32 0xD7 2108 #define V_008DFC_SQ_V_CMP_F_U64 0xE0 2109 #define V_008DFC_SQ_V_CMP_LT_U64 0xE1 2110 #define V_008DFC_SQ_V_CMP_EQ_U64 0xE2 2111 #define V_008DFC_SQ_V_CMP_LE_U64 0xE3 2112 #define V_008DFC_SQ_V_CMP_GT_U64 0xE4 2113 #define V_008DFC_SQ_V_CMP_NE_U64 0xE5 2114 #define V_008DFC_SQ_V_CMP_GE_U64 0xE6 2115 #define V_008DFC_SQ_V_CMP_T_U64 0xE7 2116 #define V_008DFC_SQ_V_CMPX_F_U64 0xF0 2117 #define V_008DFC_SQ_V_CMPX_LT_U64 0xF1 2118 #define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2 2119 #define V_008DFC_SQ_V_CMPX_LE_U64 0xF3 2120 #define V_008DFC_SQ_V_CMPX_GT_U64 0xF4 2121 #define V_008DFC_SQ_V_CMPX_NE_U64 0xF5 2122 #define V_008DFC_SQ_V_CMPX_GE_U64 0xF6 2123 #define V_008DFC_SQ_V_CMPX_T_U64 0xF7 2124 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) 2125 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) 2126 #define C_008DFC_ENCODING 0x01FFFFFF 2127 #define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E 2128 #define R_008DFC_SQ_SOP1 0x008DFC 2129 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) 2130 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) 2131 #define C_008DFC_SSRC0 0xFFFFFF00 2132 #define V_008DFC_SQ_SGPR 0x00 2133 #define V_008DFC_SQ_VCC_LO 0x6A 2134 #define V_008DFC_SQ_VCC_HI 0x6B 2135 #define V_008DFC_SQ_TBA_LO 0x6C 2136 #define V_008DFC_SQ_TBA_HI 0x6D 2137 #define V_008DFC_SQ_TMA_LO 0x6E 2138 #define V_008DFC_SQ_TMA_HI 0x6F 2139 #define V_008DFC_SQ_TTMP0 0x70 2140 #define V_008DFC_SQ_TTMP1 0x71 2141 #define V_008DFC_SQ_TTMP2 0x72 2142 #define V_008DFC_SQ_TTMP3 0x73 2143 #define V_008DFC_SQ_TTMP4 0x74 2144 #define V_008DFC_SQ_TTMP5 0x75 2145 #define V_008DFC_SQ_TTMP6 0x76 2146 #define V_008DFC_SQ_TTMP7 0x77 2147 #define V_008DFC_SQ_TTMP8 0x78 2148 #define V_008DFC_SQ_TTMP9 0x79 2149 #define V_008DFC_SQ_TTMP10 0x7A 2150 #define V_008DFC_SQ_TTMP11 0x7B 2151 #define V_008DFC_SQ_M0 0x7C 2152 #define V_008DFC_SQ_EXEC_LO 0x7E 2153 #define V_008DFC_SQ_EXEC_HI 0x7F 2154 #define V_008DFC_SQ_SRC_0 0x80 2155 #define V_008DFC_SQ_SRC_1_INT 0x81 2156 #define V_008DFC_SQ_SRC_2_INT 0x82 2157 #define V_008DFC_SQ_SRC_3_INT 0x83 2158 #define V_008DFC_SQ_SRC_4_INT 0x84 2159 #define V_008DFC_SQ_SRC_5_INT 0x85 2160 #define V_008DFC_SQ_SRC_6_INT 0x86 2161 #define V_008DFC_SQ_SRC_7_INT 0x87 2162 #define V_008DFC_SQ_SRC_8_INT 0x88 2163 #define V_008DFC_SQ_SRC_9_INT 0x89 2164 #define V_008DFC_SQ_SRC_10_INT 0x8A 2165 #define V_008DFC_SQ_SRC_11_INT 0x8B 2166 #define V_008DFC_SQ_SRC_12_INT 0x8C 2167 #define V_008DFC_SQ_SRC_13_INT 0x8D 2168 #define V_008DFC_SQ_SRC_14_INT 0x8E 2169 #define V_008DFC_SQ_SRC_15_INT 0x8F 2170 #define V_008DFC_SQ_SRC_16_INT 0x90 2171 #define V_008DFC_SQ_SRC_17_INT 0x91 2172 #define V_008DFC_SQ_SRC_18_INT 0x92 2173 #define V_008DFC_SQ_SRC_19_INT 0x93 2174 #define V_008DFC_SQ_SRC_20_INT 0x94 2175 #define V_008DFC_SQ_SRC_21_INT 0x95 2176 #define V_008DFC_SQ_SRC_22_INT 0x96 2177 #define V_008DFC_SQ_SRC_23_INT 0x97 2178 #define V_008DFC_SQ_SRC_24_INT 0x98 2179 #define V_008DFC_SQ_SRC_25_INT 0x99 2180 #define V_008DFC_SQ_SRC_26_INT 0x9A 2181 #define V_008DFC_SQ_SRC_27_INT 0x9B 2182 #define V_008DFC_SQ_SRC_28_INT 0x9C 2183 #define V_008DFC_SQ_SRC_29_INT 0x9D 2184 #define V_008DFC_SQ_SRC_30_INT 0x9E 2185 #define V_008DFC_SQ_SRC_31_INT 0x9F 2186 #define V_008DFC_SQ_SRC_32_INT 0xA0 2187 #define V_008DFC_SQ_SRC_33_INT 0xA1 2188 #define V_008DFC_SQ_SRC_34_INT 0xA2 2189 #define V_008DFC_SQ_SRC_35_INT 0xA3 2190 #define V_008DFC_SQ_SRC_36_INT 0xA4 2191 #define V_008DFC_SQ_SRC_37_INT 0xA5 2192 #define V_008DFC_SQ_SRC_38_INT 0xA6 2193 #define V_008DFC_SQ_SRC_39_INT 0xA7 2194 #define V_008DFC_SQ_SRC_40_INT 0xA8 2195 #define V_008DFC_SQ_SRC_41_INT 0xA9 2196 #define V_008DFC_SQ_SRC_42_INT 0xAA 2197 #define V_008DFC_SQ_SRC_43_INT 0xAB 2198 #define V_008DFC_SQ_SRC_44_INT 0xAC 2199 #define V_008DFC_SQ_SRC_45_INT 0xAD 2200 #define V_008DFC_SQ_SRC_46_INT 0xAE 2201 #define V_008DFC_SQ_SRC_47_INT 0xAF 2202 #define V_008DFC_SQ_SRC_48_INT 0xB0 2203 #define V_008DFC_SQ_SRC_49_INT 0xB1 2204 #define V_008DFC_SQ_SRC_50_INT 0xB2 2205 #define V_008DFC_SQ_SRC_51_INT 0xB3 2206 #define V_008DFC_SQ_SRC_52_INT 0xB4 2207 #define V_008DFC_SQ_SRC_53_INT 0xB5 2208 #define V_008DFC_SQ_SRC_54_INT 0xB6 2209 #define V_008DFC_SQ_SRC_55_INT 0xB7 2210 #define V_008DFC_SQ_SRC_56_INT 0xB8 2211 #define V_008DFC_SQ_SRC_57_INT 0xB9 2212 #define V_008DFC_SQ_SRC_58_INT 0xBA 2213 #define V_008DFC_SQ_SRC_59_INT 0xBB 2214 #define V_008DFC_SQ_SRC_60_INT 0xBC 2215 #define V_008DFC_SQ_SRC_61_INT 0xBD 2216 #define V_008DFC_SQ_SRC_62_INT 0xBE 2217 #define V_008DFC_SQ_SRC_63_INT 0xBF 2218 #define V_008DFC_SQ_SRC_64_INT 0xC0 2219 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 2220 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 2221 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 2222 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 2223 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 2224 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 2225 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 2226 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 2227 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 2228 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 2229 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 2230 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 2231 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 2232 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 2233 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 2234 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 2235 #define V_008DFC_SQ_SRC_0_5 0xF0 2236 #define V_008DFC_SQ_SRC_M_0_5 0xF1 2237 #define V_008DFC_SQ_SRC_1 0xF2 2238 #define V_008DFC_SQ_SRC_M_1 0xF3 2239 #define V_008DFC_SQ_SRC_2 0xF4 2240 #define V_008DFC_SQ_SRC_M_2 0xF5 2241 #define V_008DFC_SQ_SRC_4 0xF6 2242 #define V_008DFC_SQ_SRC_M_4 0xF7 2243 #define V_008DFC_SQ_SRC_VCCZ 0xFB 2244 #define V_008DFC_SQ_SRC_EXECZ 0xFC 2245 #define V_008DFC_SQ_SRC_SCC 0xFD 2246 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 2247 #define S_008DFC_OP(x) (((x) & 0xFF) << 8) 2248 #define G_008DFC_OP(x) (((x) >> 8) & 0xFF) 2249 #define C_008DFC_OP 0xFFFF00FF 2250 #define V_008DFC_SQ_S_MOV_B32 0x03 2251 #define V_008DFC_SQ_S_MOV_B64 0x04 2252 #define V_008DFC_SQ_S_CMOV_B32 0x05 2253 #define V_008DFC_SQ_S_CMOV_B64 0x06 2254 #define V_008DFC_SQ_S_NOT_B32 0x07 2255 #define V_008DFC_SQ_S_NOT_B64 0x08 2256 #define V_008DFC_SQ_S_WQM_B32 0x09 2257 #define V_008DFC_SQ_S_WQM_B64 0x0A 2258 #define V_008DFC_SQ_S_BREV_B32 0x0B 2259 #define V_008DFC_SQ_S_BREV_B64 0x0C 2260 #define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D 2261 #define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E 2262 #define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F 2263 #define V_008DFC_SQ_S_BCNT1_I32_B64 0x10 2264 #define V_008DFC_SQ_S_FF0_I32_B32 0x11 2265 #define V_008DFC_SQ_S_FF0_I32_B64 0x12 2266 #define V_008DFC_SQ_S_FF1_I32_B32 0x13 2267 #define V_008DFC_SQ_S_FF1_I32_B64 0x14 2268 #define V_008DFC_SQ_S_FLBIT_I32_B32 0x15 2269 #define V_008DFC_SQ_S_FLBIT_I32_B64 0x16 2270 #define V_008DFC_SQ_S_FLBIT_I32 0x17 2271 #define V_008DFC_SQ_S_FLBIT_I32_I64 0x18 2272 #define V_008DFC_SQ_S_SEXT_I32_I8 0x19 2273 #define V_008DFC_SQ_S_SEXT_I32_I16 0x1A 2274 #define V_008DFC_SQ_S_BITSET0_B32 0x1B 2275 #define V_008DFC_SQ_S_BITSET0_B64 0x1C 2276 #define V_008DFC_SQ_S_BITSET1_B32 0x1D 2277 #define V_008DFC_SQ_S_BITSET1_B64 0x1E 2278 #define V_008DFC_SQ_S_GETPC_B64 0x1F 2279 #define V_008DFC_SQ_S_SETPC_B64 0x20 2280 #define V_008DFC_SQ_S_SWAPPC_B64 0x21 2281 #define V_008DFC_SQ_S_RFE_B64 0x22 2282 #define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24 2283 #define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25 2284 #define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26 2285 #define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27 2286 #define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28 2287 #define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29 2288 #define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A 2289 #define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B 2290 #define V_008DFC_SQ_S_QUADMASK_B32 0x2C 2291 #define V_008DFC_SQ_S_QUADMASK_B64 0x2D 2292 #define V_008DFC_SQ_S_MOVRELS_B32 0x2E 2293 #define V_008DFC_SQ_S_MOVRELS_B64 0x2F 2294 #define V_008DFC_SQ_S_MOVRELD_B32 0x30 2295 #define V_008DFC_SQ_S_MOVRELD_B64 0x31 2296 #define V_008DFC_SQ_S_CBRANCH_JOIN 0x32 2297 #define V_008DFC_SQ_S_MOV_REGRD_B32 0x33 2298 #define V_008DFC_SQ_S_ABS_I32 0x34 2299 #define V_008DFC_SQ_S_MOV_FED_B32 0x35 2300 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16) 2301 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) 2302 #define C_008DFC_SDST 0xFF80FFFF 2303 #define V_008DFC_SQ_SGPR 0x00 2304 #define V_008DFC_SQ_VCC_LO 0x6A 2305 #define V_008DFC_SQ_VCC_HI 0x6B 2306 #define V_008DFC_SQ_TBA_LO 0x6C 2307 #define V_008DFC_SQ_TBA_HI 0x6D 2308 #define V_008DFC_SQ_TMA_LO 0x6E 2309 #define V_008DFC_SQ_TMA_HI 0x6F 2310 #define V_008DFC_SQ_TTMP0 0x70 2311 #define V_008DFC_SQ_TTMP1 0x71 2312 #define V_008DFC_SQ_TTMP2 0x72 2313 #define V_008DFC_SQ_TTMP3 0x73 2314 #define V_008DFC_SQ_TTMP4 0x74 2315 #define V_008DFC_SQ_TTMP5 0x75 2316 #define V_008DFC_SQ_TTMP6 0x76 2317 #define V_008DFC_SQ_TTMP7 0x77 2318 #define V_008DFC_SQ_TTMP8 0x78 2319 #define V_008DFC_SQ_TTMP9 0x79 2320 #define V_008DFC_SQ_TTMP10 0x7A 2321 #define V_008DFC_SQ_TTMP11 0x7B 2322 #define V_008DFC_SQ_M0 0x7C 2323 #define V_008DFC_SQ_EXEC_LO 0x7E 2324 #define V_008DFC_SQ_EXEC_HI 0x7F 2325 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) 2326 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) 2327 #define C_008DFC_ENCODING 0x007FFFFF 2328 #define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D 2329 #define R_008DFC_SQ_MTBUF_1 0x008DFC 2330 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) 2331 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) 2332 #define C_008DFC_VADDR 0xFFFFFF00 2333 #define V_008DFC_SQ_VGPR 0x00 2334 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) 2335 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) 2336 #define C_008DFC_VDATA 0xFFFF00FF 2337 #define V_008DFC_SQ_VGPR 0x00 2338 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) 2339 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) 2340 #define C_008DFC_SRSRC 0xFFE0FFFF 2341 #define S_008DFC_SLC(x) (((x) & 0x1) << 22) 2342 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1) 2343 #define C_008DFC_SLC 0xFFBFFFFF 2344 #define S_008DFC_TFE(x) (((x) & 0x1) << 23) 2345 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1) 2346 #define C_008DFC_TFE 0xFF7FFFFF 2347 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) 2348 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) 2349 #define C_008DFC_SOFFSET 0x00FFFFFF 2350 #define V_008DFC_SQ_SGPR 0x00 2351 #define V_008DFC_SQ_VCC_LO 0x6A 2352 #define V_008DFC_SQ_VCC_HI 0x6B 2353 #define V_008DFC_SQ_TBA_LO 0x6C 2354 #define V_008DFC_SQ_TBA_HI 0x6D 2355 #define V_008DFC_SQ_TMA_LO 0x6E 2356 #define V_008DFC_SQ_TMA_HI 0x6F 2357 #define V_008DFC_SQ_TTMP0 0x70 2358 #define V_008DFC_SQ_TTMP1 0x71 2359 #define V_008DFC_SQ_TTMP2 0x72 2360 #define V_008DFC_SQ_TTMP3 0x73 2361 #define V_008DFC_SQ_TTMP4 0x74 2362 #define V_008DFC_SQ_TTMP5 0x75 2363 #define V_008DFC_SQ_TTMP6 0x76 2364 #define V_008DFC_SQ_TTMP7 0x77 2365 #define V_008DFC_SQ_TTMP8 0x78 2366 #define V_008DFC_SQ_TTMP9 0x79 2367 #define V_008DFC_SQ_TTMP10 0x7A 2368 #define V_008DFC_SQ_TTMP11 0x7B 2369 #define V_008DFC_SQ_M0 0x7C 2370 #define V_008DFC_SQ_EXEC_LO 0x7E 2371 #define V_008DFC_SQ_EXEC_HI 0x7F 2372 #define V_008DFC_SQ_SRC_0 0x80 2373 #define V_008DFC_SQ_SRC_1_INT 0x81 2374 #define V_008DFC_SQ_SRC_2_INT 0x82 2375 #define V_008DFC_SQ_SRC_3_INT 0x83 2376 #define V_008DFC_SQ_SRC_4_INT 0x84 2377 #define V_008DFC_SQ_SRC_5_INT 0x85 2378 #define V_008DFC_SQ_SRC_6_INT 0x86 2379 #define V_008DFC_SQ_SRC_7_INT 0x87 2380 #define V_008DFC_SQ_SRC_8_INT 0x88 2381 #define V_008DFC_SQ_SRC_9_INT 0x89 2382 #define V_008DFC_SQ_SRC_10_INT 0x8A 2383 #define V_008DFC_SQ_SRC_11_INT 0x8B 2384 #define V_008DFC_SQ_SRC_12_INT 0x8C 2385 #define V_008DFC_SQ_SRC_13_INT 0x8D 2386 #define V_008DFC_SQ_SRC_14_INT 0x8E 2387 #define V_008DFC_SQ_SRC_15_INT 0x8F 2388 #define V_008DFC_SQ_SRC_16_INT 0x90 2389 #define V_008DFC_SQ_SRC_17_INT 0x91 2390 #define V_008DFC_SQ_SRC_18_INT 0x92 2391 #define V_008DFC_SQ_SRC_19_INT 0x93 2392 #define V_008DFC_SQ_SRC_20_INT 0x94 2393 #define V_008DFC_SQ_SRC_21_INT 0x95 2394 #define V_008DFC_SQ_SRC_22_INT 0x96 2395 #define V_008DFC_SQ_SRC_23_INT 0x97 2396 #define V_008DFC_SQ_SRC_24_INT 0x98 2397 #define V_008DFC_SQ_SRC_25_INT 0x99 2398 #define V_008DFC_SQ_SRC_26_INT 0x9A 2399 #define V_008DFC_SQ_SRC_27_INT 0x9B 2400 #define V_008DFC_SQ_SRC_28_INT 0x9C 2401 #define V_008DFC_SQ_SRC_29_INT 0x9D 2402 #define V_008DFC_SQ_SRC_30_INT 0x9E 2403 #define V_008DFC_SQ_SRC_31_INT 0x9F 2404 #define V_008DFC_SQ_SRC_32_INT 0xA0 2405 #define V_008DFC_SQ_SRC_33_INT 0xA1 2406 #define V_008DFC_SQ_SRC_34_INT 0xA2 2407 #define V_008DFC_SQ_SRC_35_INT 0xA3 2408 #define V_008DFC_SQ_SRC_36_INT 0xA4 2409 #define V_008DFC_SQ_SRC_37_INT 0xA5 2410 #define V_008DFC_SQ_SRC_38_INT 0xA6 2411 #define V_008DFC_SQ_SRC_39_INT 0xA7 2412 #define V_008DFC_SQ_SRC_40_INT 0xA8 2413 #define V_008DFC_SQ_SRC_41_INT 0xA9 2414 #define V_008DFC_SQ_SRC_42_INT 0xAA 2415 #define V_008DFC_SQ_SRC_43_INT 0xAB 2416 #define V_008DFC_SQ_SRC_44_INT 0xAC 2417 #define V_008DFC_SQ_SRC_45_INT 0xAD 2418 #define V_008DFC_SQ_SRC_46_INT 0xAE 2419 #define V_008DFC_SQ_SRC_47_INT 0xAF 2420 #define V_008DFC_SQ_SRC_48_INT 0xB0 2421 #define V_008DFC_SQ_SRC_49_INT 0xB1 2422 #define V_008DFC_SQ_SRC_50_INT 0xB2 2423 #define V_008DFC_SQ_SRC_51_INT 0xB3 2424 #define V_008DFC_SQ_SRC_52_INT 0xB4 2425 #define V_008DFC_SQ_SRC_53_INT 0xB5 2426 #define V_008DFC_SQ_SRC_54_INT 0xB6 2427 #define V_008DFC_SQ_SRC_55_INT 0xB7 2428 #define V_008DFC_SQ_SRC_56_INT 0xB8 2429 #define V_008DFC_SQ_SRC_57_INT 0xB9 2430 #define V_008DFC_SQ_SRC_58_INT 0xBA 2431 #define V_008DFC_SQ_SRC_59_INT 0xBB 2432 #define V_008DFC_SQ_SRC_60_INT 0xBC 2433 #define V_008DFC_SQ_SRC_61_INT 0xBD 2434 #define V_008DFC_SQ_SRC_62_INT 0xBE 2435 #define V_008DFC_SQ_SRC_63_INT 0xBF 2436 #define V_008DFC_SQ_SRC_64_INT 0xC0 2437 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 2438 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 2439 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 2440 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 2441 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 2442 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 2443 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 2444 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 2445 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 2446 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 2447 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 2448 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 2449 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 2450 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 2451 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 2452 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 2453 #define V_008DFC_SQ_SRC_0_5 0xF0 2454 #define V_008DFC_SQ_SRC_M_0_5 0xF1 2455 #define V_008DFC_SQ_SRC_1 0xF2 2456 #define V_008DFC_SQ_SRC_M_1 0xF3 2457 #define V_008DFC_SQ_SRC_2 0xF4 2458 #define V_008DFC_SQ_SRC_M_2 0xF5 2459 #define V_008DFC_SQ_SRC_4 0xF6 2460 #define V_008DFC_SQ_SRC_M_4 0xF7 2461 #define V_008DFC_SQ_SRC_VCCZ 0xFB 2462 #define V_008DFC_SQ_SRC_EXECZ 0xFC 2463 #define V_008DFC_SQ_SRC_SCC 0xFD 2464 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 2465 #define R_008DFC_SQ_SOP2 0x008DFC 2466 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) 2467 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) 2468 #define C_008DFC_SSRC0 0xFFFFFF00 2469 #define V_008DFC_SQ_SGPR 0x00 2470 #define V_008DFC_SQ_VCC_LO 0x6A 2471 #define V_008DFC_SQ_VCC_HI 0x6B 2472 #define V_008DFC_SQ_TBA_LO 0x6C 2473 #define V_008DFC_SQ_TBA_HI 0x6D 2474 #define V_008DFC_SQ_TMA_LO 0x6E 2475 #define V_008DFC_SQ_TMA_HI 0x6F 2476 #define V_008DFC_SQ_TTMP0 0x70 2477 #define V_008DFC_SQ_TTMP1 0x71 2478 #define V_008DFC_SQ_TTMP2 0x72 2479 #define V_008DFC_SQ_TTMP3 0x73 2480 #define V_008DFC_SQ_TTMP4 0x74 2481 #define V_008DFC_SQ_TTMP5 0x75 2482 #define V_008DFC_SQ_TTMP6 0x76 2483 #define V_008DFC_SQ_TTMP7 0x77 2484 #define V_008DFC_SQ_TTMP8 0x78 2485 #define V_008DFC_SQ_TTMP9 0x79 2486 #define V_008DFC_SQ_TTMP10 0x7A 2487 #define V_008DFC_SQ_TTMP11 0x7B 2488 #define V_008DFC_SQ_M0 0x7C 2489 #define V_008DFC_SQ_EXEC_LO 0x7E 2490 #define V_008DFC_SQ_EXEC_HI 0x7F 2491 #define V_008DFC_SQ_SRC_0 0x80 2492 #define V_008DFC_SQ_SRC_1_INT 0x81 2493 #define V_008DFC_SQ_SRC_2_INT 0x82 2494 #define V_008DFC_SQ_SRC_3_INT 0x83 2495 #define V_008DFC_SQ_SRC_4_INT 0x84 2496 #define V_008DFC_SQ_SRC_5_INT 0x85 2497 #define V_008DFC_SQ_SRC_6_INT 0x86 2498 #define V_008DFC_SQ_SRC_7_INT 0x87 2499 #define V_008DFC_SQ_SRC_8_INT 0x88 2500 #define V_008DFC_SQ_SRC_9_INT 0x89 2501 #define V_008DFC_SQ_SRC_10_INT 0x8A 2502 #define V_008DFC_SQ_SRC_11_INT 0x8B 2503 #define V_008DFC_SQ_SRC_12_INT 0x8C 2504 #define V_008DFC_SQ_SRC_13_INT 0x8D 2505 #define V_008DFC_SQ_SRC_14_INT 0x8E 2506 #define V_008DFC_SQ_SRC_15_INT 0x8F 2507 #define V_008DFC_SQ_SRC_16_INT 0x90 2508 #define V_008DFC_SQ_SRC_17_INT 0x91 2509 #define V_008DFC_SQ_SRC_18_INT 0x92 2510 #define V_008DFC_SQ_SRC_19_INT 0x93 2511 #define V_008DFC_SQ_SRC_20_INT 0x94 2512 #define V_008DFC_SQ_SRC_21_INT 0x95 2513 #define V_008DFC_SQ_SRC_22_INT 0x96 2514 #define V_008DFC_SQ_SRC_23_INT 0x97 2515 #define V_008DFC_SQ_SRC_24_INT 0x98 2516 #define V_008DFC_SQ_SRC_25_INT 0x99 2517 #define V_008DFC_SQ_SRC_26_INT 0x9A 2518 #define V_008DFC_SQ_SRC_27_INT 0x9B 2519 #define V_008DFC_SQ_SRC_28_INT 0x9C 2520 #define V_008DFC_SQ_SRC_29_INT 0x9D 2521 #define V_008DFC_SQ_SRC_30_INT 0x9E 2522 #define V_008DFC_SQ_SRC_31_INT 0x9F 2523 #define V_008DFC_SQ_SRC_32_INT 0xA0 2524 #define V_008DFC_SQ_SRC_33_INT 0xA1 2525 #define V_008DFC_SQ_SRC_34_INT 0xA2 2526 #define V_008DFC_SQ_SRC_35_INT 0xA3 2527 #define V_008DFC_SQ_SRC_36_INT 0xA4 2528 #define V_008DFC_SQ_SRC_37_INT 0xA5 2529 #define V_008DFC_SQ_SRC_38_INT 0xA6 2530 #define V_008DFC_SQ_SRC_39_INT 0xA7 2531 #define V_008DFC_SQ_SRC_40_INT 0xA8 2532 #define V_008DFC_SQ_SRC_41_INT 0xA9 2533 #define V_008DFC_SQ_SRC_42_INT 0xAA 2534 #define V_008DFC_SQ_SRC_43_INT 0xAB 2535 #define V_008DFC_SQ_SRC_44_INT 0xAC 2536 #define V_008DFC_SQ_SRC_45_INT 0xAD 2537 #define V_008DFC_SQ_SRC_46_INT 0xAE 2538 #define V_008DFC_SQ_SRC_47_INT 0xAF 2539 #define V_008DFC_SQ_SRC_48_INT 0xB0 2540 #define V_008DFC_SQ_SRC_49_INT 0xB1 2541 #define V_008DFC_SQ_SRC_50_INT 0xB2 2542 #define V_008DFC_SQ_SRC_51_INT 0xB3 2543 #define V_008DFC_SQ_SRC_52_INT 0xB4 2544 #define V_008DFC_SQ_SRC_53_INT 0xB5 2545 #define V_008DFC_SQ_SRC_54_INT 0xB6 2546 #define V_008DFC_SQ_SRC_55_INT 0xB7 2547 #define V_008DFC_SQ_SRC_56_INT 0xB8 2548 #define V_008DFC_SQ_SRC_57_INT 0xB9 2549 #define V_008DFC_SQ_SRC_58_INT 0xBA 2550 #define V_008DFC_SQ_SRC_59_INT 0xBB 2551 #define V_008DFC_SQ_SRC_60_INT 0xBC 2552 #define V_008DFC_SQ_SRC_61_INT 0xBD 2553 #define V_008DFC_SQ_SRC_62_INT 0xBE 2554 #define V_008DFC_SQ_SRC_63_INT 0xBF 2555 #define V_008DFC_SQ_SRC_64_INT 0xC0 2556 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 2557 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 2558 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 2559 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 2560 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 2561 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 2562 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 2563 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 2564 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 2565 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 2566 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 2567 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 2568 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 2569 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 2570 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 2571 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 2572 #define V_008DFC_SQ_SRC_0_5 0xF0 2573 #define V_008DFC_SQ_SRC_M_0_5 0xF1 2574 #define V_008DFC_SQ_SRC_1 0xF2 2575 #define V_008DFC_SQ_SRC_M_1 0xF3 2576 #define V_008DFC_SQ_SRC_2 0xF4 2577 #define V_008DFC_SQ_SRC_M_2 0xF5 2578 #define V_008DFC_SQ_SRC_4 0xF6 2579 #define V_008DFC_SQ_SRC_M_4 0xF7 2580 #define V_008DFC_SQ_SRC_VCCZ 0xFB 2581 #define V_008DFC_SQ_SRC_EXECZ 0xFC 2582 #define V_008DFC_SQ_SRC_SCC 0xFD 2583 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 2584 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) 2585 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) 2586 #define C_008DFC_SSRC1 0xFFFF00FF 2587 #define V_008DFC_SQ_SGPR 0x00 2588 #define V_008DFC_SQ_VCC_LO 0x6A 2589 #define V_008DFC_SQ_VCC_HI 0x6B 2590 #define V_008DFC_SQ_TBA_LO 0x6C 2591 #define V_008DFC_SQ_TBA_HI 0x6D 2592 #define V_008DFC_SQ_TMA_LO 0x6E 2593 #define V_008DFC_SQ_TMA_HI 0x6F 2594 #define V_008DFC_SQ_TTMP0 0x70 2595 #define V_008DFC_SQ_TTMP1 0x71 2596 #define V_008DFC_SQ_TTMP2 0x72 2597 #define V_008DFC_SQ_TTMP3 0x73 2598 #define V_008DFC_SQ_TTMP4 0x74 2599 #define V_008DFC_SQ_TTMP5 0x75 2600 #define V_008DFC_SQ_TTMP6 0x76 2601 #define V_008DFC_SQ_TTMP7 0x77 2602 #define V_008DFC_SQ_TTMP8 0x78 2603 #define V_008DFC_SQ_TTMP9 0x79 2604 #define V_008DFC_SQ_TTMP10 0x7A 2605 #define V_008DFC_SQ_TTMP11 0x7B 2606 #define V_008DFC_SQ_M0 0x7C 2607 #define V_008DFC_SQ_EXEC_LO 0x7E 2608 #define V_008DFC_SQ_EXEC_HI 0x7F 2609 #define V_008DFC_SQ_SRC_0 0x80 2610 #define V_008DFC_SQ_SRC_1_INT 0x81 2611 #define V_008DFC_SQ_SRC_2_INT 0x82 2612 #define V_008DFC_SQ_SRC_3_INT 0x83 2613 #define V_008DFC_SQ_SRC_4_INT 0x84 2614 #define V_008DFC_SQ_SRC_5_INT 0x85 2615 #define V_008DFC_SQ_SRC_6_INT 0x86 2616 #define V_008DFC_SQ_SRC_7_INT 0x87 2617 #define V_008DFC_SQ_SRC_8_INT 0x88 2618 #define V_008DFC_SQ_SRC_9_INT 0x89 2619 #define V_008DFC_SQ_SRC_10_INT 0x8A 2620 #define V_008DFC_SQ_SRC_11_INT 0x8B 2621 #define V_008DFC_SQ_SRC_12_INT 0x8C 2622 #define V_008DFC_SQ_SRC_13_INT 0x8D 2623 #define V_008DFC_SQ_SRC_14_INT 0x8E 2624 #define V_008DFC_SQ_SRC_15_INT 0x8F 2625 #define V_008DFC_SQ_SRC_16_INT 0x90 2626 #define V_008DFC_SQ_SRC_17_INT 0x91 2627 #define V_008DFC_SQ_SRC_18_INT 0x92 2628 #define V_008DFC_SQ_SRC_19_INT 0x93 2629 #define V_008DFC_SQ_SRC_20_INT 0x94 2630 #define V_008DFC_SQ_SRC_21_INT 0x95 2631 #define V_008DFC_SQ_SRC_22_INT 0x96 2632 #define V_008DFC_SQ_SRC_23_INT 0x97 2633 #define V_008DFC_SQ_SRC_24_INT 0x98 2634 #define V_008DFC_SQ_SRC_25_INT 0x99 2635 #define V_008DFC_SQ_SRC_26_INT 0x9A 2636 #define V_008DFC_SQ_SRC_27_INT 0x9B 2637 #define V_008DFC_SQ_SRC_28_INT 0x9C 2638 #define V_008DFC_SQ_SRC_29_INT 0x9D 2639 #define V_008DFC_SQ_SRC_30_INT 0x9E 2640 #define V_008DFC_SQ_SRC_31_INT 0x9F 2641 #define V_008DFC_SQ_SRC_32_INT 0xA0 2642 #define V_008DFC_SQ_SRC_33_INT 0xA1 2643 #define V_008DFC_SQ_SRC_34_INT 0xA2 2644 #define V_008DFC_SQ_SRC_35_INT 0xA3 2645 #define V_008DFC_SQ_SRC_36_INT 0xA4 2646 #define V_008DFC_SQ_SRC_37_INT 0xA5 2647 #define V_008DFC_SQ_SRC_38_INT 0xA6 2648 #define V_008DFC_SQ_SRC_39_INT 0xA7 2649 #define V_008DFC_SQ_SRC_40_INT 0xA8 2650 #define V_008DFC_SQ_SRC_41_INT 0xA9 2651 #define V_008DFC_SQ_SRC_42_INT 0xAA 2652 #define V_008DFC_SQ_SRC_43_INT 0xAB 2653 #define V_008DFC_SQ_SRC_44_INT 0xAC 2654 #define V_008DFC_SQ_SRC_45_INT 0xAD 2655 #define V_008DFC_SQ_SRC_46_INT 0xAE 2656 #define V_008DFC_SQ_SRC_47_INT 0xAF 2657 #define V_008DFC_SQ_SRC_48_INT 0xB0 2658 #define V_008DFC_SQ_SRC_49_INT 0xB1 2659 #define V_008DFC_SQ_SRC_50_INT 0xB2 2660 #define V_008DFC_SQ_SRC_51_INT 0xB3 2661 #define V_008DFC_SQ_SRC_52_INT 0xB4 2662 #define V_008DFC_SQ_SRC_53_INT 0xB5 2663 #define V_008DFC_SQ_SRC_54_INT 0xB6 2664 #define V_008DFC_SQ_SRC_55_INT 0xB7 2665 #define V_008DFC_SQ_SRC_56_INT 0xB8 2666 #define V_008DFC_SQ_SRC_57_INT 0xB9 2667 #define V_008DFC_SQ_SRC_58_INT 0xBA 2668 #define V_008DFC_SQ_SRC_59_INT 0xBB 2669 #define V_008DFC_SQ_SRC_60_INT 0xBC 2670 #define V_008DFC_SQ_SRC_61_INT 0xBD 2671 #define V_008DFC_SQ_SRC_62_INT 0xBE 2672 #define V_008DFC_SQ_SRC_63_INT 0xBF 2673 #define V_008DFC_SQ_SRC_64_INT 0xC0 2674 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 2675 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 2676 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 2677 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 2678 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 2679 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 2680 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 2681 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 2682 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 2683 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 2684 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 2685 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 2686 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 2687 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 2688 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 2689 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 2690 #define V_008DFC_SQ_SRC_0_5 0xF0 2691 #define V_008DFC_SQ_SRC_M_0_5 0xF1 2692 #define V_008DFC_SQ_SRC_1 0xF2 2693 #define V_008DFC_SQ_SRC_M_1 0xF3 2694 #define V_008DFC_SQ_SRC_2 0xF4 2695 #define V_008DFC_SQ_SRC_M_2 0xF5 2696 #define V_008DFC_SQ_SRC_4 0xF6 2697 #define V_008DFC_SQ_SRC_M_4 0xF7 2698 #define V_008DFC_SQ_SRC_VCCZ 0xFB 2699 #define V_008DFC_SQ_SRC_EXECZ 0xFC 2700 #define V_008DFC_SQ_SRC_SCC 0xFD 2701 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 2702 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16) 2703 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) 2704 #define C_008DFC_SDST 0xFF80FFFF 2705 #define V_008DFC_SQ_SGPR 0x00 2706 #define V_008DFC_SQ_VCC_LO 0x6A 2707 #define V_008DFC_SQ_VCC_HI 0x6B 2708 #define V_008DFC_SQ_TBA_LO 0x6C 2709 #define V_008DFC_SQ_TBA_HI 0x6D 2710 #define V_008DFC_SQ_TMA_LO 0x6E 2711 #define V_008DFC_SQ_TMA_HI 0x6F 2712 #define V_008DFC_SQ_TTMP0 0x70 2713 #define V_008DFC_SQ_TTMP1 0x71 2714 #define V_008DFC_SQ_TTMP2 0x72 2715 #define V_008DFC_SQ_TTMP3 0x73 2716 #define V_008DFC_SQ_TTMP4 0x74 2717 #define V_008DFC_SQ_TTMP5 0x75 2718 #define V_008DFC_SQ_TTMP6 0x76 2719 #define V_008DFC_SQ_TTMP7 0x77 2720 #define V_008DFC_SQ_TTMP8 0x78 2721 #define V_008DFC_SQ_TTMP9 0x79 2722 #define V_008DFC_SQ_TTMP10 0x7A 2723 #define V_008DFC_SQ_TTMP11 0x7B 2724 #define V_008DFC_SQ_M0 0x7C 2725 #define V_008DFC_SQ_EXEC_LO 0x7E 2726 #define V_008DFC_SQ_EXEC_HI 0x7F 2727 #define S_008DFC_OP(x) (((x) & 0x7F) << 23) 2728 #define G_008DFC_OP(x) (((x) >> 23) & 0x7F) 2729 #define C_008DFC_OP 0xC07FFFFF 2730 #define V_008DFC_SQ_S_ADD_U32 0x00 2731 #define V_008DFC_SQ_S_SUB_U32 0x01 2732 #define V_008DFC_SQ_S_ADD_I32 0x02 2733 #define V_008DFC_SQ_S_SUB_I32 0x03 2734 #define V_008DFC_SQ_S_ADDC_U32 0x04 2735 #define V_008DFC_SQ_S_SUBB_U32 0x05 2736 #define V_008DFC_SQ_S_MIN_I32 0x06 2737 #define V_008DFC_SQ_S_MIN_U32 0x07 2738 #define V_008DFC_SQ_S_MAX_I32 0x08 2739 #define V_008DFC_SQ_S_MAX_U32 0x09 2740 #define V_008DFC_SQ_S_CSELECT_B32 0x0A 2741 #define V_008DFC_SQ_S_CSELECT_B64 0x0B 2742 #define V_008DFC_SQ_S_AND_B32 0x0E 2743 #define V_008DFC_SQ_S_AND_B64 0x0F 2744 #define V_008DFC_SQ_S_OR_B32 0x10 2745 #define V_008DFC_SQ_S_OR_B64 0x11 2746 #define V_008DFC_SQ_S_XOR_B32 0x12 2747 #define V_008DFC_SQ_S_XOR_B64 0x13 2748 #define V_008DFC_SQ_S_ANDN2_B32 0x14 2749 #define V_008DFC_SQ_S_ANDN2_B64 0x15 2750 #define V_008DFC_SQ_S_ORN2_B32 0x16 2751 #define V_008DFC_SQ_S_ORN2_B64 0x17 2752 #define V_008DFC_SQ_S_NAND_B32 0x18 2753 #define V_008DFC_SQ_S_NAND_B64 0x19 2754 #define V_008DFC_SQ_S_NOR_B32 0x1A 2755 #define V_008DFC_SQ_S_NOR_B64 0x1B 2756 #define V_008DFC_SQ_S_XNOR_B32 0x1C 2757 #define V_008DFC_SQ_S_XNOR_B64 0x1D 2758 #define V_008DFC_SQ_S_LSHL_B32 0x1E 2759 #define V_008DFC_SQ_S_LSHL_B64 0x1F 2760 #define V_008DFC_SQ_S_LSHR_B32 0x20 2761 #define V_008DFC_SQ_S_LSHR_B64 0x21 2762 #define V_008DFC_SQ_S_ASHR_I32 0x22 2763 #define V_008DFC_SQ_S_ASHR_I64 0x23 2764 #define V_008DFC_SQ_S_BFM_B32 0x24 2765 #define V_008DFC_SQ_S_BFM_B64 0x25 2766 #define V_008DFC_SQ_S_MUL_I32 0x26 2767 #define V_008DFC_SQ_S_BFE_U32 0x27 2768 #define V_008DFC_SQ_S_BFE_I32 0x28 2769 #define V_008DFC_SQ_S_BFE_U64 0x29 2770 #define V_008DFC_SQ_S_BFE_I64 0x2A 2771 #define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B 2772 #define V_008DFC_SQ_S_ABSDIFF_I32 0x2C 2773 #define S_008DFC_ENCODING(x) (((x) & 0x03) << 30) 2774 #define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03) 2775 #define C_008DFC_ENCODING 0x3FFFFFFF 2776 #define V_008DFC_SQ_ENC_SOP2_FIELD 0x02 2777 #define R_008DFC_SQ_SOPK 0x008DFC 2778 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) 2779 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) 2780 #define C_008DFC_SIMM16 0xFFFF0000 2781 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16) 2782 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) 2783 #define C_008DFC_SDST 0xFF80FFFF 2784 #define V_008DFC_SQ_SGPR 0x00 2785 #define V_008DFC_SQ_VCC_LO 0x6A 2786 #define V_008DFC_SQ_VCC_HI 0x6B 2787 #define V_008DFC_SQ_TBA_LO 0x6C 2788 #define V_008DFC_SQ_TBA_HI 0x6D 2789 #define V_008DFC_SQ_TMA_LO 0x6E 2790 #define V_008DFC_SQ_TMA_HI 0x6F 2791 #define V_008DFC_SQ_TTMP0 0x70 2792 #define V_008DFC_SQ_TTMP1 0x71 2793 #define V_008DFC_SQ_TTMP2 0x72 2794 #define V_008DFC_SQ_TTMP3 0x73 2795 #define V_008DFC_SQ_TTMP4 0x74 2796 #define V_008DFC_SQ_TTMP5 0x75 2797 #define V_008DFC_SQ_TTMP6 0x76 2798 #define V_008DFC_SQ_TTMP7 0x77 2799 #define V_008DFC_SQ_TTMP8 0x78 2800 #define V_008DFC_SQ_TTMP9 0x79 2801 #define V_008DFC_SQ_TTMP10 0x7A 2802 #define V_008DFC_SQ_TTMP11 0x7B 2803 #define V_008DFC_SQ_M0 0x7C 2804 #define V_008DFC_SQ_EXEC_LO 0x7E 2805 #define V_008DFC_SQ_EXEC_HI 0x7F 2806 #define S_008DFC_OP(x) (((x) & 0x1F) << 23) 2807 #define G_008DFC_OP(x) (((x) >> 23) & 0x1F) 2808 #define C_008DFC_OP 0xF07FFFFF 2809 #define V_008DFC_SQ_S_MOVK_I32 0x00 2810 #define V_008DFC_SQ_S_CMOVK_I32 0x02 2811 #define V_008DFC_SQ_S_CMPK_EQ_I32 0x03 2812 #define V_008DFC_SQ_S_CMPK_LG_I32 0x04 2813 #define V_008DFC_SQ_S_CMPK_GT_I32 0x05 2814 #define V_008DFC_SQ_S_CMPK_GE_I32 0x06 2815 #define V_008DFC_SQ_S_CMPK_LT_I32 0x07 2816 #define V_008DFC_SQ_S_CMPK_LE_I32 0x08 2817 #define V_008DFC_SQ_S_CMPK_EQ_U32 0x09 2818 #define V_008DFC_SQ_S_CMPK_LG_U32 0x0A 2819 #define V_008DFC_SQ_S_CMPK_GT_U32 0x0B 2820 #define V_008DFC_SQ_S_CMPK_GE_U32 0x0C 2821 #define V_008DFC_SQ_S_CMPK_LT_U32 0x0D 2822 #define V_008DFC_SQ_S_CMPK_LE_U32 0x0E 2823 #define V_008DFC_SQ_S_ADDK_I32 0x0F 2824 #define V_008DFC_SQ_S_MULK_I32 0x10 2825 #define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11 2826 #define V_008DFC_SQ_S_GETREG_B32 0x12 2827 #define V_008DFC_SQ_S_SETREG_B32 0x13 2828 #define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14 2829 #define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15 2830 #define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28) 2831 #define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F) 2832 #define C_008DFC_ENCODING 0x0FFFFFFF 2833 #define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B 2834 #define R_008DFC_SQ_VOP3_0 0x008DFC 2835 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0) 2836 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) 2837 #define C_008DFC_VDST 0xFFFFFF00 2838 #define V_008DFC_SQ_VGPR 0x00 2839 #define S_008DFC_ABS(x) (((x) & 0x07) << 8) 2840 #define G_008DFC_ABS(x) (((x) >> 8) & 0x07) 2841 #define C_008DFC_ABS 0xFFFFF8FF 2842 #define S_008DFC_CLAMP(x) (((x) & 0x1) << 11) 2843 #define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1) 2844 #define C_008DFC_CLAMP 0xFFFFF7FF 2845 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17) 2846 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) 2847 #define C_008DFC_OP 0xFC01FFFF 2848 #define V_008DFC_SQ_V_OPC_OFFSET 0x00 2849 #define V_008DFC_SQ_V_OP2_OFFSET 0x100 2850 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 2851 #define V_008DFC_SQ_V_MAD_F32 0x141 2852 #define V_008DFC_SQ_V_MAD_I32_I24 0x142 2853 #define V_008DFC_SQ_V_MAD_U32_U24 0x143 2854 #define V_008DFC_SQ_V_CUBEID_F32 0x144 2855 #define V_008DFC_SQ_V_CUBESC_F32 0x145 2856 #define V_008DFC_SQ_V_CUBETC_F32 0x146 2857 #define V_008DFC_SQ_V_CUBEMA_F32 0x147 2858 #define V_008DFC_SQ_V_BFE_U32 0x148 2859 #define V_008DFC_SQ_V_BFE_I32 0x149 2860 #define V_008DFC_SQ_V_BFI_B32 0x14A 2861 #define V_008DFC_SQ_V_FMA_F32 0x14B 2862 #define V_008DFC_SQ_V_FMA_F64 0x14C 2863 #define V_008DFC_SQ_V_LERP_U8 0x14D 2864 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E 2865 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F 2866 #define V_008DFC_SQ_V_MULLIT_F32 0x150 2867 #define V_008DFC_SQ_V_MIN3_F32 0x151 2868 #define V_008DFC_SQ_V_MIN3_I32 0x152 2869 #define V_008DFC_SQ_V_MIN3_U32 0x153 2870 #define V_008DFC_SQ_V_MAX3_F32 0x154 2871 #define V_008DFC_SQ_V_MAX3_I32 0x155 2872 #define V_008DFC_SQ_V_MAX3_U32 0x156 2873 #define V_008DFC_SQ_V_MED3_F32 0x157 2874 #define V_008DFC_SQ_V_MED3_I32 0x158 2875 #define V_008DFC_SQ_V_MED3_U32 0x159 2876 #define V_008DFC_SQ_V_SAD_U8 0x15A 2877 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B 2878 #define V_008DFC_SQ_V_SAD_U16 0x15C 2879 #define V_008DFC_SQ_V_SAD_U32 0x15D 2880 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E 2881 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F 2882 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 2883 #define V_008DFC_SQ_V_LSHL_B64 0x161 2884 #define V_008DFC_SQ_V_LSHR_B64 0x162 2885 #define V_008DFC_SQ_V_ASHR_I64 0x163 2886 #define V_008DFC_SQ_V_ADD_F64 0x164 2887 #define V_008DFC_SQ_V_MUL_F64 0x165 2888 #define V_008DFC_SQ_V_MIN_F64 0x166 2889 #define V_008DFC_SQ_V_MAX_F64 0x167 2890 #define V_008DFC_SQ_V_LDEXP_F64 0x168 2891 #define V_008DFC_SQ_V_MUL_LO_U32 0x169 2892 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A 2893 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B 2894 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C 2895 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D 2896 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E 2897 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F 2898 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 2899 #define V_008DFC_SQ_V_MSAD_U8 0x171 2900 #define V_008DFC_SQ_V_QSAD_U8 0x172 2901 #define V_008DFC_SQ_V_MQSAD_U8 0x173 2902 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 2903 #define V_008DFC_SQ_V_OP1_OFFSET 0x180 2904 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 2905 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 2906 #define C_008DFC_ENCODING 0x03FFFFFF 2907 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 2908 #define R_008DFC_SQ_VOP2 0x008DFC 2909 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) 2910 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) 2911 #define C_008DFC_SRC0 0xFFFFFE00 2912 #define V_008DFC_SQ_SGPR 0x00 2913 #define V_008DFC_SQ_VCC_LO 0x6A 2914 #define V_008DFC_SQ_VCC_HI 0x6B 2915 #define V_008DFC_SQ_TBA_LO 0x6C 2916 #define V_008DFC_SQ_TBA_HI 0x6D 2917 #define V_008DFC_SQ_TMA_LO 0x6E 2918 #define V_008DFC_SQ_TMA_HI 0x6F 2919 #define V_008DFC_SQ_TTMP0 0x70 2920 #define V_008DFC_SQ_TTMP1 0x71 2921 #define V_008DFC_SQ_TTMP2 0x72 2922 #define V_008DFC_SQ_TTMP3 0x73 2923 #define V_008DFC_SQ_TTMP4 0x74 2924 #define V_008DFC_SQ_TTMP5 0x75 2925 #define V_008DFC_SQ_TTMP6 0x76 2926 #define V_008DFC_SQ_TTMP7 0x77 2927 #define V_008DFC_SQ_TTMP8 0x78 2928 #define V_008DFC_SQ_TTMP9 0x79 2929 #define V_008DFC_SQ_TTMP10 0x7A 2930 #define V_008DFC_SQ_TTMP11 0x7B 2931 #define V_008DFC_SQ_M0 0x7C 2932 #define V_008DFC_SQ_EXEC_LO 0x7E 2933 #define V_008DFC_SQ_EXEC_HI 0x7F 2934 #define V_008DFC_SQ_SRC_0 0x80 2935 #define V_008DFC_SQ_SRC_1_INT 0x81 2936 #define V_008DFC_SQ_SRC_2_INT 0x82 2937 #define V_008DFC_SQ_SRC_3_INT 0x83 2938 #define V_008DFC_SQ_SRC_4_INT 0x84 2939 #define V_008DFC_SQ_SRC_5_INT 0x85 2940 #define V_008DFC_SQ_SRC_6_INT 0x86 2941 #define V_008DFC_SQ_SRC_7_INT 0x87 2942 #define V_008DFC_SQ_SRC_8_INT 0x88 2943 #define V_008DFC_SQ_SRC_9_INT 0x89 2944 #define V_008DFC_SQ_SRC_10_INT 0x8A 2945 #define V_008DFC_SQ_SRC_11_INT 0x8B 2946 #define V_008DFC_SQ_SRC_12_INT 0x8C 2947 #define V_008DFC_SQ_SRC_13_INT 0x8D 2948 #define V_008DFC_SQ_SRC_14_INT 0x8E 2949 #define V_008DFC_SQ_SRC_15_INT 0x8F 2950 #define V_008DFC_SQ_SRC_16_INT 0x90 2951 #define V_008DFC_SQ_SRC_17_INT 0x91 2952 #define V_008DFC_SQ_SRC_18_INT 0x92 2953 #define V_008DFC_SQ_SRC_19_INT 0x93 2954 #define V_008DFC_SQ_SRC_20_INT 0x94 2955 #define V_008DFC_SQ_SRC_21_INT 0x95 2956 #define V_008DFC_SQ_SRC_22_INT 0x96 2957 #define V_008DFC_SQ_SRC_23_INT 0x97 2958 #define V_008DFC_SQ_SRC_24_INT 0x98 2959 #define V_008DFC_SQ_SRC_25_INT 0x99 2960 #define V_008DFC_SQ_SRC_26_INT 0x9A 2961 #define V_008DFC_SQ_SRC_27_INT 0x9B 2962 #define V_008DFC_SQ_SRC_28_INT 0x9C 2963 #define V_008DFC_SQ_SRC_29_INT 0x9D 2964 #define V_008DFC_SQ_SRC_30_INT 0x9E 2965 #define V_008DFC_SQ_SRC_31_INT 0x9F 2966 #define V_008DFC_SQ_SRC_32_INT 0xA0 2967 #define V_008DFC_SQ_SRC_33_INT 0xA1 2968 #define V_008DFC_SQ_SRC_34_INT 0xA2 2969 #define V_008DFC_SQ_SRC_35_INT 0xA3 2970 #define V_008DFC_SQ_SRC_36_INT 0xA4 2971 #define V_008DFC_SQ_SRC_37_INT 0xA5 2972 #define V_008DFC_SQ_SRC_38_INT 0xA6 2973 #define V_008DFC_SQ_SRC_39_INT 0xA7 2974 #define V_008DFC_SQ_SRC_40_INT 0xA8 2975 #define V_008DFC_SQ_SRC_41_INT 0xA9 2976 #define V_008DFC_SQ_SRC_42_INT 0xAA 2977 #define V_008DFC_SQ_SRC_43_INT 0xAB 2978 #define V_008DFC_SQ_SRC_44_INT 0xAC 2979 #define V_008DFC_SQ_SRC_45_INT 0xAD 2980 #define V_008DFC_SQ_SRC_46_INT 0xAE 2981 #define V_008DFC_SQ_SRC_47_INT 0xAF 2982 #define V_008DFC_SQ_SRC_48_INT 0xB0 2983 #define V_008DFC_SQ_SRC_49_INT 0xB1 2984 #define V_008DFC_SQ_SRC_50_INT 0xB2 2985 #define V_008DFC_SQ_SRC_51_INT 0xB3 2986 #define V_008DFC_SQ_SRC_52_INT 0xB4 2987 #define V_008DFC_SQ_SRC_53_INT 0xB5 2988 #define V_008DFC_SQ_SRC_54_INT 0xB6 2989 #define V_008DFC_SQ_SRC_55_INT 0xB7 2990 #define V_008DFC_SQ_SRC_56_INT 0xB8 2991 #define V_008DFC_SQ_SRC_57_INT 0xB9 2992 #define V_008DFC_SQ_SRC_58_INT 0xBA 2993 #define V_008DFC_SQ_SRC_59_INT 0xBB 2994 #define V_008DFC_SQ_SRC_60_INT 0xBC 2995 #define V_008DFC_SQ_SRC_61_INT 0xBD 2996 #define V_008DFC_SQ_SRC_62_INT 0xBE 2997 #define V_008DFC_SQ_SRC_63_INT 0xBF 2998 #define V_008DFC_SQ_SRC_64_INT 0xC0 2999 #define V_008DFC_SQ_SRC_M_1_INT 0xC1 3000 #define V_008DFC_SQ_SRC_M_2_INT 0xC2 3001 #define V_008DFC_SQ_SRC_M_3_INT 0xC3 3002 #define V_008DFC_SQ_SRC_M_4_INT 0xC4 3003 #define V_008DFC_SQ_SRC_M_5_INT 0xC5 3004 #define V_008DFC_SQ_SRC_M_6_INT 0xC6 3005 #define V_008DFC_SQ_SRC_M_7_INT 0xC7 3006 #define V_008DFC_SQ_SRC_M_8_INT 0xC8 3007 #define V_008DFC_SQ_SRC_M_9_INT 0xC9 3008 #define V_008DFC_SQ_SRC_M_10_INT 0xCA 3009 #define V_008DFC_SQ_SRC_M_11_INT 0xCB 3010 #define V_008DFC_SQ_SRC_M_12_INT 0xCC 3011 #define V_008DFC_SQ_SRC_M_13_INT 0xCD 3012 #define V_008DFC_SQ_SRC_M_14_INT 0xCE 3013 #define V_008DFC_SQ_SRC_M_15_INT 0xCF 3014 #define V_008DFC_SQ_SRC_M_16_INT 0xD0 3015 #define V_008DFC_SQ_SRC_0_5 0xF0 3016 #define V_008DFC_SQ_SRC_M_0_5 0xF1 3017 #define V_008DFC_SQ_SRC_1 0xF2 3018 #define V_008DFC_SQ_SRC_M_1 0xF3 3019 #define V_008DFC_SQ_SRC_2 0xF4 3020 #define V_008DFC_SQ_SRC_M_2 0xF5 3021 #define V_008DFC_SQ_SRC_4 0xF6 3022 #define V_008DFC_SQ_SRC_M_4 0xF7 3023 #define V_008DFC_SQ_SRC_VCCZ 0xFB 3024 #define V_008DFC_SQ_SRC_EXECZ 0xFC 3025 #define V_008DFC_SQ_SRC_SCC 0xFD 3026 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE 3027 #define V_008DFC_SQ_SRC_VGPR 0x100 3028 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) 3029 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) 3030 #define C_008DFC_VSRC1 0xFFFE01FF 3031 #define V_008DFC_SQ_VGPR 0x00 3032 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17) 3033 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) 3034 #define C_008DFC_VDST 0xFE01FFFF 3035 #define V_008DFC_SQ_VGPR 0x00 3036 #define S_008DFC_OP(x) (((x) & 0x3F) << 25) 3037 #define G_008DFC_OP(x) (((x) >> 25) & 0x3F) 3038 #define C_008DFC_OP 0x81FFFFFF 3039 #define V_008DFC_SQ_V_CNDMASK_B32 0x00 3040 #define V_008DFC_SQ_V_READLANE_B32 0x01 3041 #define V_008DFC_SQ_V_WRITELANE_B32 0x02 3042 #define V_008DFC_SQ_V_ADD_F32 0x03 3043 #define V_008DFC_SQ_V_SUB_F32 0x04 3044 #define V_008DFC_SQ_V_SUBREV_F32 0x05 3045 #define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06 3046 #define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07 3047 #define V_008DFC_SQ_V_MUL_F32 0x08 3048 #define V_008DFC_SQ_V_MUL_I32_I24 0x09 3049 #define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A 3050 #define V_008DFC_SQ_V_MUL_U32_U24 0x0B 3051 #define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C 3052 #define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D 3053 #define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E 3054 #define V_008DFC_SQ_V_MIN_F32 0x0F 3055 #define V_008DFC_SQ_V_MAX_F32 0x10 3056 #define V_008DFC_SQ_V_MIN_I32 0x11 3057 #define V_008DFC_SQ_V_MAX_I32 0x12 3058 #define V_008DFC_SQ_V_MIN_U32 0x13 3059 #define V_008DFC_SQ_V_MAX_U32 0x14 3060 #define V_008DFC_SQ_V_LSHR_B32 0x15 3061 #define V_008DFC_SQ_V_LSHRREV_B32 0x16 3062 #define V_008DFC_SQ_V_ASHR_I32 0x17 3063 #define V_008DFC_SQ_V_ASHRREV_I32 0x18 3064 #define V_008DFC_SQ_V_LSHL_B32 0x19 3065 #define V_008DFC_SQ_V_LSHLREV_B32 0x1A 3066 #define V_008DFC_SQ_V_AND_B32 0x1B 3067 #define V_008DFC_SQ_V_OR_B32 0x1C 3068 #define V_008DFC_SQ_V_XOR_B32 0x1D 3069 #define V_008DFC_SQ_V_BFM_B32 0x1E 3070 #define V_008DFC_SQ_V_MAC_F32 0x1F 3071 #define V_008DFC_SQ_V_MADMK_F32 0x20 3072 #define V_008DFC_SQ_V_MADAK_F32 0x21 3073 #define V_008DFC_SQ_V_BCNT_U32_B32 0x22 3074 #define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23 3075 #define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24 3076 #define V_008DFC_SQ_V_ADD_I32 0x25 3077 #define V_008DFC_SQ_V_SUB_I32 0x26 3078 #define V_008DFC_SQ_V_SUBREV_I32 0x27 3079 #define V_008DFC_SQ_V_ADDC_U32 0x28 3080 #define V_008DFC_SQ_V_SUBB_U32 0x29 3081 #define V_008DFC_SQ_V_SUBBREV_U32 0x2A 3082 #define V_008DFC_SQ_V_LDEXP_F32 0x2B 3083 #define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C 3084 #define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D 3085 #define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E 3086 #define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F 3087 #define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30 3088 #define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31 3089 #define S_008DFC_ENCODING(x) (((x) & 0x1) << 31) 3090 #define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1) 3091 #define C_008DFC_ENCODING 0x7FFFFFFF 3092 #define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC 3093 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0) 3094 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) 3095 #define C_008DFC_VDST 0xFFFFFF00 3096 #define V_008DFC_SQ_VGPR 0x00 3097 #define S_008DFC_SDST(x) (((x) & 0x7F) << 8) 3098 #define G_008DFC_SDST(x) (((x) >> 8) & 0x7F) 3099 #define C_008DFC_SDST 0xFFFF80FF 3100 #define V_008DFC_SQ_SGPR 0x00 3101 #define V_008DFC_SQ_VCC_LO 0x6A 3102 #define V_008DFC_SQ_VCC_HI 0x6B 3103 #define V_008DFC_SQ_TBA_LO 0x6C 3104 #define V_008DFC_SQ_TBA_HI 0x6D 3105 #define V_008DFC_SQ_TMA_LO 0x6E 3106 #define V_008DFC_SQ_TMA_HI 0x6F 3107 #define V_008DFC_SQ_TTMP0 0x70 3108 #define V_008DFC_SQ_TTMP1 0x71 3109 #define V_008DFC_SQ_TTMP2 0x72 3110 #define V_008DFC_SQ_TTMP3 0x73 3111 #define V_008DFC_SQ_TTMP4 0x74 3112 #define V_008DFC_SQ_TTMP5 0x75 3113 #define V_008DFC_SQ_TTMP6 0x76 3114 #define V_008DFC_SQ_TTMP7 0x77 3115 #define V_008DFC_SQ_TTMP8 0x78 3116 #define V_008DFC_SQ_TTMP9 0x79 3117 #define V_008DFC_SQ_TTMP10 0x7A 3118 #define V_008DFC_SQ_TTMP11 0x7B 3119 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17) 3120 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) 3121 #define C_008DFC_OP 0xFC01FFFF 3122 #define V_008DFC_SQ_V_OPC_OFFSET 0x00 3123 #define V_008DFC_SQ_V_OP2_OFFSET 0x100 3124 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 3125 #define V_008DFC_SQ_V_MAD_F32 0x141 3126 #define V_008DFC_SQ_V_MAD_I32_I24 0x142 3127 #define V_008DFC_SQ_V_MAD_U32_U24 0x143 3128 #define V_008DFC_SQ_V_CUBEID_F32 0x144 3129 #define V_008DFC_SQ_V_CUBESC_F32 0x145 3130 #define V_008DFC_SQ_V_CUBETC_F32 0x146 3131 #define V_008DFC_SQ_V_CUBEMA_F32 0x147 3132 #define V_008DFC_SQ_V_BFE_U32 0x148 3133 #define V_008DFC_SQ_V_BFE_I32 0x149 3134 #define V_008DFC_SQ_V_BFI_B32 0x14A 3135 #define V_008DFC_SQ_V_FMA_F32 0x14B 3136 #define V_008DFC_SQ_V_FMA_F64 0x14C 3137 #define V_008DFC_SQ_V_LERP_U8 0x14D 3138 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E 3139 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F 3140 #define V_008DFC_SQ_V_MULLIT_F32 0x150 3141 #define V_008DFC_SQ_V_MIN3_F32 0x151 3142 #define V_008DFC_SQ_V_MIN3_I32 0x152 3143 #define V_008DFC_SQ_V_MIN3_U32 0x153 3144 #define V_008DFC_SQ_V_MAX3_F32 0x154 3145 #define V_008DFC_SQ_V_MAX3_I32 0x155 3146 #define V_008DFC_SQ_V_MAX3_U32 0x156 3147 #define V_008DFC_SQ_V_MED3_F32 0x157 3148 #define V_008DFC_SQ_V_MED3_I32 0x158 3149 #define V_008DFC_SQ_V_MED3_U32 0x159 3150 #define V_008DFC_SQ_V_SAD_U8 0x15A 3151 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B 3152 #define V_008DFC_SQ_V_SAD_U16 0x15C 3153 #define V_008DFC_SQ_V_SAD_U32 0x15D 3154 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E 3155 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F 3156 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 3157 #define V_008DFC_SQ_V_LSHL_B64 0x161 3158 #define V_008DFC_SQ_V_LSHR_B64 0x162 3159 #define V_008DFC_SQ_V_ASHR_I64 0x163 3160 #define V_008DFC_SQ_V_ADD_F64 0x164 3161 #define V_008DFC_SQ_V_MUL_F64 0x165 3162 #define V_008DFC_SQ_V_MIN_F64 0x166 3163 #define V_008DFC_SQ_V_MAX_F64 0x167 3164 #define V_008DFC_SQ_V_LDEXP_F64 0x168 3165 #define V_008DFC_SQ_V_MUL_LO_U32 0x169 3166 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A 3167 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B 3168 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C 3169 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D 3170 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E 3171 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F 3172 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 3173 #define V_008DFC_SQ_V_MSAD_U8 0x171 3174 #define V_008DFC_SQ_V_QSAD_U8 0x172 3175 #define V_008DFC_SQ_V_MQSAD_U8 0x173 3176 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 3177 #define V_008DFC_SQ_V_OP1_OFFSET 0x180 3178 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 3179 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 3180 #define C_008DFC_ENCODING 0x03FFFFFF 3181 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 3182 #define R_008DFC_SQ_MUBUF_0 0x008DFC 3183 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) 3184 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) 3185 #define C_008DFC_OFFSET 0xFFFFF000 3186 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) 3187 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) 3188 #define C_008DFC_OFFEN 0xFFFFEFFF 3189 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) 3190 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) 3191 #define C_008DFC_IDXEN 0xFFFFDFFF 3192 #define S_008DFC_GLC(x) (((x) & 0x1) << 14) 3193 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1) 3194 #define C_008DFC_GLC 0xFFFFBFFF 3195 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) 3196 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) 3197 #define C_008DFC_ADDR64 0xFFFF7FFF 3198 #define S_008DFC_LDS(x) (((x) & 0x1) << 16) 3199 #define G_008DFC_LDS(x) (((x) >> 16) & 0x1) 3200 #define C_008DFC_LDS 0xFFFEFFFF 3201 #define S_008DFC_OP(x) (((x) & 0x7F) << 18) 3202 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F) 3203 #define C_008DFC_OP 0xFE03FFFF 3204 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00 3205 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01 3206 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02 3207 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03 3208 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04 3209 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05 3210 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06 3211 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07 3212 #define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08 3213 #define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09 3214 #define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A 3215 #define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B 3216 #define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C 3217 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D 3218 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E 3219 #define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18 3220 #define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A 3221 #define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C 3222 #define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D 3223 #define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E 3224 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30 3225 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31 3226 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32 3227 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33 3228 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34 3229 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35 3230 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36 3231 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37 3232 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38 3233 #define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39 3234 #define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A 3235 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B 3236 #define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C 3237 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D 3238 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E 3239 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F 3240 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40 3241 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50 3242 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 3243 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52 3244 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53 3245 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54 3246 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55 3247 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56 3248 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57 3249 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58 3250 #define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59 3251 #define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A 3252 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B 3253 #define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C 3254 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D 3255 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E 3256 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F 3257 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60 3258 #define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70 3259 #define V_008DFC_SQ_BUFFER_WBINVL1 0x71 3260 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) 3261 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) 3262 #define C_008DFC_ENCODING 0x03FFFFFF 3263 #define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38 3264 #endif 3265 #define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00 3266 #define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04 3267 #define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0) 3268 #define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF) 3269 #define C_008F04_BASE_ADDRESS_HI 0xFFFF0000 3270 #define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16) 3271 #define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF) 3272 #define C_008F04_STRIDE 0xC000FFFF 3273 #define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30) 3274 #define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1) 3275 #define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF 3276 #define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31) 3277 #define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1) 3278 #define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF 3279 #define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08 3280 #define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C 3281 #define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0) 3282 #define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07) 3283 #define C_008F0C_DST_SEL_X 0xFFFFFFF8 3284 #define V_008F0C_SQ_SEL_0 0x00 3285 #define V_008F0C_SQ_SEL_1 0x01 3286 #define V_008F0C_SQ_SEL_RESERVED_0 0x02 3287 #define V_008F0C_SQ_SEL_RESERVED_1 0x03 3288 #define V_008F0C_SQ_SEL_X 0x04 3289 #define V_008F0C_SQ_SEL_Y 0x05 3290 #define V_008F0C_SQ_SEL_Z 0x06 3291 #define V_008F0C_SQ_SEL_W 0x07 3292 #define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3) 3293 #define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07) 3294 #define C_008F0C_DST_SEL_Y 0xFFFFFFC7 3295 #define V_008F0C_SQ_SEL_0 0x00 3296 #define V_008F0C_SQ_SEL_1 0x01 3297 #define V_008F0C_SQ_SEL_RESERVED_0 0x02 3298 #define V_008F0C_SQ_SEL_RESERVED_1 0x03 3299 #define V_008F0C_SQ_SEL_X 0x04 3300 #define V_008F0C_SQ_SEL_Y 0x05 3301 #define V_008F0C_SQ_SEL_Z 0x06 3302 #define V_008F0C_SQ_SEL_W 0x07 3303 #define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6) 3304 #define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07) 3305 #define C_008F0C_DST_SEL_Z 0xFFFFFE3F 3306 #define V_008F0C_SQ_SEL_0 0x00 3307 #define V_008F0C_SQ_SEL_1 0x01 3308 #define V_008F0C_SQ_SEL_RESERVED_0 0x02 3309 #define V_008F0C_SQ_SEL_RESERVED_1 0x03 3310 #define V_008F0C_SQ_SEL_X 0x04 3311 #define V_008F0C_SQ_SEL_Y 0x05 3312 #define V_008F0C_SQ_SEL_Z 0x06 3313 #define V_008F0C_SQ_SEL_W 0x07 3314 #define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9) 3315 #define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07) 3316 #define C_008F0C_DST_SEL_W 0xFFFFF1FF 3317 #define V_008F0C_SQ_SEL_0 0x00 3318 #define V_008F0C_SQ_SEL_1 0x01 3319 #define V_008F0C_SQ_SEL_RESERVED_0 0x02 3320 #define V_008F0C_SQ_SEL_RESERVED_1 0x03 3321 #define V_008F0C_SQ_SEL_X 0x04 3322 #define V_008F0C_SQ_SEL_Y 0x05 3323 #define V_008F0C_SQ_SEL_Z 0x06 3324 #define V_008F0C_SQ_SEL_W 0x07 3325 #define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12) 3326 #define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07) 3327 #define C_008F0C_NUM_FORMAT 0xFFFF8FFF 3328 #define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00 3329 #define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01 3330 #define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02 3331 #define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03 3332 #define V_008F0C_BUF_NUM_FORMAT_UINT 0x04 3333 #define V_008F0C_BUF_NUM_FORMAT_SINT 0x05 3334 #define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06 3335 #define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07 3336 #define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15) 3337 #define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F) 3338 #define C_008F0C_DATA_FORMAT 0xFFF87FFF 3339 #define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00 3340 #define V_008F0C_BUF_DATA_FORMAT_8 0x01 3341 #define V_008F0C_BUF_DATA_FORMAT_16 0x02 3342 #define V_008F0C_BUF_DATA_FORMAT_8_8 0x03 3343 #define V_008F0C_BUF_DATA_FORMAT_32 0x04 3344 #define V_008F0C_BUF_DATA_FORMAT_16_16 0x05 3345 #define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06 3346 #define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07 3347 #define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08 3348 #define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09 3349 #define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A 3350 #define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B 3351 #define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C 3352 #define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D 3353 #define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E 3354 #define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F 3355 #define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19) 3356 #define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03) 3357 #define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF 3358 #define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21) 3359 #define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03) 3360 #define C_008F0C_INDEX_STRIDE 0xFF9FFFFF 3361 #define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23) 3362 #define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1) 3363 #define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF 3364 #define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25) 3365 #define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1) 3366 #define C_008F0C_HASH_ENABLE 0xFDFFFFFF 3367 #define S_008F0C_HEAP(x) (((x) & 0x1) << 26) 3368 #define G_008F0C_HEAP(x) (((x) >> 26) & 0x1) 3369 #define C_008F0C_HEAP 0xFBFFFFFF 3370 #define S_008F0C_TYPE(x) (((x) & 0x03) << 30) 3371 #define G_008F0C_TYPE(x) (((x) >> 30) & 0x03) 3372 #define C_008F0C_TYPE 0x3FFFFFFF 3373 #define V_008F0C_SQ_RSRC_BUF 0x00 3374 #define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01 3375 #define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02 3376 #define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03 3377 #define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10 3378 #define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14 3379 #define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0) 3380 #define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF) 3381 #define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00 3382 #define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8) 3383 #define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF) 3384 #define C_008F14_MIN_LOD 0xFFF000FF 3385 #define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20) 3386 #define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F) 3387 #define C_008F14_DATA_FORMAT 0xFC0FFFFF 3388 #define V_008F14_IMG_DATA_FORMAT_INVALID 0x00 3389 #define V_008F14_IMG_DATA_FORMAT_8 0x01 3390 #define V_008F14_IMG_DATA_FORMAT_16 0x02 3391 #define V_008F14_IMG_DATA_FORMAT_8_8 0x03 3392 #define V_008F14_IMG_DATA_FORMAT_32 0x04 3393 #define V_008F14_IMG_DATA_FORMAT_16_16 0x05 3394 #define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06 3395 #define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07 3396 #define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08 3397 #define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09 3398 #define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A 3399 #define V_008F14_IMG_DATA_FORMAT_32_32 0x0B 3400 #define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C 3401 #define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D 3402 #define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E 3403 #define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F 3404 #define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10 3405 #define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11 3406 #define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12 3407 #define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13 3408 #define V_008F14_IMG_DATA_FORMAT_8_24 0x14 3409 #define V_008F14_IMG_DATA_FORMAT_24_8 0x15 3410 #define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16 3411 #define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17 3412 #define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18 3413 #define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19 3414 #define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A 3415 #define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B 3416 #define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C 3417 #define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D 3418 #define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E 3419 #define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F 3420 #define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20 3421 #define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21 3422 #define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22 3423 #define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A 3424 #define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B 3425 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C 3426 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D 3427 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E 3428 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F 3429 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30 3430 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31 3431 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32 3432 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33 3433 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34 3434 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35 3435 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36 3436 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37 3437 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38 3438 #define V_008F14_IMG_DATA_FORMAT_4_4 0x39 3439 #define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A 3440 #define V_008F14_IMG_DATA_FORMAT_1 0x3B 3441 #define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C 3442 #define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D 3443 #define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E 3444 #define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F 3445 #define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26) 3446 #define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F) 3447 #define C_008F14_NUM_FORMAT 0xC3FFFFFF 3448 #define V_008F14_IMG_NUM_FORMAT_UNORM 0x00 3449 #define V_008F14_IMG_NUM_FORMAT_SNORM 0x01 3450 #define V_008F14_IMG_NUM_FORMAT_USCALED 0x02 3451 #define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03 3452 #define V_008F14_IMG_NUM_FORMAT_UINT 0x04 3453 #define V_008F14_IMG_NUM_FORMAT_SINT 0x05 3454 #define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06 3455 #define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07 3456 #define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08 3457 #define V_008F14_IMG_NUM_FORMAT_SRGB 0x09 3458 #define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A 3459 #define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B 3460 #define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C 3461 #define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D 3462 #define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E 3463 #define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F 3464 #define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18 3465 #define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0) 3466 #define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF) 3467 #define C_008F18_WIDTH 0xFFFFC000 3468 #define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14) 3469 #define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF) 3470 #define C_008F18_HEIGHT 0xF0003FFF 3471 #define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28) 3472 #define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07) 3473 #define C_008F18_PERF_MOD 0x8FFFFFFF 3474 #define S_008F18_INTERLACED(x) (((x) & 0x1) << 31) 3475 #define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1) 3476 #define C_008F18_INTERLACED 0x7FFFFFFF 3477 #define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C 3478 #define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0) 3479 #define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07) 3480 #define C_008F1C_DST_SEL_X 0xFFFFFFF8 3481 #define V_008F1C_SQ_SEL_0 0x00 3482 #define V_008F1C_SQ_SEL_1 0x01 3483 #define V_008F1C_SQ_SEL_RESERVED_0 0x02 3484 #define V_008F1C_SQ_SEL_RESERVED_1 0x03 3485 #define V_008F1C_SQ_SEL_X 0x04 3486 #define V_008F1C_SQ_SEL_Y 0x05 3487 #define V_008F1C_SQ_SEL_Z 0x06 3488 #define V_008F1C_SQ_SEL_W 0x07 3489 #define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3) 3490 #define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07) 3491 #define C_008F1C_DST_SEL_Y 0xFFFFFFC7 3492 #define V_008F1C_SQ_SEL_0 0x00 3493 #define V_008F1C_SQ_SEL_1 0x01 3494 #define V_008F1C_SQ_SEL_RESERVED_0 0x02 3495 #define V_008F1C_SQ_SEL_RESERVED_1 0x03 3496 #define V_008F1C_SQ_SEL_X 0x04 3497 #define V_008F1C_SQ_SEL_Y 0x05 3498 #define V_008F1C_SQ_SEL_Z 0x06 3499 #define V_008F1C_SQ_SEL_W 0x07 3500 #define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6) 3501 #define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07) 3502 #define C_008F1C_DST_SEL_Z 0xFFFFFE3F 3503 #define V_008F1C_SQ_SEL_0 0x00 3504 #define V_008F1C_SQ_SEL_1 0x01 3505 #define V_008F1C_SQ_SEL_RESERVED_0 0x02 3506 #define V_008F1C_SQ_SEL_RESERVED_1 0x03 3507 #define V_008F1C_SQ_SEL_X 0x04 3508 #define V_008F1C_SQ_SEL_Y 0x05 3509 #define V_008F1C_SQ_SEL_Z 0x06 3510 #define V_008F1C_SQ_SEL_W 0x07 3511 #define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9) 3512 #define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07) 3513 #define C_008F1C_DST_SEL_W 0xFFFFF1FF 3514 #define V_008F1C_SQ_SEL_0 0x00 3515 #define V_008F1C_SQ_SEL_1 0x01 3516 #define V_008F1C_SQ_SEL_RESERVED_0 0x02 3517 #define V_008F1C_SQ_SEL_RESERVED_1 0x03 3518 #define V_008F1C_SQ_SEL_X 0x04 3519 #define V_008F1C_SQ_SEL_Y 0x05 3520 #define V_008F1C_SQ_SEL_Z 0x06 3521 #define V_008F1C_SQ_SEL_W 0x07 3522 #define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12) 3523 #define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F) 3524 #define C_008F1C_BASE_LEVEL 0xFFFF0FFF 3525 #define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16) 3526 #define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F) 3527 #define C_008F1C_LAST_LEVEL 0xFFF0FFFF 3528 #define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20) 3529 #define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F) 3530 #define C_008F1C_TILING_INDEX 0xFE0FFFFF 3531 #define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25) 3532 #define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1) 3533 #define C_008F1C_POW2_PAD 0xFDFFFFFF 3534 #define S_008F1C_TYPE(x) (((x) & 0x0F) << 28) 3535 #define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F) 3536 #define C_008F1C_TYPE 0x0FFFFFFF 3537 #define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00 3538 #define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01 3539 #define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02 3540 #define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03 3541 #define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04 3542 #define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05 3543 #define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06 3544 #define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07 3545 #define V_008F1C_SQ_RSRC_IMG_1D 0x08 3546 #define V_008F1C_SQ_RSRC_IMG_2D 0x09 3547 #define V_008F1C_SQ_RSRC_IMG_3D 0x0A 3548 #define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B 3549 #define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C 3550 #define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D 3551 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E 3552 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F 3553 #define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20 3554 #define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0) 3555 #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF) 3556 #define C_008F20_DEPTH 0xFFFFE000 3557 #define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13) 3558 #define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF) 3559 #define C_008F20_PITCH 0xF8001FFF 3560 #define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24 3561 #define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0) 3562 #define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF) 3563 #define C_008F24_BASE_ARRAY 0xFFFFE000 3564 #define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13) 3565 #define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF) 3566 #define C_008F24_LAST_ARRAY 0xFC001FFF 3567 #define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28 3568 #define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0) 3569 #define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF) 3570 #define C_008F28_MIN_LOD_WARN 0xFFFFF000 3571 #define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C 3572 #define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30 3573 #define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0) 3574 #define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07) 3575 #define C_008F30_CLAMP_X 0xFFFFFFF8 3576 #define V_008F30_SQ_TEX_WRAP 0x00 3577 #define V_008F30_SQ_TEX_MIRROR 0x01 3578 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 3579 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 3580 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 3581 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 3582 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 3583 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 3584 #define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3) 3585 #define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07) 3586 #define C_008F30_CLAMP_Y 0xFFFFFFC7 3587 #define V_008F30_SQ_TEX_WRAP 0x00 3588 #define V_008F30_SQ_TEX_MIRROR 0x01 3589 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 3590 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 3591 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 3592 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 3593 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 3594 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 3595 #define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6) 3596 #define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07) 3597 #define C_008F30_CLAMP_Z 0xFFFFFE3F 3598 #define V_008F30_SQ_TEX_WRAP 0x00 3599 #define V_008F30_SQ_TEX_MIRROR 0x01 3600 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 3601 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 3602 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 3603 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 3604 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 3605 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 3606 #define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12) 3607 #define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07) 3608 #define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF 3609 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00 3610 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01 3611 #define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02 3612 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03 3613 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04 3614 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05 3615 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06 3616 #define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07 3617 #define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15) 3618 #define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1) 3619 #define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF 3620 #define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19) 3621 #define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1) 3622 #define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF 3623 #define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20) 3624 #define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1) 3625 #define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF 3626 #define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27) 3627 #define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1) 3628 #define C_008F30_TRUNC_COORD 0xF7FFFFFF 3629 #define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28) 3630 #define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1) 3631 #define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF 3632 #define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29) 3633 #define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03) 3634 #define C_008F30_FILTER_MODE 0x9FFFFFFF 3635 #define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34 3636 #define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0) 3637 #define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF) 3638 #define C_008F34_MIN_LOD 0xFFFFF000 3639 #define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12) 3640 #define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF) 3641 #define C_008F34_MAX_LOD 0xFF000FFF 3642 #define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24) 3643 #define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F) 3644 #define C_008F34_PERF_MIP 0xF0FFFFFF 3645 #define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28) 3646 #define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F) 3647 #define C_008F34_PERF_Z 0x0FFFFFFF 3648 #define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38 3649 #define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0) 3650 #define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF) 3651 #define C_008F38_LOD_BIAS 0xFFFFC000 3652 #define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14) 3653 #define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F) 3654 #define C_008F38_LOD_BIAS_SEC 0xFFF03FFF 3655 #define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20) 3656 #define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03) 3657 #define C_008F38_XY_MAG_FILTER 0xFFCFFFFF 3658 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 3659 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 3660 #define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22) 3661 #define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03) 3662 #define C_008F38_XY_MIN_FILTER 0xFF3FFFFF 3663 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 3664 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 3665 #define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24) 3666 #define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03) 3667 #define C_008F38_Z_FILTER 0xFCFFFFFF 3668 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 3669 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 3670 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 3671 #define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26) 3672 #define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03) 3673 #define C_008F38_MIP_FILTER 0xF3FFFFFF 3674 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 3675 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 3676 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 3677 #define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28) 3678 #define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1) 3679 #define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF 3680 #define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29) 3681 #define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1) 3682 #define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF 3683 #define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30) 3684 #define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1) 3685 #define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF 3686 #define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C 3687 #define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0) 3688 #define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF) 3689 #define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000 3690 #define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30) 3691 #define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03) 3692 #define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF 3693 #define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00 3694 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01 3695 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02 3696 #define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03 3697 #define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC 3698 #define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0) 3699 #define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F) 3700 #define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0 3701 #define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4) 3702 #define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F) 3703 #define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F 3704 #define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8) 3705 #define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F) 3706 #define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF 3707 #define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12) 3708 #define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F) 3709 #define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF 3710 #define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16) 3711 #define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F) 3712 #define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF 3713 #define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0 3714 #define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0) 3715 #define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF) 3716 #define C_0090E0_PS_CU_EN 0xFFFF0000 3717 #define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16) 3718 #define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF) 3719 #define C_0090E0_VS_CU_EN 0x0000FFFF 3720 #define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4 3721 #define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0) 3722 #define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF) 3723 #define C_0090E4_GS_CU_EN 0xFFFF0000 3724 #define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16) 3725 #define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF) 3726 #define C_0090E4_ES_CU_EN 0x0000FFFF 3727 #define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 3728 #define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0) 3729 #define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF) 3730 #define C_0090E8_LSHS_CU_EN 0xFFFF0000 3731 #define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC 3732 #define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) 3733 #define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) 3734 #define C_0090EC_MAX_WAVE_ID 0xFFFFF000 3735 #define R_0090F0_SPI_ARB_PRIORITY 0x0090F0 3736 #define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0) 3737 #define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07) 3738 #define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8 3739 #define V_0090F0_X_R0 0x00 3740 #define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3) 3741 #define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07) 3742 #define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7 3743 #define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6) 3744 #define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07) 3745 #define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F 3746 #define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 3747 #define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0) 3748 #define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF) 3749 #define C_0090F4_TS0_DURATION 0xFFFF0000 3750 #define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16) 3751 #define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF) 3752 #define C_0090F4_TS1_DURATION 0x0000FFFF 3753 #define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 3754 #define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0) 3755 #define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF) 3756 #define C_0090F8_TS2_DURATION 0xFFFF0000 3757 #define R_009100_SPI_CONFIG_CNTL 0x009100 3758 #define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0) 3759 #define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF) 3760 #define C_009100_GPR_WRITE_PRIORITY 0xFFE00000 3761 #define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21) 3762 #define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07) 3763 #define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF 3764 #define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24) 3765 #define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1) 3766 #define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF 3767 #define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25) 3768 #define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1) 3769 #define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF 3770 #define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26) 3771 #define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1) 3772 #define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF 3773 #define R_00913C_SPI_CONFIG_CNTL_1 0x00913C 3774 #define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0) 3775 #define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F) 3776 #define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0 3777 #define V_00913C_X_DELAY_14_CLKS 0x00 3778 #define V_00913C_X_DELAY_16_CLKS 0x01 3779 #define V_00913C_X_DELAY_18_CLKS 0x02 3780 #define V_00913C_X_DELAY_20_CLKS 0x03 3781 #define V_00913C_X_DELAY_22_CLKS 0x04 3782 #define V_00913C_X_DELAY_24_CLKS 0x05 3783 #define V_00913C_X_DELAY_26_CLKS 0x06 3784 #define V_00913C_X_DELAY_28_CLKS 0x07 3785 #define V_00913C_X_DELAY_30_CLKS 0x08 3786 #define V_00913C_X_DELAY_32_CLKS 0x09 3787 #define V_00913C_X_DELAY_34_CLKS 0x0A 3788 #define V_00913C_X_DELAY_4_CLKS 0x0B 3789 #define V_00913C_X_DELAY_6_CLKS 0x0C 3790 #define V_00913C_X_DELAY_8_CLKS 0x0D 3791 #define V_00913C_X_DELAY_10_CLKS 0x0E 3792 #define V_00913C_X_DELAY_12_CLKS 0x0F 3793 #define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4) 3794 #define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1) 3795 #define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF 3796 #define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6) 3797 #define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1) 3798 #define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF 3799 #define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7) 3800 #define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1) 3801 #define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F 3802 #define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16) 3803 #define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF) 3804 #define C_00913C_PC_LIMIT_SIZE 0x0000FFFF 3805 #define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C 3806 #define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0) 3807 #define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F) 3808 #define C_00936C_TYPE_A 0xFFFFFFF0 3809 #define S_00936C_VGPR_A(x) (((x) & 0x07) << 4) 3810 #define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07) 3811 #define C_00936C_VGPR_A 0xFFFFFF8F 3812 #define S_00936C_SGPR_A(x) (((x) & 0x07) << 7) 3813 #define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07) 3814 #define C_00936C_SGPR_A 0xFFFFFC7F 3815 #define S_00936C_LDS_A(x) (((x) & 0x07) << 10) 3816 #define G_00936C_LDS_A(x) (((x) >> 10) & 0x07) 3817 #define C_00936C_LDS_A 0xFFFFE3FF 3818 #define S_00936C_WAVES_A(x) (((x) & 0x03) << 13) 3819 #define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03) 3820 #define C_00936C_WAVES_A 0xFFFF9FFF 3821 #define S_00936C_EN_A(x) (((x) & 0x1) << 15) 3822 #define G_00936C_EN_A(x) (((x) >> 15) & 0x1) 3823 #define C_00936C_EN_A 0xFFFF7FFF 3824 #define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16) 3825 #define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F) 3826 #define C_00936C_TYPE_B 0xFFF0FFFF 3827 #define S_00936C_VGPR_B(x) (((x) & 0x07) << 20) 3828 #define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07) 3829 #define C_00936C_VGPR_B 0xFF8FFFFF 3830 #define S_00936C_SGPR_B(x) (((x) & 0x07) << 23) 3831 #define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07) 3832 #define C_00936C_SGPR_B 0xFC7FFFFF 3833 #define S_00936C_LDS_B(x) (((x) & 0x07) << 26) 3834 #define G_00936C_LDS_B(x) (((x) >> 26) & 0x07) 3835 #define C_00936C_LDS_B 0xE3FFFFFF 3836 #define S_00936C_WAVES_B(x) (((x) & 0x03) << 29) 3837 #define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03) 3838 #define C_00936C_WAVES_B 0x9FFFFFFF 3839 #define S_00936C_EN_B(x) (((x) & 0x1) << 31) 3840 #define G_00936C_EN_B(x) (((x) >> 31) & 0x1) 3841 #define C_00936C_EN_B 0x7FFFFFFF 3842 #define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C 3843 #define R_009858_DB_SUBTILE_CONTROL 0x009858 3844 #define S_009858_MSAA1_X(x) (((x) & 0x03) << 0) 3845 #define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03) 3846 #define C_009858_MSAA1_X 0xFFFFFFFC 3847 #define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2) 3848 #define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03) 3849 #define C_009858_MSAA1_Y 0xFFFFFFF3 3850 #define S_009858_MSAA2_X(x) (((x) & 0x03) << 4) 3851 #define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03) 3852 #define C_009858_MSAA2_X 0xFFFFFFCF 3853 #define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6) 3854 #define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03) 3855 #define C_009858_MSAA2_Y 0xFFFFFF3F 3856 #define S_009858_MSAA4_X(x) (((x) & 0x03) << 8) 3857 #define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03) 3858 #define C_009858_MSAA4_X 0xFFFFFCFF 3859 #define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10) 3860 #define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03) 3861 #define C_009858_MSAA4_Y 0xFFFFF3FF 3862 #define S_009858_MSAA8_X(x) (((x) & 0x03) << 12) 3863 #define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03) 3864 #define C_009858_MSAA8_X 0xFFFFCFFF 3865 #define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14) 3866 #define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03) 3867 #define C_009858_MSAA8_Y 0xFFFF3FFF 3868 #define S_009858_MSAA16_X(x) (((x) & 0x03) << 16) 3869 #define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03) 3870 #define C_009858_MSAA16_X 0xFFFCFFFF 3871 #define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18) 3872 #define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03) 3873 #define C_009858_MSAA16_Y 0xFFF3FFFF 3874 #define R_009910_GB_TILE_MODE0 0x009910 3875 #define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0) 3876 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03) 3877 #define C_009910_MICRO_TILE_MODE 0xFFFFFFFC 3878 #define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00 3879 #define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01 3880 #define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02 3881 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03 3882 #define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2) 3883 #define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F) 3884 #define C_009910_ARRAY_MODE 0xFFFFFFC3 3885 #define V_009910_ARRAY_LINEAR_GENERAL 0x00 3886 #define V_009910_ARRAY_LINEAR_ALIGNED 0x01 3887 #define V_009910_ARRAY_1D_TILED_THIN1 0x02 3888 #define V_009910_ARRAY_1D_TILED_THICK 0x03 3889 #define V_009910_ARRAY_2D_TILED_THIN1 0x04 3890 #define V_009910_ARRAY_2D_TILED_THICK 0x07 3891 #define V_009910_ARRAY_2D_TILED_XTHICK 0x08 3892 #define V_009910_ARRAY_3D_TILED_THIN1 0x0C 3893 #define V_009910_ARRAY_3D_TILED_THICK 0x0D 3894 #define V_009910_ARRAY_3D_TILED_XTHICK 0x0E 3895 #define V_009910_ARRAY_POWER_SAVE 0x0F 3896 #define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6) 3897 #define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F) 3898 #define C_009910_PIPE_CONFIG 0xFFFFF83F 3899 #define V_009910_ADDR_SURF_P2 0x00 3900 #define V_009910_ADDR_SURF_P2_RESERVED0 0x01 3901 #define V_009910_ADDR_SURF_P2_RESERVED1 0x02 3902 #define V_009910_ADDR_SURF_P2_RESERVED2 0x03 3903 #define V_009910_X_ADDR_SURF_P4_8X16 0x04 3904 #define V_009910_X_ADDR_SURF_P4_16X16 0x05 3905 #define V_009910_X_ADDR_SURF_P4_16X32 0x06 3906 #define V_009910_X_ADDR_SURF_P4_32X32 0x07 3907 #define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08 3908 #define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09 3909 #define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A 3910 #define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B 3911 #define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C 3912 #define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D 3913 #define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E 3914 #define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11) 3915 #define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07) 3916 #define C_009910_TILE_SPLIT 0xFFFFC7FF 3917 #define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00 3918 #define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01 3919 #define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02 3920 #define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03 3921 #define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04 3922 #define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05 3923 #define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06 3924 #define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14) 3925 #define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03) 3926 #define C_009910_BANK_WIDTH 0xFFFF3FFF 3927 #define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00 3928 #define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01 3929 #define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02 3930 #define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03 3931 #define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16) 3932 #define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03) 3933 #define C_009910_BANK_HEIGHT 0xFFFCFFFF 3934 #define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00 3935 #define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01 3936 #define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02 3937 #define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03 3938 #define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18) 3939 #define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03) 3940 #define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF 3941 #define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00 3942 #define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01 3943 #define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02 3944 #define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03 3945 #define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20) 3946 #define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03) 3947 #define C_009910_NUM_BANKS 0xFFCFFFFF 3948 #define V_009910_ADDR_SURF_2_BANK 0x00 3949 #define V_009910_ADDR_SURF_4_BANK 0x01 3950 #define V_009910_ADDR_SURF_8_BANK 0x02 3951 #define V_009910_ADDR_SURF_16_BANK 0x03 3952 #define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020 3953 #define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024 3954 #define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0) 3955 #define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF) 3956 #define C_00B024_MEM_BASE 0xFFFFFF00 3957 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 3958 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 3959 #define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F) 3960 #define C_00B028_VGPRS 0xFFFFFFC0 3961 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 3962 #define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F) 3963 #define C_00B028_SGPRS 0xFFFFFC3F 3964 #define S_00B028_PRIORITY(x) (((x) & 0x03) << 10) 3965 #define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03) 3966 #define C_00B028_PRIORITY 0xFFFFF3FF 3967 #define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12) 3968 #define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 3969 #define C_00B028_FLOAT_MODE 0xFFF00FFF 3970 #define S_00B028_PRIV(x) (((x) & 0x1) << 20) 3971 #define G_00B028_PRIV(x) (((x) >> 20) & 0x1) 3972 #define C_00B028_PRIV 0xFFEFFFFF 3973 #define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21) 3974 #define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1) 3975 #define C_00B028_DX10_CLAMP 0xFFDFFFFF 3976 #define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22) 3977 #define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1) 3978 #define C_00B028_DEBUG_MODE 0xFFBFFFFF 3979 #define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23) 3980 #define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1) 3981 #define C_00B028_IEEE_MODE 0xFF7FFFFF 3982 #define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24) 3983 #define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1) 3984 #define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF 3985 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 3986 #define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0) 3987 #define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 3988 #define C_00B02C_SCRATCH_EN 0xFFFFFFFE 3989 #define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1) 3990 #define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F) 3991 #define C_00B02C_USER_SGPR 0xFFFFFFC1 3992 #define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7) 3993 #define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1) 3994 #define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F 3995 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 3996 #define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF) 3997 #define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF 3998 #define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16) 3999 #define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F) 4000 #define C_00B02C_EXCP_EN 0xFF80FFFF 4001 #define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030 4002 #define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034 4003 #define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038 4004 #define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C 4005 #define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040 4006 #define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044 4007 #define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048 4008 #define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C 4009 #define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050 4010 #define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054 4011 #define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058 4012 #define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C 4013 #define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060 4014 #define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064 4015 #define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068 4016 #define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C 4017 #define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120 4018 #define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124 4019 #define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0) 4020 #define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF) 4021 #define C_00B124_MEM_BASE 0xFFFFFF00 4022 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 4023 #define S_00B128_VGPRS(x) (((x) & 0x3F) << 0) 4024 #define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F) 4025 #define C_00B128_VGPRS 0xFFFFFFC0 4026 #define S_00B128_SGPRS(x) (((x) & 0x0F) << 6) 4027 #define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F) 4028 #define C_00B128_SGPRS 0xFFFFFC3F 4029 #define S_00B128_PRIORITY(x) (((x) & 0x03) << 10) 4030 #define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03) 4031 #define C_00B128_PRIORITY 0xFFFFF3FF 4032 #define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12) 4033 #define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 4034 #define C_00B128_FLOAT_MODE 0xFFF00FFF 4035 #define S_00B128_PRIV(x) (((x) & 0x1) << 20) 4036 #define G_00B128_PRIV(x) (((x) >> 20) & 0x1) 4037 #define C_00B128_PRIV 0xFFEFFFFF 4038 #define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21) 4039 #define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1) 4040 #define C_00B128_DX10_CLAMP 0xFFDFFFFF 4041 #define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22) 4042 #define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1) 4043 #define C_00B128_DEBUG_MODE 0xFFBFFFFF 4044 #define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23) 4045 #define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1) 4046 #define C_00B128_IEEE_MODE 0xFF7FFFFF 4047 #define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) 4048 #define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) 4049 #define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF 4050 #define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) 4051 #define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) 4052 #define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF 4053 #define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C 4054 #define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0) 4055 #define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 4056 #define C_00B12C_SCRATCH_EN 0xFFFFFFFE 4057 #define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1) 4058 #define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F) 4059 #define C_00B12C_USER_SGPR 0xFFFFFFC1 4060 #define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7) 4061 #define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1) 4062 #define C_00B12C_OC_LDS_EN 0xFFFFFF7F 4063 #define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8) 4064 #define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1) 4065 #define C_00B12C_SO_BASE0_EN 0xFFFFFEFF 4066 #define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9) 4067 #define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1) 4068 #define C_00B12C_SO_BASE1_EN 0xFFFFFDFF 4069 #define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10) 4070 #define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1) 4071 #define C_00B12C_SO_BASE2_EN 0xFFFFFBFF 4072 #define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11) 4073 #define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1) 4074 #define C_00B12C_SO_BASE3_EN 0xFFFFF7FF 4075 #define S_00B12C_SO_EN(x) (((x) & 0x1) << 12) 4076 #define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1) 4077 #define C_00B12C_SO_EN 0xFFFFEFFF 4078 #define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13) 4079 #define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F) 4080 #define C_00B12C_EXCP_EN 0xFFF01FFF 4081 #define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130 4082 #define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134 4083 #define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138 4084 #define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C 4085 #define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140 4086 #define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144 4087 #define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148 4088 #define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C 4089 #define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150 4090 #define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154 4091 #define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158 4092 #define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C 4093 #define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160 4094 #define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164 4095 #define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168 4096 #define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C 4097 #define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220 4098 #define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224 4099 #define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0) 4100 #define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF) 4101 #define C_00B224_MEM_BASE 0xFFFFFF00 4102 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 4103 #define S_00B228_VGPRS(x) (((x) & 0x3F) << 0) 4104 #define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F) 4105 #define C_00B228_VGPRS 0xFFFFFFC0 4106 #define S_00B228_SGPRS(x) (((x) & 0x0F) << 6) 4107 #define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F) 4108 #define C_00B228_SGPRS 0xFFFFFC3F 4109 #define S_00B228_PRIORITY(x) (((x) & 0x03) << 10) 4110 #define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03) 4111 #define C_00B228_PRIORITY 0xFFFFF3FF 4112 #define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12) 4113 #define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 4114 #define C_00B228_FLOAT_MODE 0xFFF00FFF 4115 #define S_00B228_PRIV(x) (((x) & 0x1) << 20) 4116 #define G_00B228_PRIV(x) (((x) >> 20) & 0x1) 4117 #define C_00B228_PRIV 0xFFEFFFFF 4118 #define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21) 4119 #define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1) 4120 #define C_00B228_DX10_CLAMP 0xFFDFFFFF 4121 #define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22) 4122 #define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1) 4123 #define C_00B228_DEBUG_MODE 0xFFBFFFFF 4124 #define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23) 4125 #define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1) 4126 #define C_00B228_IEEE_MODE 0xFF7FFFFF 4127 #define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24) 4128 #define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1) 4129 #define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF 4130 #define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C 4131 #define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0) 4132 #define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 4133 #define C_00B22C_SCRATCH_EN 0xFFFFFFFE 4134 #define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1) 4135 #define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F) 4136 #define C_00B22C_USER_SGPR 0xFFFFFFC1 4137 #define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7) 4138 #define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F) 4139 #define C_00B22C_EXCP_EN 0xFFFFC07F 4140 #define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230 4141 #define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320 4142 #define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324 4143 #define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0) 4144 #define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF) 4145 #define C_00B324_MEM_BASE 0xFFFFFF00 4146 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 4147 #define S_00B328_VGPRS(x) (((x) & 0x3F) << 0) 4148 #define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F) 4149 #define C_00B328_VGPRS 0xFFFFFFC0 4150 #define S_00B328_SGPRS(x) (((x) & 0x0F) << 6) 4151 #define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F) 4152 #define C_00B328_SGPRS 0xFFFFFC3F 4153 #define S_00B328_PRIORITY(x) (((x) & 0x03) << 10) 4154 #define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03) 4155 #define C_00B328_PRIORITY 0xFFFFF3FF 4156 #define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12) 4157 #define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 4158 #define C_00B328_FLOAT_MODE 0xFFF00FFF 4159 #define S_00B328_PRIV(x) (((x) & 0x1) << 20) 4160 #define G_00B328_PRIV(x) (((x) >> 20) & 0x1) 4161 #define C_00B328_PRIV 0xFFEFFFFF 4162 #define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21) 4163 #define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1) 4164 #define C_00B328_DX10_CLAMP 0xFFDFFFFF 4165 #define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22) 4166 #define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1) 4167 #define C_00B328_DEBUG_MODE 0xFFBFFFFF 4168 #define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23) 4169 #define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1) 4170 #define C_00B328_IEEE_MODE 0xFF7FFFFF 4171 #define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) 4172 #define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) 4173 #define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF 4174 #define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) 4175 #define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) 4176 #define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF 4177 #define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C 4178 #define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0) 4179 #define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 4180 #define C_00B32C_SCRATCH_EN 0xFFFFFFFE 4181 #define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1) 4182 #define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F) 4183 #define C_00B32C_USER_SGPR 0xFFFFFFC1 4184 #define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7) 4185 #define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1) 4186 #define C_00B32C_OC_LDS_EN 0xFFFFFF7F 4187 #define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8) 4188 #define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F) 4189 #define C_00B32C_EXCP_EN 0xFFFF80FF 4190 #define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330 4191 #define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420 4192 #define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424 4193 #define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0) 4194 #define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF) 4195 #define C_00B424_MEM_BASE 0xFFFFFF00 4196 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 4197 #define S_00B428_VGPRS(x) (((x) & 0x3F) << 0) 4198 #define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F) 4199 #define C_00B428_VGPRS 0xFFFFFFC0 4200 #define S_00B428_SGPRS(x) (((x) & 0x0F) << 6) 4201 #define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F) 4202 #define C_00B428_SGPRS 0xFFFFFC3F 4203 #define S_00B428_PRIORITY(x) (((x) & 0x03) << 10) 4204 #define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03) 4205 #define C_00B428_PRIORITY 0xFFFFF3FF 4206 #define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12) 4207 #define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 4208 #define C_00B428_FLOAT_MODE 0xFFF00FFF 4209 #define S_00B428_PRIV(x) (((x) & 0x1) << 20) 4210 #define G_00B428_PRIV(x) (((x) >> 20) & 0x1) 4211 #define C_00B428_PRIV 0xFFEFFFFF 4212 #define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21) 4213 #define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1) 4214 #define C_00B428_DX10_CLAMP 0xFFDFFFFF 4215 #define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22) 4216 #define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1) 4217 #define C_00B428_DEBUG_MODE 0xFFBFFFFF 4218 #define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23) 4219 #define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1) 4220 #define C_00B428_IEEE_MODE 0xFF7FFFFF 4221 #define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C 4222 #define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0) 4223 #define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 4224 #define C_00B42C_SCRATCH_EN 0xFFFFFFFE 4225 #define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1) 4226 #define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F) 4227 #define C_00B42C_USER_SGPR 0xFFFFFFC1 4228 #define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7) 4229 #define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1) 4230 #define C_00B42C_OC_LDS_EN 0xFFFFFF7F 4231 #define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8) 4232 #define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1) 4233 #define C_00B42C_TG_SIZE_EN 0xFFFFFEFF 4234 #define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9) 4235 #define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F) 4236 #define C_00B42C_EXCP_EN 0xFFFF01FF 4237 #define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430 4238 #define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520 4239 #define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524 4240 #define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0) 4241 #define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF) 4242 #define C_00B524_MEM_BASE 0xFFFFFF00 4243 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 4244 #define S_00B528_VGPRS(x) (((x) & 0x3F) << 0) 4245 #define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F) 4246 #define C_00B528_VGPRS 0xFFFFFFC0 4247 #define S_00B528_SGPRS(x) (((x) & 0x0F) << 6) 4248 #define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F) 4249 #define C_00B528_SGPRS 0xFFFFFC3F 4250 #define S_00B528_PRIORITY(x) (((x) & 0x03) << 10) 4251 #define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03) 4252 #define C_00B528_PRIORITY 0xFFFFF3FF 4253 #define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12) 4254 #define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 4255 #define C_00B528_FLOAT_MODE 0xFFF00FFF 4256 #define S_00B528_PRIV(x) (((x) & 0x1) << 20) 4257 #define G_00B528_PRIV(x) (((x) >> 20) & 0x1) 4258 #define C_00B528_PRIV 0xFFEFFFFF 4259 #define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21) 4260 #define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1) 4261 #define C_00B528_DX10_CLAMP 0xFFDFFFFF 4262 #define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22) 4263 #define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1) 4264 #define C_00B528_DEBUG_MODE 0xFFBFFFFF 4265 #define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23) 4266 #define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1) 4267 #define C_00B528_IEEE_MODE 0xFF7FFFFF 4268 #define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) 4269 #define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) 4270 #define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF 4271 #define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C 4272 #define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0) 4273 #define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 4274 #define C_00B52C_SCRATCH_EN 0xFFFFFFFE 4275 #define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1) 4276 #define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F) 4277 #define C_00B52C_USER_SGPR 0xFFFFFFC1 4278 #define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7) 4279 #define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF) 4280 #define C_00B52C_LDS_SIZE 0xFFFF007F 4281 #define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16) 4282 #define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F) 4283 #define C_00B52C_EXCP_EN 0xFF80FFFF 4284 #define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530 4285 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 4286 #define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0) 4287 #define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1) 4288 #define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE 4289 #define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1) 4290 #define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1) 4291 #define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD 4292 #define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2) 4293 #define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1) 4294 #define C_00B800_FORCE_START_AT_000 0xFFFFFFFB 4295 #define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3) 4296 #define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1) 4297 #define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7 4298 #define R_00B804_COMPUTE_DIM_X 0x00B804 4299 #define R_00B808_COMPUTE_DIM_Y 0x00B808 4300 #define R_00B80C_COMPUTE_DIM_Z 0x00B80C 4301 #define R_00B810_COMPUTE_START_X 0x00B810 4302 #define R_00B814_COMPUTE_START_Y 0x00B814 4303 #define R_00B818_COMPUTE_START_Z 0x00B818 4304 #define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C 4305 #define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) 4306 #define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) 4307 #define C_00B81C_NUM_THREAD_FULL 0xFFFF0000 4308 #define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) 4309 #define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) 4310 #define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF 4311 #define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820 4312 #define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) 4313 #define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) 4314 #define C_00B820_NUM_THREAD_FULL 0xFFFF0000 4315 #define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) 4316 #define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) 4317 #define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF 4318 #define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824 4319 #define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) 4320 #define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) 4321 #define C_00B824_NUM_THREAD_FULL 0xFFFF0000 4322 #define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) 4323 #define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) 4324 #define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF 4325 #define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C 4326 #define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) 4327 #define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) 4328 #define C_00B82C_MAX_WAVE_ID 0xFFFFF000 4329 #define R_00B830_COMPUTE_PGM_LO 0x00B830 4330 #define R_00B834_COMPUTE_PGM_HI 0x00B834 4331 #define S_00B834_DATA(x) (((x) & 0xFF) << 0) 4332 #define G_00B834_DATA(x) (((x) >> 0) & 0xFF) 4333 #define C_00B834_DATA 0xFFFFFF00 4334 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 4335 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 4336 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 4337 #define C_00B848_VGPRS 0xFFFFFFC0 4338 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 4339 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 4340 #define C_00B848_SGPRS 0xFFFFFC3F 4341 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 4342 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 4343 #define C_00B848_PRIORITY 0xFFFFF3FF 4344 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 4345 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 4346 #define C_00B848_FLOAT_MODE 0xFFF00FFF 4347 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 4348 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 4349 #define C_00B848_PRIV 0xFFEFFFFF 4350 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 4351 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 4352 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 4353 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 4354 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 4355 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 4356 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 4357 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 4358 #define C_00B848_IEEE_MODE 0xFF7FFFFF 4359 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 4360 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 4361 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 4362 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 4363 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 4364 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 4365 #define C_00B84C_USER_SGPR 0xFFFFFFC1 4366 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 4367 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 4368 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 4369 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 4370 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 4371 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 4372 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 4373 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 4374 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 4375 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 4376 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 4377 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 4378 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 4379 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 4380 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 4381 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 4382 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 4383 #define C_00B84C_LDS_SIZE 0xFF007FFF 4384 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 4385 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 4386 #define C_00B84C_EXCP_EN 0x80FFFFFF 4387 #define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854 4388 #define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0) 4389 #define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F) 4390 #define C_00B854_WAVES_PER_SH 0xFFFFFFC0 4391 #define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12) 4392 #define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F) 4393 #define C_00B854_TG_PER_CU 0xFFFF0FFF 4394 #define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16) 4395 #define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F) 4396 #define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF 4397 #define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22) 4398 #define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1) 4399 #define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF 4400 #define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858 4401 #define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) 4402 #define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) 4403 #define C_00B858_SH0_CU_EN 0xFFFF0000 4404 #define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) 4405 #define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) 4406 #define C_00B858_SH1_CU_EN 0x0000FFFF 4407 #define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C 4408 #define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) 4409 #define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) 4410 #define C_00B85C_SH0_CU_EN 0xFFFF0000 4411 #define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) 4412 #define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) 4413 #define C_00B85C_SH1_CU_EN 0x0000FFFF 4414 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 4415 #define S_00B860_WAVES(x) (((x) & 0xFFF) << 0) 4416 #define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF) 4417 #define C_00B860_WAVES 0xFFFFF000 4418 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 4419 #define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF) 4420 #define C_00B860_WAVESIZE 0xFE000FFF 4421 #define R_00B900_COMPUTE_USER_DATA_0 0x00B900 4422 #define R_028000_DB_RENDER_CONTROL 0x028000 4423 #define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0) 4424 #define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1) 4425 #define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE 4426 #define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1) 4427 #define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1) 4428 #define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD 4429 #define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2) 4430 #define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1) 4431 #define C_028000_DEPTH_COPY 0xFFFFFFFB 4432 #define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3) 4433 #define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1) 4434 #define C_028000_STENCIL_COPY 0xFFFFFFF7 4435 #define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4) 4436 #define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1) 4437 #define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF 4438 #define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) 4439 #define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1) 4440 #define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF 4441 #define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) 4442 #define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1) 4443 #define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF 4444 #define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7) 4445 #define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1) 4446 #define C_028000_COPY_CENTROID 0xFFFFFF7F 4447 #define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8) 4448 #define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F) 4449 #define C_028000_COPY_SAMPLE 0xFFFFF0FF 4450 #define R_028004_DB_COUNT_CONTROL 0x028004 4451 #define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0) 4452 #define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1) 4453 #define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE 4454 #define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1) 4455 #define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1) 4456 #define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD 4457 #define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4) 4458 #define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07) 4459 #define C_028004_SAMPLE_RATE 0xFFFFFF8F 4460 #define R_028008_DB_DEPTH_VIEW 0x028008 4461 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 4462 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 4463 #define C_028008_SLICE_START 0xFFFFF800 4464 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 4465 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 4466 #define C_028008_SLICE_MAX 0xFF001FFF 4467 #define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24) 4468 #define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1) 4469 #define C_028008_Z_READ_ONLY 0xFEFFFFFF 4470 #define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25) 4471 #define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1) 4472 #define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF 4473 #define R_02800C_DB_RENDER_OVERRIDE 0x02800C 4474 #define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0) 4475 #define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03) 4476 #define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC 4477 #define V_02800C_FORCE_OFF 0x00 4478 #define V_02800C_FORCE_ENABLE 0x01 4479 #define V_02800C_FORCE_DISABLE 0x02 4480 #define V_02800C_FORCE_RESERVED 0x03 4481 #define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2) 4482 #define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03) 4483 #define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3 4484 #define V_02800C_FORCE_OFF 0x00 4485 #define V_02800C_FORCE_ENABLE 0x01 4486 #define V_02800C_FORCE_DISABLE 0x02 4487 #define V_02800C_FORCE_RESERVED 0x03 4488 #define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4) 4489 #define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03) 4490 #define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF 4491 #define V_02800C_FORCE_OFF 0x00 4492 #define V_02800C_FORCE_ENABLE 0x01 4493 #define V_02800C_FORCE_DISABLE 0x02 4494 #define V_02800C_FORCE_RESERVED 0x03 4495 #define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) 4496 #define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) 4497 #define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF 4498 #define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) 4499 #define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) 4500 #define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F 4501 #define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) 4502 #define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) 4503 #define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF 4504 #define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) 4505 #define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) 4506 #define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF 4507 #define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) 4508 #define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) 4509 #define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF 4510 #define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11) 4511 #define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1) 4512 #define C_02800C_FORCE_Z_READ 0xFFFFF7FF 4513 #define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) 4514 #define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) 4515 #define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF 4516 #define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13) 4517 #define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03) 4518 #define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF 4519 #define V_02800C_FORCE_OFF 0x00 4520 #define V_02800C_FORCE_ENABLE 0x01 4521 #define V_02800C_FORCE_DISABLE 0x02 4522 #define V_02800C_FORCE_RESERVED 0x03 4523 #define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) 4524 #define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) 4525 #define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF 4526 #define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) 4527 #define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) 4528 #define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF 4529 #define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) 4530 #define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) 4531 #define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF 4532 #define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18) 4533 #define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1) 4534 #define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF 4535 #define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19) 4536 #define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03) 4537 #define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF 4538 #define V_02800C_FORCE_SUMM_OFF 0x00 4539 #define V_02800C_FORCE_SUMM_MINZ 0x01 4540 #define V_02800C_FORCE_SUMM_MAXZ 0x02 4541 #define V_02800C_FORCE_SUMM_BOTH 0x03 4542 #define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21) 4543 #define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F) 4544 #define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF 4545 #define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26) 4546 #define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1) 4547 #define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF 4548 #define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27) 4549 #define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1) 4550 #define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF 4551 #define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28) 4552 #define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1) 4553 #define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF 4554 #define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29) 4555 #define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1) 4556 #define C_02800C_FORCE_Z_VALID 0xDFFFFFFF 4557 #define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30) 4558 #define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1) 4559 #define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF 4560 #define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31) 4561 #define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1) 4562 #define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF 4563 #define R_028010_DB_RENDER_OVERRIDE2 0x028010 4564 #define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0) 4565 #define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03) 4566 #define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC 4567 #define V_028010_PSLC_AUTO 0x00 4568 #define V_028010_PSLC_ON_HANG_ONLY 0x01 4569 #define V_028010_PSLC_ASAP 0x02 4570 #define V_028010_PSLC_COUNTDOWN 0x03 4571 #define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2) 4572 #define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07) 4573 #define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3 4574 #define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO(x) (((x) & 0x1) << 5) 4575 #define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO(x) (((x) >> 5) & 0x1) 4576 #define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO 0xFFFFFFDF 4577 #define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6) 4578 #define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1) 4579 #define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF 4580 #define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7) 4581 #define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1) 4582 #define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F 4583 #define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8) 4584 #define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1) 4585 #define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF 4586 #define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9) 4587 #define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1) 4588 #define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF 4589 #define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10) 4590 #define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1) 4591 #define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF 4592 #define R_028014_DB_HTILE_DATA_BASE 0x028014 4593 #define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020 4594 #define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024 4595 #define R_028028_DB_STENCIL_CLEAR 0x028028 4596 #define S_028028_CLEAR(x) (((x) & 0xFF) << 0) 4597 #define G_028028_CLEAR(x) (((x) >> 0) & 0xFF) 4598 #define C_028028_CLEAR 0xFFFFFF00 4599 #define R_02802C_DB_DEPTH_CLEAR 0x02802C 4600 #define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 4601 #define S_028030_TL_X(x) (((x) & 0xFFFF) << 0) 4602 #define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF) 4603 #define C_028030_TL_X 0xFFFF0000 4604 #define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16) 4605 #define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF) 4606 #define C_028030_TL_Y 0x0000FFFF 4607 #define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 4608 #define S_028034_BR_X(x) (((x) & 0xFFFF) << 0) 4609 #define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF) 4610 #define C_028034_BR_X 0xFFFF0000 4611 #define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16) 4612 #define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF) 4613 #define C_028034_BR_Y 0x0000FFFF 4614 #define R_02803C_DB_DEPTH_INFO 0x02803C 4615 #define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0) 4616 #define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F) 4617 #define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0 4618 #define R_028040_DB_Z_INFO 0x028040 4619 #define S_028040_FORMAT(x) (((x) & 0x03) << 0) 4620 #define G_028040_FORMAT(x) (((x) >> 0) & 0x03) 4621 #define C_028040_FORMAT 0xFFFFFFFC 4622 #define V_028040_Z_INVALID 0x00 4623 #define V_028040_Z_16 0x01 4624 #define V_028040_Z_24 0x02 /* deprecated */ 4625 #define V_028040_Z_32_FLOAT 0x03 4626 #define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2) 4627 #define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03) 4628 #define C_028040_NUM_SAMPLES 0xFFFFFFF3 4629 #define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) 4630 #define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) 4631 #define C_028040_TILE_MODE_INDEX 0xFF8FFFFF 4632 #define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) 4633 #define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) 4634 #define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF 4635 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 4636 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 4637 #define C_028040_READ_SIZE 0xEFFFFFFF 4638 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 4639 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 4640 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 4641 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 4642 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 4643 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 4644 #define R_028044_DB_STENCIL_INFO 0x028044 4645 #define S_028044_FORMAT(x) (((x) & 0x1) << 0) 4646 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 4647 #define C_028044_FORMAT 0xFFFFFFFE 4648 #define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) 4649 #define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) 4650 #define C_028044_TILE_MODE_INDEX 0xFF8FFFFF 4651 #define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) 4652 #define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) 4653 #define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF 4654 #define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29) 4655 #define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1) 4656 #define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF 4657 #define R_028048_DB_Z_READ_BASE 0x028048 4658 #define R_02804C_DB_STENCIL_READ_BASE 0x02804C 4659 #define R_028050_DB_Z_WRITE_BASE 0x028050 4660 #define R_028054_DB_STENCIL_WRITE_BASE 0x028054 4661 #define R_028058_DB_DEPTH_SIZE 0x028058 4662 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 4663 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 4664 #define C_028058_PITCH_TILE_MAX 0xFFFFF800 4665 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 4666 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 4667 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 4668 #define R_02805C_DB_DEPTH_SLICE 0x02805C 4669 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 4670 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 4671 #define C_02805C_SLICE_TILE_MAX 0xFFC00000 4672 #define R_028080_TA_BC_BASE_ADDR 0x028080 4673 #define R_028200_PA_SC_WINDOW_OFFSET 0x028200 4674 #define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0) 4675 #define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF) 4676 #define C_028200_WINDOW_X_OFFSET 0xFFFF0000 4677 #define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16) 4678 #define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF) 4679 #define C_028200_WINDOW_Y_OFFSET 0x0000FFFF 4680 #define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 4681 #define S_028204_TL_X(x) (((x) & 0x7FFF) << 0) 4682 #define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF) 4683 #define C_028204_TL_X 0xFFFF8000 4684 #define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16) 4685 #define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF) 4686 #define C_028204_TL_Y 0x8000FFFF 4687 #define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) 4688 #define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) 4689 #define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF 4690 #define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 4691 #define S_028208_BR_X(x) (((x) & 0x7FFF) << 0) 4692 #define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF) 4693 #define C_028208_BR_X 0xFFFF8000 4694 #define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16) 4695 #define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF) 4696 #define C_028208_BR_Y 0x8000FFFF 4697 #define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C 4698 #define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0) 4699 #define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF) 4700 #define C_02820C_CLIP_RULE 0xFFFF0000 4701 #define R_028210_PA_SC_CLIPRECT_0_TL 0x028210 4702 #define S_028210_TL_X(x) (((x) & 0x7FFF) << 0) 4703 #define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF) 4704 #define C_028210_TL_X 0xFFFF8000 4705 #define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16) 4706 #define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF) 4707 #define C_028210_TL_Y 0x8000FFFF 4708 #define R_028214_PA_SC_CLIPRECT_0_BR 0x028214 4709 #define S_028214_BR_X(x) (((x) & 0x7FFF) << 0) 4710 #define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF) 4711 #define C_028214_BR_X 0xFFFF8000 4712 #define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16) 4713 #define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF) 4714 #define C_028214_BR_Y 0x8000FFFF 4715 #define R_028218_PA_SC_CLIPRECT_1_TL 0x028218 4716 #define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C 4717 #define R_028220_PA_SC_CLIPRECT_2_TL 0x028220 4718 #define R_028224_PA_SC_CLIPRECT_2_BR 0x028224 4719 #define R_028228_PA_SC_CLIPRECT_3_TL 0x028228 4720 #define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C 4721 #define R_028230_PA_SC_EDGERULE 0x028230 4722 #define S_028230_ER_TRI(x) (((x) & 0x0F) << 0) 4723 #define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F) 4724 #define C_028230_ER_TRI 0xFFFFFFF0 4725 #define S_028230_ER_POINT(x) (((x) & 0x0F) << 4) 4726 #define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F) 4727 #define C_028230_ER_POINT 0xFFFFFF0F 4728 #define S_028230_ER_RECT(x) (((x) & 0x0F) << 8) 4729 #define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F) 4730 #define C_028230_ER_RECT 0xFFFFF0FF 4731 #define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12) 4732 #define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F) 4733 #define C_028230_ER_LINE_LR 0xFFFC0FFF 4734 #define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18) 4735 #define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F) 4736 #define C_028230_ER_LINE_RL 0xFF03FFFF 4737 #define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24) 4738 #define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F) 4739 #define C_028230_ER_LINE_TB 0xF0FFFFFF 4740 #define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28) 4741 #define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F) 4742 #define C_028230_ER_LINE_BT 0x0FFFFFFF 4743 #define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234 4744 #define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0) 4745 #define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF) 4746 #define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00 4747 #define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16) 4748 #define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF) 4749 #define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF 4750 #define R_028238_CB_TARGET_MASK 0x028238 4751 #define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0) 4752 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F) 4753 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 4754 #define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4) 4755 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F) 4756 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 4757 #define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8) 4758 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F) 4759 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 4760 #define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12) 4761 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F) 4762 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 4763 #define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16) 4764 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F) 4765 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 4766 #define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20) 4767 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F) 4768 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 4769 #define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24) 4770 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F) 4771 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 4772 #define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28) 4773 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F) 4774 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 4775 #define R_02823C_CB_SHADER_MASK 0x02823C 4776 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0) 4777 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F) 4778 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 4779 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4) 4780 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F) 4781 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 4782 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8) 4783 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F) 4784 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 4785 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12) 4786 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F) 4787 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 4788 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16) 4789 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F) 4790 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 4791 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20) 4792 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F) 4793 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 4794 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24) 4795 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F) 4796 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 4797 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28) 4798 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F) 4799 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 4800 #define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 4801 #define S_028240_TL_X(x) (((x) & 0x7FFF) << 0) 4802 #define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF) 4803 #define C_028240_TL_X 0xFFFF8000 4804 #define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16) 4805 #define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF) 4806 #define C_028240_TL_Y 0x8000FFFF 4807 #define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) 4808 #define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) 4809 #define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF 4810 #define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 4811 #define S_028244_BR_X(x) (((x) & 0x7FFF) << 0) 4812 #define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF) 4813 #define C_028244_BR_X 0xFFFF8000 4814 #define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16) 4815 #define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF) 4816 #define C_028244_BR_Y 0x8000FFFF 4817 #define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 4818 #define S_028250_TL_X(x) (((x) & 0x7FFF) << 0) 4819 #define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) 4820 #define C_028250_TL_X 0xFFFF8000 4821 #define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16) 4822 #define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) 4823 #define C_028250_TL_Y 0x8000FFFF 4824 #define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) 4825 #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) 4826 #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF 4827 #define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254 4828 #define S_028254_BR_X(x) (((x) & 0x7FFF) << 0) 4829 #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) 4830 #define C_028254_BR_X 0xFFFF8000 4831 #define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16) 4832 #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) 4833 #define C_028254_BR_Y 0x8000FFFF 4834 #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 4835 #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 4836 #define R_028350_PA_SC_RASTER_CONFIG 0x028350 4837 #define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0) 4838 #define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03) 4839 #define C_028350_RB_MAP_PKR0 0xFFFFFFFC 4840 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 4841 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 4842 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 4843 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 4844 #define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2) 4845 #define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03) 4846 #define C_028350_RB_MAP_PKR1 0xFFFFFFF3 4847 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 4848 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 4849 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 4850 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 4851 #define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4) 4852 #define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03) 4853 #define C_028350_RB_XSEL2 0xFFFFFFCF 4854 #define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00 4855 #define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01 4856 #define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02 4857 #define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03 4858 #define S_028350_RB_XSEL(x) (((x) & 0x1) << 6) 4859 #define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1) 4860 #define C_028350_RB_XSEL 0xFFFFFFBF 4861 #define S_028350_RB_YSEL(x) (((x) & 0x1) << 7) 4862 #define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1) 4863 #define C_028350_RB_YSEL 0xFFFFFF7F 4864 #define S_028350_PKR_MAP(x) (((x) & 0x03) << 8) 4865 #define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03) 4866 #define C_028350_PKR_MAP 0xFFFFFCFF 4867 #define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00 4868 #define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01 4869 #define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02 4870 #define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03 4871 #define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10) 4872 #define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03) 4873 #define C_028350_PKR_XSEL 0xFFFFF3FF 4874 #define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00 4875 #define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01 4876 #define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02 4877 #define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03 4878 #define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12) 4879 #define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03) 4880 #define C_028350_PKR_YSEL 0xFFFFCFFF 4881 #define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00 4882 #define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01 4883 #define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02 4884 #define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03 4885 #define S_028350_SC_MAP(x) (((x) & 0x03) << 16) 4886 #define G_028350_SC_MAP(x) (((x) >> 16) & 0x03) 4887 #define C_028350_SC_MAP 0xFFFCFFFF 4888 #define V_028350_RASTER_CONFIG_SC_MAP_0 0x00 4889 #define V_028350_RASTER_CONFIG_SC_MAP_1 0x01 4890 #define V_028350_RASTER_CONFIG_SC_MAP_2 0x02 4891 #define V_028350_RASTER_CONFIG_SC_MAP_3 0x03 4892 #define S_028350_SC_XSEL(x) (((x) & 0x03) << 18) 4893 #define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03) 4894 #define C_028350_SC_XSEL 0xFFF3FFFF 4895 #define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00 4896 #define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01 4897 #define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02 4898 #define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03 4899 #define S_028350_SC_YSEL(x) (((x) & 0x03) << 20) 4900 #define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03) 4901 #define C_028350_SC_YSEL 0xFFCFFFFF 4902 #define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00 4903 #define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01 4904 #define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02 4905 #define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03 4906 #define S_028350_SE_MAP(x) (((x) & 0x03) << 24) 4907 #define G_028350_SE_MAP(x) (((x) >> 24) & 0x03) 4908 #define C_028350_SE_MAP 0xFCFFFFFF 4909 #define V_028350_RASTER_CONFIG_SE_MAP_0 0x00 4910 #define V_028350_RASTER_CONFIG_SE_MAP_1 0x01 4911 #define V_028350_RASTER_CONFIG_SE_MAP_2 0x02 4912 #define V_028350_RASTER_CONFIG_SE_MAP_3 0x03 4913 #define S_028350_SE_XSEL(x) (((x) & 0x03) << 26) 4914 #define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03) 4915 #define C_028350_SE_XSEL 0xF3FFFFFF 4916 #define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00 4917 #define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01 4918 #define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02 4919 #define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03 4920 #define S_028350_SE_YSEL(x) (((x) & 0x03) << 28) 4921 #define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03) 4922 #define C_028350_SE_YSEL 0xCFFFFFFF 4923 #define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00 4924 #define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01 4925 #define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02 4926 #define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03 4927 #define R_028400_VGT_MAX_VTX_INDX 0x028400 4928 #define R_028404_VGT_MIN_VTX_INDX 0x028404 4929 #define R_028408_VGT_INDX_OFFSET 0x028408 4930 #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C 4931 #define R_028414_CB_BLEND_RED 0x028414 4932 #define R_028418_CB_BLEND_GREEN 0x028418 4933 #define R_02841C_CB_BLEND_BLUE 0x02841C 4934 #define R_028420_CB_BLEND_ALPHA 0x028420 4935 #define R_02842C_DB_STENCIL_CONTROL 0x02842C 4936 #define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0) 4937 #define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F) 4938 #define C_02842C_STENCILFAIL 0xFFFFFFF0 4939 #define V_02842C_STENCIL_KEEP 0x00 4940 #define V_02842C_STENCIL_ZERO 0x01 4941 #define V_02842C_STENCIL_ONES 0x02 4942 #define V_02842C_STENCIL_REPLACE_TEST 0x03 4943 #define V_02842C_STENCIL_REPLACE_OP 0x04 4944 #define V_02842C_STENCIL_ADD_CLAMP 0x05 4945 #define V_02842C_STENCIL_SUB_CLAMP 0x06 4946 #define V_02842C_STENCIL_INVERT 0x07 4947 #define V_02842C_STENCIL_ADD_WRAP 0x08 4948 #define V_02842C_STENCIL_SUB_WRAP 0x09 4949 #define V_02842C_STENCIL_AND 0x0A 4950 #define V_02842C_STENCIL_OR 0x0B 4951 #define V_02842C_STENCIL_XOR 0x0C 4952 #define V_02842C_STENCIL_NAND 0x0D 4953 #define V_02842C_STENCIL_NOR 0x0E 4954 #define V_02842C_STENCIL_XNOR 0x0F 4955 #define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4) 4956 #define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F) 4957 #define C_02842C_STENCILZPASS 0xFFFFFF0F 4958 #define V_02842C_STENCIL_KEEP 0x00 4959 #define V_02842C_STENCIL_ZERO 0x01 4960 #define V_02842C_STENCIL_ONES 0x02 4961 #define V_02842C_STENCIL_REPLACE_TEST 0x03 4962 #define V_02842C_STENCIL_REPLACE_OP 0x04 4963 #define V_02842C_STENCIL_ADD_CLAMP 0x05 4964 #define V_02842C_STENCIL_SUB_CLAMP 0x06 4965 #define V_02842C_STENCIL_INVERT 0x07 4966 #define V_02842C_STENCIL_ADD_WRAP 0x08 4967 #define V_02842C_STENCIL_SUB_WRAP 0x09 4968 #define V_02842C_STENCIL_AND 0x0A 4969 #define V_02842C_STENCIL_OR 0x0B 4970 #define V_02842C_STENCIL_XOR 0x0C 4971 #define V_02842C_STENCIL_NAND 0x0D 4972 #define V_02842C_STENCIL_NOR 0x0E 4973 #define V_02842C_STENCIL_XNOR 0x0F 4974 #define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8) 4975 #define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F) 4976 #define C_02842C_STENCILZFAIL 0xFFFFF0FF 4977 #define V_02842C_STENCIL_KEEP 0x00 4978 #define V_02842C_STENCIL_ZERO 0x01 4979 #define V_02842C_STENCIL_ONES 0x02 4980 #define V_02842C_STENCIL_REPLACE_TEST 0x03 4981 #define V_02842C_STENCIL_REPLACE_OP 0x04 4982 #define V_02842C_STENCIL_ADD_CLAMP 0x05 4983 #define V_02842C_STENCIL_SUB_CLAMP 0x06 4984 #define V_02842C_STENCIL_INVERT 0x07 4985 #define V_02842C_STENCIL_ADD_WRAP 0x08 4986 #define V_02842C_STENCIL_SUB_WRAP 0x09 4987 #define V_02842C_STENCIL_AND 0x0A 4988 #define V_02842C_STENCIL_OR 0x0B 4989 #define V_02842C_STENCIL_XOR 0x0C 4990 #define V_02842C_STENCIL_NAND 0x0D 4991 #define V_02842C_STENCIL_NOR 0x0E 4992 #define V_02842C_STENCIL_XNOR 0x0F 4993 #define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12) 4994 #define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F) 4995 #define C_02842C_STENCILFAIL_BF 0xFFFF0FFF 4996 #define V_02842C_STENCIL_KEEP 0x00 4997 #define V_02842C_STENCIL_ZERO 0x01 4998 #define V_02842C_STENCIL_ONES 0x02 4999 #define V_02842C_STENCIL_REPLACE_TEST 0x03 5000 #define V_02842C_STENCIL_REPLACE_OP 0x04 5001 #define V_02842C_STENCIL_ADD_CLAMP 0x05 5002 #define V_02842C_STENCIL_SUB_CLAMP 0x06 5003 #define V_02842C_STENCIL_INVERT 0x07 5004 #define V_02842C_STENCIL_ADD_WRAP 0x08 5005 #define V_02842C_STENCIL_SUB_WRAP 0x09 5006 #define V_02842C_STENCIL_AND 0x0A 5007 #define V_02842C_STENCIL_OR 0x0B 5008 #define V_02842C_STENCIL_XOR 0x0C 5009 #define V_02842C_STENCIL_NAND 0x0D 5010 #define V_02842C_STENCIL_NOR 0x0E 5011 #define V_02842C_STENCIL_XNOR 0x0F 5012 #define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16) 5013 #define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F) 5014 #define C_02842C_STENCILZPASS_BF 0xFFF0FFFF 5015 #define V_02842C_STENCIL_KEEP 0x00 5016 #define V_02842C_STENCIL_ZERO 0x01 5017 #define V_02842C_STENCIL_ONES 0x02 5018 #define V_02842C_STENCIL_REPLACE_TEST 0x03 5019 #define V_02842C_STENCIL_REPLACE_OP 0x04 5020 #define V_02842C_STENCIL_ADD_CLAMP 0x05 5021 #define V_02842C_STENCIL_SUB_CLAMP 0x06 5022 #define V_02842C_STENCIL_INVERT 0x07 5023 #define V_02842C_STENCIL_ADD_WRAP 0x08 5024 #define V_02842C_STENCIL_SUB_WRAP 0x09 5025 #define V_02842C_STENCIL_AND 0x0A 5026 #define V_02842C_STENCIL_OR 0x0B 5027 #define V_02842C_STENCIL_XOR 0x0C 5028 #define V_02842C_STENCIL_NAND 0x0D 5029 #define V_02842C_STENCIL_NOR 0x0E 5030 #define V_02842C_STENCIL_XNOR 0x0F 5031 #define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20) 5032 #define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F) 5033 #define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF 5034 #define V_02842C_STENCIL_KEEP 0x00 5035 #define V_02842C_STENCIL_ZERO 0x01 5036 #define V_02842C_STENCIL_ONES 0x02 5037 #define V_02842C_STENCIL_REPLACE_TEST 0x03 5038 #define V_02842C_STENCIL_REPLACE_OP 0x04 5039 #define V_02842C_STENCIL_ADD_CLAMP 0x05 5040 #define V_02842C_STENCIL_SUB_CLAMP 0x06 5041 #define V_02842C_STENCIL_INVERT 0x07 5042 #define V_02842C_STENCIL_ADD_WRAP 0x08 5043 #define V_02842C_STENCIL_SUB_WRAP 0x09 5044 #define V_02842C_STENCIL_AND 0x0A 5045 #define V_02842C_STENCIL_OR 0x0B 5046 #define V_02842C_STENCIL_XOR 0x0C 5047 #define V_02842C_STENCIL_NAND 0x0D 5048 #define V_02842C_STENCIL_NOR 0x0E 5049 #define V_02842C_STENCIL_XNOR 0x0F 5050 #define R_028430_DB_STENCILREFMASK 0x028430 5051 #define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0) 5052 #define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF) 5053 #define C_028430_STENCILTESTVAL 0xFFFFFF00 5054 #define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8) 5055 #define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF) 5056 #define C_028430_STENCILMASK 0xFFFF00FF 5057 #define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16) 5058 #define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF) 5059 #define C_028430_STENCILWRITEMASK 0xFF00FFFF 5060 #define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24) 5061 #define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF) 5062 #define C_028430_STENCILOPVAL 0x00FFFFFF 5063 #define R_028434_DB_STENCILREFMASK_BF 0x028434 5064 #define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0) 5065 #define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF) 5066 #define C_028434_STENCILTESTVAL_BF 0xFFFFFF00 5067 #define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8) 5068 #define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF) 5069 #define C_028434_STENCILMASK_BF 0xFFFF00FF 5070 #define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16) 5071 #define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF) 5072 #define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF 5073 #define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24) 5074 #define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF) 5075 #define C_028434_STENCILOPVAL_BF 0x00FFFFFF 5076 #define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C 5077 #define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440 5078 #define R_028444_PA_CL_VPORT_YSCALE_0 0x028444 5079 #define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448 5080 #define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C 5081 #define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450 5082 #define R_0285BC_PA_CL_UCP_0_X 0x0285BC 5083 #define R_0285C0_PA_CL_UCP_0_Y 0x0285C0 5084 #define R_0285C4_PA_CL_UCP_0_Z 0x0285C4 5085 #define R_0285C8_PA_CL_UCP_0_W 0x0285C8 5086 #define R_0285CC_PA_CL_UCP_1_X 0x0285CC 5087 #define R_0285D0_PA_CL_UCP_1_Y 0x0285D0 5088 #define R_0285D4_PA_CL_UCP_1_Z 0x0285D4 5089 #define R_0285D8_PA_CL_UCP_1_W 0x0285D8 5090 #define R_0285DC_PA_CL_UCP_2_X 0x0285DC 5091 #define R_0285E0_PA_CL_UCP_2_Y 0x0285E0 5092 #define R_0285E4_PA_CL_UCP_2_Z 0x0285E4 5093 #define R_0285E8_PA_CL_UCP_2_W 0x0285E8 5094 #define R_0285EC_PA_CL_UCP_3_X 0x0285EC 5095 #define R_0285F0_PA_CL_UCP_3_Y 0x0285F0 5096 #define R_0285F4_PA_CL_UCP_3_Z 0x0285F4 5097 #define R_0285F8_PA_CL_UCP_3_W 0x0285F8 5098 #define R_0285FC_PA_CL_UCP_4_X 0x0285FC 5099 #define R_028600_PA_CL_UCP_4_Y 0x028600 5100 #define R_028604_PA_CL_UCP_4_Z 0x028604 5101 #define R_028608_PA_CL_UCP_4_W 0x028608 5102 #define R_02860C_PA_CL_UCP_5_X 0x02860C 5103 #define R_028610_PA_CL_UCP_5_Y 0x028610 5104 #define R_028614_PA_CL_UCP_5_Z 0x028614 5105 #define R_028618_PA_CL_UCP_5_W 0x028618 5106 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 5107 #define S_028644_OFFSET(x) (((x) & 0x3F) << 0) 5108 #define G_028644_OFFSET(x) (((x) >> 0) & 0x3F) 5109 #define C_028644_OFFSET 0xFFFFFFC0 5110 #define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8) 5111 #define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03) 5112 #define C_028644_DEFAULT_VAL 0xFFFFFCFF 5113 #define V_028644_X_0_0F 0x00 5114 #define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10) 5115 #define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1) 5116 #define C_028644_FLAT_SHADE 0xFFFFFBFF 5117 #define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13) 5118 #define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F) 5119 #define C_028644_CYL_WRAP 0xFFFE1FFF 5120 #define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17) 5121 #define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1) 5122 #define C_028644_PT_SPRITE_TEX 0xFFFDFFFF 5123 #define R_028648_SPI_PS_INPUT_CNTL_1 0x028648 5124 #define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C 5125 #define R_028650_SPI_PS_INPUT_CNTL_3 0x028650 5126 #define R_028654_SPI_PS_INPUT_CNTL_4 0x028654 5127 #define R_028658_SPI_PS_INPUT_CNTL_5 0x028658 5128 #define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C 5129 #define R_028660_SPI_PS_INPUT_CNTL_7 0x028660 5130 #define R_028664_SPI_PS_INPUT_CNTL_8 0x028664 5131 #define R_028668_SPI_PS_INPUT_CNTL_9 0x028668 5132 #define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C 5133 #define R_028670_SPI_PS_INPUT_CNTL_11 0x028670 5134 #define R_028674_SPI_PS_INPUT_CNTL_12 0x028674 5135 #define R_028678_SPI_PS_INPUT_CNTL_13 0x028678 5136 #define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C 5137 #define R_028680_SPI_PS_INPUT_CNTL_15 0x028680 5138 #define R_028684_SPI_PS_INPUT_CNTL_16 0x028684 5139 #define R_028688_SPI_PS_INPUT_CNTL_17 0x028688 5140 #define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C 5141 #define R_028690_SPI_PS_INPUT_CNTL_19 0x028690 5142 #define R_028694_SPI_PS_INPUT_CNTL_20 0x028694 5143 #define R_028698_SPI_PS_INPUT_CNTL_21 0x028698 5144 #define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C 5145 #define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0 5146 #define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4 5147 #define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8 5148 #define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC 5149 #define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0 5150 #define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4 5151 #define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8 5152 #define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC 5153 #define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0 5154 #define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 5155 #define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) 5156 #define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) 5157 #define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 5158 #define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6) 5159 #define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1) 5160 #define C_0286C4_VS_HALF_PACK 0xFFFFFFBF 5161 #define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7) 5162 #define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1) 5163 #define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F 5164 #define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8) 5165 #define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F) 5166 #define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF 5167 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 5168 #define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) 5169 #define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) 5170 #define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE 5171 #define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) 5172 #define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) 5173 #define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD 5174 #define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) 5175 #define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) 5176 #define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB 5177 #define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) 5178 #define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) 5179 #define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 5180 #define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) 5181 #define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) 5182 #define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF 5183 #define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) 5184 #define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) 5185 #define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF 5186 #define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) 5187 #define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) 5188 #define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF 5189 #define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) 5190 #define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) 5191 #define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F 5192 #define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) 5193 #define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) 5194 #define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF 5195 #define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) 5196 #define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) 5197 #define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF 5198 #define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) 5199 #define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) 5200 #define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF 5201 #define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) 5202 #define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) 5203 #define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF 5204 #define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) 5205 #define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) 5206 #define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF 5207 #define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13) 5208 #define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) 5209 #define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF 5210 #define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) 5211 #define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) 5212 #define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF 5213 #define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) 5214 #define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) 5215 #define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF 5216 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 5217 #define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) 5218 #define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) 5219 #define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE 5220 #define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) 5221 #define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) 5222 #define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD 5223 #define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) 5224 #define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) 5225 #define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB 5226 #define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) 5227 #define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) 5228 #define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 5229 #define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) 5230 #define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) 5231 #define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF 5232 #define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) 5233 #define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) 5234 #define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF 5235 #define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) 5236 #define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) 5237 #define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF 5238 #define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) 5239 #define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) 5240 #define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F 5241 #define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) 5242 #define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) 5243 #define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF 5244 #define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) 5245 #define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) 5246 #define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF 5247 #define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) 5248 #define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) 5249 #define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF 5250 #define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) 5251 #define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) 5252 #define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF 5253 #define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) 5254 #define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) 5255 #define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF 5256 #define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13) 5257 #define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) 5258 #define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF 5259 #define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) 5260 #define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) 5261 #define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF 5262 #define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) 5263 #define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) 5264 #define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF 5265 #define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 5266 #define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0) 5267 #define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1) 5268 #define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE 5269 #define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1) 5270 #define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1) 5271 #define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD 5272 #define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2) 5273 #define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07) 5274 #define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3 5275 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 5276 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 5277 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 5278 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 5279 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 5280 #define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5) 5281 #define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07) 5282 #define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F 5283 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 5284 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 5285 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 5286 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 5287 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 5288 #define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8) 5289 #define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07) 5290 #define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF 5291 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 5292 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 5293 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 5294 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 5295 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 5296 #define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11) 5297 #define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07) 5298 #define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF 5299 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 5300 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 5301 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 5302 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 5303 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 5304 #define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14) 5305 #define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1) 5306 #define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF 5307 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 5308 #define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0) 5309 #define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F) 5310 #define C_0286D8_NUM_INTERP 0xFFFFFFC0 5311 #define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6) 5312 #define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1) 5313 #define C_0286D8_PARAM_GEN 0xFFFFFFBF 5314 #define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7) 5315 #define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F) 5316 #define C_0286D8_FOG_ADDR 0xFFFFC07F 5317 #define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14) 5318 #define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1) 5319 #define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF 5320 #define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15) 5321 #define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1) 5322 #define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF 5323 #define R_0286E0_SPI_BARYC_CNTL 0x0286E0 5324 #define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0) 5325 #define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1) 5326 #define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE 5327 #define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4) 5328 #define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1) 5329 #define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF 5330 #define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8) 5331 #define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1) 5332 #define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF 5333 #define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12) 5334 #define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1) 5335 #define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF 5336 #define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16) 5337 #define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03) 5338 #define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF 5339 #define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00 5340 #define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20) 5341 #define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1) 5342 #define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF 5343 #define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24) 5344 #define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1) 5345 #define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF 5346 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 5347 #define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0) 5348 #define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF) 5349 #define C_0286E8_WAVES 0xFFFFF000 5350 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 5351 #define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF) 5352 #define C_0286E8_WAVESIZE 0xFE000FFF 5353 #define R_028704_SPI_WAVE_MGMT_1 0x028704 5354 #define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0) 5355 #define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F) 5356 #define C_028704_NUM_PS_WAVES 0xFFFFFFC0 5357 #define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6) 5358 #define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F) 5359 #define C_028704_NUM_VS_WAVES 0xFFFFF03F 5360 #define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12) 5361 #define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F) 5362 #define C_028704_NUM_GS_WAVES 0xFFFC0FFF 5363 #define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18) 5364 #define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F) 5365 #define C_028704_NUM_ES_WAVES 0xFF03FFFF 5366 #define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24) 5367 #define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F) 5368 #define C_028704_NUM_HS_WAVES 0xC0FFFFFF 5369 #define R_028708_SPI_WAVE_MGMT_2 0x028708 5370 #define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0) 5371 #define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F) 5372 #define C_028708_NUM_LS_WAVES 0xFFFFFFC0 5373 #define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C 5374 #define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) 5375 #define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) 5376 #define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0 5377 #define V_02870C_SPI_SHADER_NONE 0x00 5378 #define V_02870C_SPI_SHADER_1COMP 0x01 5379 #define V_02870C_SPI_SHADER_2COMP 0x02 5380 #define V_02870C_SPI_SHADER_4COMPRESS 0x03 5381 #define V_02870C_SPI_SHADER_4COMP 0x04 5382 #define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) 5383 #define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) 5384 #define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F 5385 #define V_02870C_SPI_SHADER_NONE 0x00 5386 #define V_02870C_SPI_SHADER_1COMP 0x01 5387 #define V_02870C_SPI_SHADER_2COMP 0x02 5388 #define V_02870C_SPI_SHADER_4COMPRESS 0x03 5389 #define V_02870C_SPI_SHADER_4COMP 0x04 5390 #define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) 5391 #define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) 5392 #define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF 5393 #define V_02870C_SPI_SHADER_NONE 0x00 5394 #define V_02870C_SPI_SHADER_1COMP 0x01 5395 #define V_02870C_SPI_SHADER_2COMP 0x02 5396 #define V_02870C_SPI_SHADER_4COMPRESS 0x03 5397 #define V_02870C_SPI_SHADER_4COMP 0x04 5398 #define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) 5399 #define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) 5400 #define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF 5401 #define V_02870C_SPI_SHADER_NONE 0x00 5402 #define V_02870C_SPI_SHADER_1COMP 0x01 5403 #define V_02870C_SPI_SHADER_2COMP 0x02 5404 #define V_02870C_SPI_SHADER_4COMPRESS 0x03 5405 #define V_02870C_SPI_SHADER_4COMP 0x04 5406 #define R_028710_SPI_SHADER_Z_FORMAT 0x028710 5407 #define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) 5408 #define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) 5409 #define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0 5410 #define V_028710_SPI_SHADER_ZERO 0x00 5411 #define V_028710_SPI_SHADER_32_R 0x01 5412 #define V_028710_SPI_SHADER_32_GR 0x02 5413 #define V_028710_SPI_SHADER_32_AR 0x03 5414 #define V_028710_SPI_SHADER_FP16_ABGR 0x04 5415 #define V_028710_SPI_SHADER_UNORM16_ABGR 0x05 5416 #define V_028710_SPI_SHADER_SNORM16_ABGR 0x06 5417 #define V_028710_SPI_SHADER_UINT16_ABGR 0x07 5418 #define V_028710_SPI_SHADER_SINT16_ABGR 0x08 5419 #define V_028710_SPI_SHADER_32_ABGR 0x09 5420 #define R_028714_SPI_SHADER_COL_FORMAT 0x028714 5421 #define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) 5422 #define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) 5423 #define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0 5424 #define V_028714_SPI_SHADER_ZERO 0x00 5425 #define V_028714_SPI_SHADER_32_R 0x01 5426 #define V_028714_SPI_SHADER_32_GR 0x02 5427 #define V_028714_SPI_SHADER_32_AR 0x03 5428 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5429 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5430 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5431 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5432 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5433 #define V_028714_SPI_SHADER_32_ABGR 0x09 5434 #define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) 5435 #define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) 5436 #define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F 5437 #define V_028714_SPI_SHADER_ZERO 0x00 5438 #define V_028714_SPI_SHADER_32_R 0x01 5439 #define V_028714_SPI_SHADER_32_GR 0x02 5440 #define V_028714_SPI_SHADER_32_AR 0x03 5441 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5442 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5443 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5444 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5445 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5446 #define V_028714_SPI_SHADER_32_ABGR 0x09 5447 #define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) 5448 #define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) 5449 #define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF 5450 #define V_028714_SPI_SHADER_ZERO 0x00 5451 #define V_028714_SPI_SHADER_32_R 0x01 5452 #define V_028714_SPI_SHADER_32_GR 0x02 5453 #define V_028714_SPI_SHADER_32_AR 0x03 5454 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5455 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5456 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5457 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5458 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5459 #define V_028714_SPI_SHADER_32_ABGR 0x09 5460 #define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) 5461 #define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) 5462 #define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF 5463 #define V_028714_SPI_SHADER_ZERO 0x00 5464 #define V_028714_SPI_SHADER_32_R 0x01 5465 #define V_028714_SPI_SHADER_32_GR 0x02 5466 #define V_028714_SPI_SHADER_32_AR 0x03 5467 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5468 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5469 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5470 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5471 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5472 #define V_028714_SPI_SHADER_32_ABGR 0x09 5473 #define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16) 5474 #define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F) 5475 #define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF 5476 #define V_028714_SPI_SHADER_ZERO 0x00 5477 #define V_028714_SPI_SHADER_32_R 0x01 5478 #define V_028714_SPI_SHADER_32_GR 0x02 5479 #define V_028714_SPI_SHADER_32_AR 0x03 5480 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5481 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5482 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5483 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5484 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5485 #define V_028714_SPI_SHADER_32_ABGR 0x09 5486 #define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20) 5487 #define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F) 5488 #define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF 5489 #define V_028714_SPI_SHADER_ZERO 0x00 5490 #define V_028714_SPI_SHADER_32_R 0x01 5491 #define V_028714_SPI_SHADER_32_GR 0x02 5492 #define V_028714_SPI_SHADER_32_AR 0x03 5493 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5494 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5495 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5496 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5497 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5498 #define V_028714_SPI_SHADER_32_ABGR 0x09 5499 #define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24) 5500 #define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F) 5501 #define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF 5502 #define V_028714_SPI_SHADER_ZERO 0x00 5503 #define V_028714_SPI_SHADER_32_R 0x01 5504 #define V_028714_SPI_SHADER_32_GR 0x02 5505 #define V_028714_SPI_SHADER_32_AR 0x03 5506 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5507 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5508 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5509 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5510 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5511 #define V_028714_SPI_SHADER_32_ABGR 0x09 5512 #define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28) 5513 #define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F) 5514 #define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF 5515 #define V_028714_SPI_SHADER_ZERO 0x00 5516 #define V_028714_SPI_SHADER_32_R 0x01 5517 #define V_028714_SPI_SHADER_32_GR 0x02 5518 #define V_028714_SPI_SHADER_32_AR 0x03 5519 #define V_028714_SPI_SHADER_FP16_ABGR 0x04 5520 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 5521 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 5522 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 5523 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 5524 #define V_028714_SPI_SHADER_32_ABGR 0x09 5525 #define R_028780_CB_BLEND0_CONTROL 0x028780 5526 #define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0) 5527 #define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F) 5528 #define C_028780_COLOR_SRCBLEND 0xFFFFFFE0 5529 #define V_028780_BLEND_ZERO 0x00 5530 #define V_028780_BLEND_ONE 0x01 5531 #define V_028780_BLEND_SRC_COLOR 0x02 5532 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 5533 #define V_028780_BLEND_SRC_ALPHA 0x04 5534 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 5535 #define V_028780_BLEND_DST_ALPHA 0x06 5536 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 5537 #define V_028780_BLEND_DST_COLOR 0x08 5538 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 5539 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A 5540 #define V_028780_BLEND_CONSTANT_COLOR 0x0D 5541 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E 5542 #define V_028780_BLEND_SRC1_COLOR 0x0F 5543 #define V_028780_BLEND_INV_SRC1_COLOR 0x10 5544 #define V_028780_BLEND_SRC1_ALPHA 0x11 5545 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 5546 #define V_028780_BLEND_CONSTANT_ALPHA 0x13 5547 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 5548 #define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5) 5549 #define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07) 5550 #define C_028780_COLOR_COMB_FCN 0xFFFFFF1F 5551 #define V_028780_COMB_DST_PLUS_SRC 0x00 5552 #define V_028780_COMB_SRC_MINUS_DST 0x01 5553 #define V_028780_COMB_MIN_DST_SRC 0x02 5554 #define V_028780_COMB_MAX_DST_SRC 0x03 5555 #define V_028780_COMB_DST_MINUS_SRC 0x04 5556 #define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8) 5557 #define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F) 5558 #define C_028780_COLOR_DESTBLEND 0xFFFFE0FF 5559 #define V_028780_BLEND_ZERO 0x00 5560 #define V_028780_BLEND_ONE 0x01 5561 #define V_028780_BLEND_SRC_COLOR 0x02 5562 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 5563 #define V_028780_BLEND_SRC_ALPHA 0x04 5564 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 5565 #define V_028780_BLEND_DST_ALPHA 0x06 5566 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 5567 #define V_028780_BLEND_DST_COLOR 0x08 5568 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 5569 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A 5570 #define V_028780_BLEND_CONSTANT_COLOR 0x0D 5571 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E 5572 #define V_028780_BLEND_SRC1_COLOR 0x0F 5573 #define V_028780_BLEND_INV_SRC1_COLOR 0x10 5574 #define V_028780_BLEND_SRC1_ALPHA 0x11 5575 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 5576 #define V_028780_BLEND_CONSTANT_ALPHA 0x13 5577 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 5578 #define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16) 5579 #define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F) 5580 #define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF 5581 #define V_028780_BLEND_ZERO 0x00 5582 #define V_028780_BLEND_ONE 0x01 5583 #define V_028780_BLEND_SRC_COLOR 0x02 5584 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 5585 #define V_028780_BLEND_SRC_ALPHA 0x04 5586 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 5587 #define V_028780_BLEND_DST_ALPHA 0x06 5588 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 5589 #define V_028780_BLEND_DST_COLOR 0x08 5590 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 5591 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A 5592 #define V_028780_BLEND_CONSTANT_COLOR 0x0D 5593 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E 5594 #define V_028780_BLEND_SRC1_COLOR 0x0F 5595 #define V_028780_BLEND_INV_SRC1_COLOR 0x10 5596 #define V_028780_BLEND_SRC1_ALPHA 0x11 5597 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 5598 #define V_028780_BLEND_CONSTANT_ALPHA 0x13 5599 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 5600 #define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21) 5601 #define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07) 5602 #define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF 5603 #define V_028780_COMB_DST_PLUS_SRC 0x00 5604 #define V_028780_COMB_SRC_MINUS_DST 0x01 5605 #define V_028780_COMB_MIN_DST_SRC 0x02 5606 #define V_028780_COMB_MAX_DST_SRC 0x03 5607 #define V_028780_COMB_DST_MINUS_SRC 0x04 5608 #define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24) 5609 #define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F) 5610 #define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF 5611 #define V_028780_BLEND_ZERO 0x00 5612 #define V_028780_BLEND_ONE 0x01 5613 #define V_028780_BLEND_SRC_COLOR 0x02 5614 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 5615 #define V_028780_BLEND_SRC_ALPHA 0x04 5616 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 5617 #define V_028780_BLEND_DST_ALPHA 0x06 5618 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 5619 #define V_028780_BLEND_DST_COLOR 0x08 5620 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 5621 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A 5622 #define V_028780_BLEND_CONSTANT_COLOR 0x0D 5623 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E 5624 #define V_028780_BLEND_SRC1_COLOR 0x0F 5625 #define V_028780_BLEND_INV_SRC1_COLOR 0x10 5626 #define V_028780_BLEND_SRC1_ALPHA 0x11 5627 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 5628 #define V_028780_BLEND_CONSTANT_ALPHA 0x13 5629 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 5630 #define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29) 5631 #define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1) 5632 #define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF 5633 #define S_028780_ENABLE(x) (((x) & 0x1) << 30) 5634 #define G_028780_ENABLE(x) (((x) >> 30) & 0x1) 5635 #define C_028780_ENABLE 0xBFFFFFFF 5636 #define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31) 5637 #define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1) 5638 #define C_028780_DISABLE_ROP3 0x7FFFFFFF 5639 #define R_028784_CB_BLEND1_CONTROL 0x028784 5640 #define R_028788_CB_BLEND2_CONTROL 0x028788 5641 #define R_02878C_CB_BLEND3_CONTROL 0x02878C 5642 #define R_028790_CB_BLEND4_CONTROL 0x028790 5643 #define R_028794_CB_BLEND5_CONTROL 0x028794 5644 #define R_028798_CB_BLEND6_CONTROL 0x028798 5645 #define R_02879C_CB_BLEND7_CONTROL 0x02879C 5646 #define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4 5647 #define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8 5648 #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC 5649 #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0 5650 #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 5651 #define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0) 5652 #define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF) 5653 #define C_0287E4_BASE_ADDR 0xFFFFFF00 5654 #define R_0287E8_VGT_DMA_BASE 0x0287E8 5655 #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 5656 #define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0) 5657 #define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03) 5658 #define C_0287F0_SOURCE_SELECT 0xFFFFFFFC 5659 #define V_0287F0_DI_SRC_SEL_DMA 0x00 5660 #define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 5661 #define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02 5662 #define V_0287F0_DI_SRC_SEL_RESERVED 0x03 5663 #define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2) 5664 #define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03) 5665 #define C_0287F0_MAJOR_MODE 0xFFFFFFF3 5666 #define V_0287F0_DI_MAJOR_MODE_0 0x00 5667 #define V_0287F0_DI_MAJOR_MODE_1 0x01 5668 #define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) 5669 #define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) 5670 #define C_0287F0_NOT_EOP 0xFFFFFFDF 5671 #define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) 5672 #define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) 5673 #define C_0287F0_USE_OPAQUE 0xFFFFFFBF 5674 #define R_0287F4_VGT_IMMED_DATA 0x0287F4 5675 #define R_028800_DB_DEPTH_CONTROL 0x028800 5676 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 5677 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 5678 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 5679 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 5680 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 5681 #define C_028800_Z_ENABLE 0xFFFFFFFD 5682 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 5683 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 5684 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 5685 #define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3) 5686 #define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1) 5687 #define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7 5688 #define S_028800_ZFUNC(x) (((x) & 0x07) << 4) 5689 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x07) 5690 #define C_028800_ZFUNC 0xFFFFFF8F 5691 #define V_028800_FRAG_NEVER 0x00 5692 #define V_028800_FRAG_LESS 0x01 5693 #define V_028800_FRAG_EQUAL 0x02 5694 #define V_028800_FRAG_LEQUAL 0x03 5695 #define V_028800_FRAG_GREATER 0x04 5696 #define V_028800_FRAG_NOTEQUAL 0x05 5697 #define V_028800_FRAG_GEQUAL 0x06 5698 #define V_028800_FRAG_ALWAYS 0x07 5699 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 5700 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 5701 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 5702 #define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8) 5703 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07) 5704 #define C_028800_STENCILFUNC 0xFFFFF8FF 5705 #define V_028800_REF_NEVER 0x00 5706 #define V_028800_REF_LESS 0x01 5707 #define V_028800_REF_EQUAL 0x02 5708 #define V_028800_REF_LEQUAL 0x03 5709 #define V_028800_REF_GREATER 0x04 5710 #define V_028800_REF_NOTEQUAL 0x05 5711 #define V_028800_REF_GEQUAL 0x06 5712 #define V_028800_REF_ALWAYS 0x07 5713 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20) 5714 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07) 5715 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 5716 #define V_028800_REF_NEVER 0x00 5717 #define V_028800_REF_LESS 0x01 5718 #define V_028800_REF_EQUAL 0x02 5719 #define V_028800_REF_LEQUAL 0x03 5720 #define V_028800_REF_GREATER 0x04 5721 #define V_028800_REF_NOTEQUAL 0x05 5722 #define V_028800_REF_GEQUAL 0x06 5723 #define V_028800_REF_ALWAYS 0x07 5724 #define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30) 5725 #define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1) 5726 #define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF 5727 #define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31) 5728 #define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1) 5729 #define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF 5730 #define R_028804_DB_EQAA 0x028804 5731 #define R_028808_CB_COLOR_CONTROL 0x028808 5732 #define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) 5733 #define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) 5734 #define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 5735 #define S_028808_MODE(x) (((x) & 0x07) << 4) 5736 #define G_028808_MODE(x) (((x) >> 4) & 0x07) 5737 #define C_028808_MODE 0xFFFFFF8F 5738 #define V_028808_CB_DISABLE 0x00 5739 #define V_028808_CB_NORMAL 0x01 5740 #define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02 5741 #define V_028808_CB_RESOLVE 0x03 5742 #define V_028808_CB_FMASK_DECOMPRESS 0x05 5743 #define S_028808_ROP3(x) (((x) & 0xFF) << 16) 5744 #define G_028808_ROP3(x) (((x) >> 16) & 0xFF) 5745 #define C_028808_ROP3 0xFF00FFFF 5746 #define V_028808_X_0X00 0x00 5747 #define V_028808_X_0X05 0x05 5748 #define V_028808_X_0X0A 0x0A 5749 #define V_028808_X_0X0F 0x0F 5750 #define V_028808_X_0X11 0x11 5751 #define V_028808_X_0X22 0x22 5752 #define V_028808_X_0X33 0x33 5753 #define V_028808_X_0X44 0x44 5754 #define V_028808_X_0X50 0x50 5755 #define V_028808_X_0X55 0x55 5756 #define V_028808_X_0X5A 0x5A 5757 #define V_028808_X_0X5F 0x5F 5758 #define V_028808_X_0X66 0x66 5759 #define V_028808_X_0X77 0x77 5760 #define V_028808_X_0X88 0x88 5761 #define V_028808_X_0X99 0x99 5762 #define V_028808_X_0XA0 0xA0 5763 #define V_028808_X_0XA5 0xA5 5764 #define V_028808_X_0XAA 0xAA 5765 #define V_028808_X_0XAF 0xAF 5766 #define V_028808_X_0XBB 0xBB 5767 #define V_028808_X_0XCC 0xCC 5768 #define V_028808_X_0XDD 0xDD 5769 #define V_028808_X_0XEE 0xEE 5770 #define V_028808_X_0XF0 0xF0 5771 #define V_028808_X_0XF5 0xF5 5772 #define V_028808_X_0XFA 0xFA 5773 #define V_028808_X_0XFF 0xFF 5774 #define R_02880C_DB_SHADER_CONTROL 0x02880C 5775 #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0) 5776 #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) 5777 #define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE 5778 #define S_02880C_STENCIL_TEST_VAL_EXPORT_ENAB(x) (((x) & 0x1) << 1) 5779 #define G_02880C_STENCIL_TEST_VAL_EXPORT_ENAB(x) (((x) >> 1) & 0x1) 5780 #define C_02880C_STENCIL_TEST_VAL_EXPORT_ENAB 0xFFFFFFFD 5781 #define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2) 5782 #define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1) 5783 #define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB 5784 #define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4) 5785 #define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03) 5786 #define C_02880C_Z_ORDER 0xFFFFFFCF 5787 #define V_02880C_LATE_Z 0x00 5788 #define V_02880C_EARLY_Z_THEN_LATE_Z 0x01 5789 #define V_02880C_RE_Z 0x02 5790 #define V_02880C_EARLY_Z_THEN_RE_Z 0x03 5791 #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6) 5792 #define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1) 5793 #define C_02880C_KILL_ENABLE 0xFFFFFFBF 5794 #define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7) 5795 #define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1) 5796 #define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F 5797 #define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8) 5798 #define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1) 5799 #define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF 5800 #define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9) 5801 #define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1) 5802 #define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF 5803 #define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10) 5804 #define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1) 5805 #define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF 5806 #define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11) 5807 #define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1) 5808 #define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF 5809 #define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12) 5810 #define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1) 5811 #define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF 5812 #define R_028810_PA_CL_CLIP_CNTL 0x028810 5813 #define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0) 5814 #define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1) 5815 #define C_028810_UCP_ENA_0 0xFFFFFFFE 5816 #define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1) 5817 #define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1) 5818 #define C_028810_UCP_ENA_1 0xFFFFFFFD 5819 #define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2) 5820 #define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1) 5821 #define C_028810_UCP_ENA_2 0xFFFFFFFB 5822 #define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3) 5823 #define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1) 5824 #define C_028810_UCP_ENA_3 0xFFFFFFF7 5825 #define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4) 5826 #define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1) 5827 #define C_028810_UCP_ENA_4 0xFFFFFFEF 5828 #define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5) 5829 #define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1) 5830 #define C_028810_UCP_ENA_5 0xFFFFFFDF 5831 #define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13) 5832 #define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1) 5833 #define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF 5834 #define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14) 5835 #define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03) 5836 #define C_028810_PS_UCP_MODE 0xFFFF3FFF 5837 #define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16) 5838 #define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1) 5839 #define C_028810_CLIP_DISABLE 0xFFFEFFFF 5840 #define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17) 5841 #define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1) 5842 #define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF 5843 #define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18) 5844 #define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1) 5845 #define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF 5846 #define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19) 5847 #define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1) 5848 #define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF 5849 #define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20) 5850 #define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1) 5851 #define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF 5852 #define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21) 5853 #define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1) 5854 #define C_028810_VTX_KILL_OR 0xFFDFFFFF 5855 #define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22) 5856 #define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1) 5857 #define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF 5858 #define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24) 5859 #define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1) 5860 #define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF 5861 #define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25) 5862 #define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1) 5863 #define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF 5864 #define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26) 5865 #define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1) 5866 #define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF 5867 #define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27) 5868 #define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1) 5869 #define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF 5870 #define R_028814_PA_SU_SC_MODE_CNTL 0x028814 5871 #define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0) 5872 #define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1) 5873 #define C_028814_CULL_FRONT 0xFFFFFFFE 5874 #define S_028814_CULL_BACK(x) (((x) & 0x1) << 1) 5875 #define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1) 5876 #define C_028814_CULL_BACK 0xFFFFFFFD 5877 #define S_028814_FACE(x) (((x) & 0x1) << 2) 5878 #define G_028814_FACE(x) (((x) >> 2) & 0x1) 5879 #define C_028814_FACE 0xFFFFFFFB 5880 #define S_028814_POLY_MODE(x) (((x) & 0x03) << 3) 5881 #define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03) 5882 #define C_028814_POLY_MODE 0xFFFFFFE7 5883 #define V_028814_X_DISABLE_POLY_MODE 0x00 5884 #define V_028814_X_DUAL_MODE 0x01 5885 #define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5) 5886 #define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07) 5887 #define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F 5888 #define V_028814_X_DRAW_POINTS 0x00 5889 #define V_028814_X_DRAW_LINES 0x01 5890 #define V_028814_X_DRAW_TRIANGLES 0x02 5891 #define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8) 5892 #define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07) 5893 #define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF 5894 #define V_028814_X_DRAW_POINTS 0x00 5895 #define V_028814_X_DRAW_LINES 0x01 5896 #define V_028814_X_DRAW_TRIANGLES 0x02 5897 #define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11) 5898 #define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1) 5899 #define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF 5900 #define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12) 5901 #define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1) 5902 #define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF 5903 #define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13) 5904 #define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1) 5905 #define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF 5906 #define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16) 5907 #define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1) 5908 #define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF 5909 #define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19) 5910 #define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1) 5911 #define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF 5912 #define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20) 5913 #define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1) 5914 #define C_028814_PERSP_CORR_DIS 0xFFEFFFFF 5915 #define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21) 5916 #define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1) 5917 #define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF 5918 #define R_028818_PA_CL_VTE_CNTL 0x028818 5919 #define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0) 5920 #define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1) 5921 #define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE 5922 #define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1) 5923 #define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1) 5924 #define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD 5925 #define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2) 5926 #define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1) 5927 #define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB 5928 #define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3) 5929 #define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1) 5930 #define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7 5931 #define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4) 5932 #define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1) 5933 #define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF 5934 #define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5) 5935 #define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1) 5936 #define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF 5937 #define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8) 5938 #define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1) 5939 #define C_028818_VTX_XY_FMT 0xFFFFFEFF 5940 #define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9) 5941 #define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1) 5942 #define C_028818_VTX_Z_FMT 0xFFFFFDFF 5943 #define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10) 5944 #define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1) 5945 #define C_028818_VTX_W0_FMT 0xFFFFFBFF 5946 #define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C 5947 #define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0) 5948 #define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1) 5949 #define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE 5950 #define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1) 5951 #define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1) 5952 #define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD 5953 #define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2) 5954 #define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1) 5955 #define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB 5956 #define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3) 5957 #define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1) 5958 #define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7 5959 #define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4) 5960 #define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1) 5961 #define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF 5962 #define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5) 5963 #define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1) 5964 #define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF 5965 #define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6) 5966 #define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1) 5967 #define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF 5968 #define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7) 5969 #define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1) 5970 #define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F 5971 #define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8) 5972 #define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1) 5973 #define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF 5974 #define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9) 5975 #define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1) 5976 #define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF 5977 #define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10) 5978 #define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1) 5979 #define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF 5980 #define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11) 5981 #define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1) 5982 #define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF 5983 #define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12) 5984 #define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1) 5985 #define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF 5986 #define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13) 5987 #define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1) 5988 #define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF 5989 #define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14) 5990 #define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1) 5991 #define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF 5992 #define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15) 5993 #define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1) 5994 #define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF 5995 #define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16) 5996 #define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1) 5997 #define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF 5998 #define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17) 5999 #define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1) 6000 #define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF 6001 #define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18) 6002 #define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1) 6003 #define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF 6004 #define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19) 6005 #define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1) 6006 #define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF 6007 #define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20) 6008 #define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1) 6009 #define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF 6010 #define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21) 6011 #define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1) 6012 #define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF 6013 #define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22) 6014 #define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1) 6015 #define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF 6016 #define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23) 6017 #define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1) 6018 #define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF 6019 #define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24) 6020 #define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1) 6021 #define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF 6022 #define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25) 6023 #define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1) 6024 #define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF 6025 #define R_028820_PA_CL_NANINF_CNTL 0x028820 6026 #define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0) 6027 #define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1) 6028 #define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE 6029 #define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1) 6030 #define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1) 6031 #define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD 6032 #define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2) 6033 #define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1) 6034 #define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB 6035 #define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3) 6036 #define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1) 6037 #define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7 6038 #define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4) 6039 #define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1) 6040 #define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF 6041 #define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5) 6042 #define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1) 6043 #define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF 6044 #define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6) 6045 #define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1) 6046 #define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF 6047 #define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7) 6048 #define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1) 6049 #define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F 6050 #define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8) 6051 #define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1) 6052 #define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF 6053 #define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9) 6054 #define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1) 6055 #define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF 6056 #define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10) 6057 #define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1) 6058 #define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF 6059 #define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11) 6060 #define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1) 6061 #define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF 6062 #define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12) 6063 #define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1) 6064 #define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF 6065 #define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13) 6066 #define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1) 6067 #define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF 6068 #define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14) 6069 #define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1) 6070 #define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF 6071 #define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20) 6072 #define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1) 6073 #define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF 6074 #define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824 6075 #define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0) 6076 #define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03) 6077 #define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC 6078 #define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2) 6079 #define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1) 6080 #define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB 6081 #define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3) 6082 #define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1) 6083 #define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7 6084 #define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4) 6085 #define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1) 6086 #define C_028824_DIAMOND_ADJUST 0xFFFFFFEF 6087 #define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828 6088 #define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C 6089 #define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0) 6090 #define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1) 6091 #define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE 6092 #define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1) 6093 #define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1) 6094 #define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD 6095 #define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2) 6096 #define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1) 6097 #define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB 6098 #define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3) 6099 #define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1) 6100 #define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7 6101 #define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4) 6102 #define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1) 6103 #define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF 6104 #define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5) 6105 #define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1) 6106 #define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF 6107 #define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6) 6108 #define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1) 6109 #define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF 6110 #define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7) 6111 #define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1) 6112 #define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F 6113 #define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8) 6114 #define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF) 6115 #define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF 6116 #define R_028A00_PA_SU_POINT_SIZE 0x028A00 6117 #define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0) 6118 #define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF) 6119 #define C_028A00_HEIGHT 0xFFFF0000 6120 #define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16) 6121 #define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF) 6122 #define C_028A00_WIDTH 0x0000FFFF 6123 #define R_028A04_PA_SU_POINT_MINMAX 0x028A04 6124 #define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0) 6125 #define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF) 6126 #define C_028A04_MIN_SIZE 0xFFFF0000 6127 #define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16) 6128 #define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF) 6129 #define C_028A04_MAX_SIZE 0x0000FFFF 6130 #define R_028A08_PA_SU_LINE_CNTL 0x028A08 6131 #define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0) 6132 #define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF) 6133 #define C_028A08_WIDTH 0xFFFF0000 6134 #define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C 6135 #define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0) 6136 #define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF) 6137 #define C_028A0C_LINE_PATTERN 0xFFFF0000 6138 #define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16) 6139 #define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF) 6140 #define C_028A0C_REPEAT_COUNT 0xFF00FFFF 6141 #define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28) 6142 #define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1) 6143 #define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF 6144 #define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29) 6145 #define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03) 6146 #define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF 6147 #define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10 6148 #define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0) 6149 #define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07) 6150 #define C_028A10_PATH_SELECT 0xFFFFFFF8 6151 #define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00 6152 #define V_028A10_VGT_OUTPATH_TESS_EN 0x01 6153 #define V_028A10_VGT_OUTPATH_PASSTHRU 0x02 6154 #define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03 6155 #define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04 6156 #define R_028A14_VGT_HOS_CNTL 0x028A14 6157 #define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0) 6158 #define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03) 6159 #define C_028A14_TESS_MODE 0xFFFFFFFC 6160 #define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18 6161 #define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C 6162 #define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20 6163 #define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0) 6164 #define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) 6165 #define C_028A20_REUSE_DEPTH 0xFFFFFF00 6166 #define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24 6167 #define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0) 6168 #define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F) 6169 #define C_028A24_PRIM_TYPE 0xFFFFFFE0 6170 #define V_028A24_VGT_GRP_3D_POINT 0x00 6171 #define V_028A24_VGT_GRP_3D_LINE 0x01 6172 #define V_028A24_VGT_GRP_3D_TRI 0x02 6173 #define V_028A24_VGT_GRP_3D_RECT 0x03 6174 #define V_028A24_VGT_GRP_3D_QUAD 0x04 6175 #define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05 6176 #define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06 6177 #define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07 6178 #define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08 6179 #define V_028A24_VGT_GRP_2D_FILL_RECT 0x09 6180 #define V_028A24_VGT_GRP_2D_LINE 0x0A 6181 #define V_028A24_VGT_GRP_2D_TRI 0x0B 6182 #define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C 6183 #define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D 6184 #define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E 6185 #define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F 6186 #define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10 6187 #define V_028A24_VGT_GRP_3D_PATCH 0x11 6188 #define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14) 6189 #define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1) 6190 #define C_028A24_RETAIN_ORDER 0xFFFFBFFF 6191 #define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15) 6192 #define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1) 6193 #define C_028A24_RETAIN_QUADS 0xFFFF7FFF 6194 #define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16) 6195 #define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07) 6196 #define C_028A24_PRIM_ORDER 0xFFF8FFFF 6197 #define V_028A24_VGT_GRP_LIST 0x00 6198 #define V_028A24_VGT_GRP_STRIP 0x01 6199 #define V_028A24_VGT_GRP_FAN 0x02 6200 #define V_028A24_VGT_GRP_LOOP 0x03 6201 #define V_028A24_VGT_GRP_POLYGON 0x04 6202 #define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28 6203 #define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0) 6204 #define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F) 6205 #define C_028A28_FIRST_DECR 0xFFFFFFF0 6206 #define R_028A2C_VGT_GROUP_DECR 0x028A2C 6207 #define S_028A2C_DECR(x) (((x) & 0x0F) << 0) 6208 #define G_028A2C_DECR(x) (((x) >> 0) & 0x0F) 6209 #define C_028A2C_DECR 0xFFFFFFF0 6210 #define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30 6211 #define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0) 6212 #define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1) 6213 #define C_028A30_COMP_X_EN 0xFFFFFFFE 6214 #define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1) 6215 #define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1) 6216 #define C_028A30_COMP_Y_EN 0xFFFFFFFD 6217 #define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2) 6218 #define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1) 6219 #define C_028A30_COMP_Z_EN 0xFFFFFFFB 6220 #define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3) 6221 #define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1) 6222 #define C_028A30_COMP_W_EN 0xFFFFFFF7 6223 #define S_028A30_STRIDE(x) (((x) & 0xFF) << 8) 6224 #define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF) 6225 #define C_028A30_STRIDE 0xFFFF00FF 6226 #define S_028A30_SHIFT(x) (((x) & 0xFF) << 16) 6227 #define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF) 6228 #define C_028A30_SHIFT 0xFF00FFFF 6229 #define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34 6230 #define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0) 6231 #define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1) 6232 #define C_028A34_COMP_X_EN 0xFFFFFFFE 6233 #define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1) 6234 #define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1) 6235 #define C_028A34_COMP_Y_EN 0xFFFFFFFD 6236 #define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2) 6237 #define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1) 6238 #define C_028A34_COMP_Z_EN 0xFFFFFFFB 6239 #define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3) 6240 #define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1) 6241 #define C_028A34_COMP_W_EN 0xFFFFFFF7 6242 #define S_028A34_STRIDE(x) (((x) & 0xFF) << 8) 6243 #define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF) 6244 #define C_028A34_STRIDE 0xFFFF00FF 6245 #define S_028A34_SHIFT(x) (((x) & 0xFF) << 16) 6246 #define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF) 6247 #define C_028A34_SHIFT 0xFF00FFFF 6248 #define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38 6249 #define S_028A38_X_CONV(x) (((x) & 0x0F) << 0) 6250 #define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F) 6251 #define C_028A38_X_CONV 0xFFFFFFF0 6252 #define V_028A38_VGT_GRP_INDEX_16 0x00 6253 #define V_028A38_VGT_GRP_INDEX_32 0x01 6254 #define V_028A38_VGT_GRP_UINT_16 0x02 6255 #define V_028A38_VGT_GRP_UINT_32 0x03 6256 #define V_028A38_VGT_GRP_SINT_16 0x04 6257 #define V_028A38_VGT_GRP_SINT_32 0x05 6258 #define V_028A38_VGT_GRP_FLOAT_32 0x06 6259 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 6260 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6261 #define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4) 6262 #define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F) 6263 #define C_028A38_X_OFFSET 0xFFFFFF0F 6264 #define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8) 6265 #define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F) 6266 #define C_028A38_Y_CONV 0xFFFFF0FF 6267 #define V_028A38_VGT_GRP_INDEX_16 0x00 6268 #define V_028A38_VGT_GRP_INDEX_32 0x01 6269 #define V_028A38_VGT_GRP_UINT_16 0x02 6270 #define V_028A38_VGT_GRP_UINT_32 0x03 6271 #define V_028A38_VGT_GRP_SINT_16 0x04 6272 #define V_028A38_VGT_GRP_SINT_32 0x05 6273 #define V_028A38_VGT_GRP_FLOAT_32 0x06 6274 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 6275 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6276 #define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12) 6277 #define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F) 6278 #define C_028A38_Y_OFFSET 0xFFFF0FFF 6279 #define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16) 6280 #define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F) 6281 #define C_028A38_Z_CONV 0xFFF0FFFF 6282 #define V_028A38_VGT_GRP_INDEX_16 0x00 6283 #define V_028A38_VGT_GRP_INDEX_32 0x01 6284 #define V_028A38_VGT_GRP_UINT_16 0x02 6285 #define V_028A38_VGT_GRP_UINT_32 0x03 6286 #define V_028A38_VGT_GRP_SINT_16 0x04 6287 #define V_028A38_VGT_GRP_SINT_32 0x05 6288 #define V_028A38_VGT_GRP_FLOAT_32 0x06 6289 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 6290 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6291 #define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20) 6292 #define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F) 6293 #define C_028A38_Z_OFFSET 0xFF0FFFFF 6294 #define S_028A38_W_CONV(x) (((x) & 0x0F) << 24) 6295 #define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F) 6296 #define C_028A38_W_CONV 0xF0FFFFFF 6297 #define V_028A38_VGT_GRP_INDEX_16 0x00 6298 #define V_028A38_VGT_GRP_INDEX_32 0x01 6299 #define V_028A38_VGT_GRP_UINT_16 0x02 6300 #define V_028A38_VGT_GRP_UINT_32 0x03 6301 #define V_028A38_VGT_GRP_SINT_16 0x04 6302 #define V_028A38_VGT_GRP_SINT_32 0x05 6303 #define V_028A38_VGT_GRP_FLOAT_32 0x06 6304 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 6305 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6306 #define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28) 6307 #define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F) 6308 #define C_028A38_W_OFFSET 0x0FFFFFFF 6309 #define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C 6310 #define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0) 6311 #define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F) 6312 #define C_028A3C_X_CONV 0xFFFFFFF0 6313 #define V_028A3C_VGT_GRP_INDEX_16 0x00 6314 #define V_028A3C_VGT_GRP_INDEX_32 0x01 6315 #define V_028A3C_VGT_GRP_UINT_16 0x02 6316 #define V_028A3C_VGT_GRP_UINT_32 0x03 6317 #define V_028A3C_VGT_GRP_SINT_16 0x04 6318 #define V_028A3C_VGT_GRP_SINT_32 0x05 6319 #define V_028A3C_VGT_GRP_FLOAT_32 0x06 6320 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 6321 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6322 #define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4) 6323 #define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F) 6324 #define C_028A3C_X_OFFSET 0xFFFFFF0F 6325 #define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8) 6326 #define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F) 6327 #define C_028A3C_Y_CONV 0xFFFFF0FF 6328 #define V_028A3C_VGT_GRP_INDEX_16 0x00 6329 #define V_028A3C_VGT_GRP_INDEX_32 0x01 6330 #define V_028A3C_VGT_GRP_UINT_16 0x02 6331 #define V_028A3C_VGT_GRP_UINT_32 0x03 6332 #define V_028A3C_VGT_GRP_SINT_16 0x04 6333 #define V_028A3C_VGT_GRP_SINT_32 0x05 6334 #define V_028A3C_VGT_GRP_FLOAT_32 0x06 6335 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 6336 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6337 #define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12) 6338 #define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F) 6339 #define C_028A3C_Y_OFFSET 0xFFFF0FFF 6340 #define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16) 6341 #define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F) 6342 #define C_028A3C_Z_CONV 0xFFF0FFFF 6343 #define V_028A3C_VGT_GRP_INDEX_16 0x00 6344 #define V_028A3C_VGT_GRP_INDEX_32 0x01 6345 #define V_028A3C_VGT_GRP_UINT_16 0x02 6346 #define V_028A3C_VGT_GRP_UINT_32 0x03 6347 #define V_028A3C_VGT_GRP_SINT_16 0x04 6348 #define V_028A3C_VGT_GRP_SINT_32 0x05 6349 #define V_028A3C_VGT_GRP_FLOAT_32 0x06 6350 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 6351 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6352 #define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20) 6353 #define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F) 6354 #define C_028A3C_Z_OFFSET 0xFF0FFFFF 6355 #define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24) 6356 #define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F) 6357 #define C_028A3C_W_CONV 0xF0FFFFFF 6358 #define V_028A3C_VGT_GRP_INDEX_16 0x00 6359 #define V_028A3C_VGT_GRP_INDEX_32 0x01 6360 #define V_028A3C_VGT_GRP_UINT_16 0x02 6361 #define V_028A3C_VGT_GRP_UINT_32 0x03 6362 #define V_028A3C_VGT_GRP_SINT_16 0x04 6363 #define V_028A3C_VGT_GRP_SINT_32 0x05 6364 #define V_028A3C_VGT_GRP_FLOAT_32 0x06 6365 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 6366 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 6367 #define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28) 6368 #define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F) 6369 #define C_028A3C_W_OFFSET 0x0FFFFFFF 6370 #define R_028A40_VGT_GS_MODE 0x028A40 6371 #define S_028A40_MODE(x) (((x) & 0x07) << 0) 6372 #define G_028A40_MODE(x) (((x) >> 0) & 0x07) 6373 #define C_028A40_MODE 0xFFFFFFF8 6374 #define V_028A40_GS_OFF 0x00 6375 #define V_028A40_GS_SCENARIO_A 0x01 6376 #define V_028A40_GS_SCENARIO_B 0x02 6377 #define V_028A40_GS_SCENARIO_G 0x03 6378 #define V_028A40_GS_SCENARIO_C 0x04 6379 #define V_028A40_SPRITE_EN 0x05 6380 #define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4) 6381 #define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03) 6382 #define C_028A40_CUT_MODE 0xFFFFFFCF 6383 #define V_028A40_GS_CUT_1024 0x00 6384 #define V_028A40_GS_CUT_512 0x01 6385 #define V_028A40_GS_CUT_256 0x02 6386 #define V_028A40_GS_CUT_128 0x03 6387 #define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11) 6388 #define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1) 6389 #define C_028A40_GS_C_PACK_EN 0xFFFFF7FF 6390 #define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13) 6391 #define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1) 6392 #define C_028A40_ES_PASSTHRU 0xFFFFDFFF 6393 #define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14) 6394 #define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1) 6395 #define C_028A40_COMPUTE_MODE 0xFFFFBFFF 6396 #define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15) 6397 #define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1) 6398 #define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF 6399 #define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16) 6400 #define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1) 6401 #define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF 6402 #define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17) 6403 #define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1) 6404 #define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF 6405 #define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18) 6406 #define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1) 6407 #define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF 6408 #define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19) 6409 #define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1) 6410 #define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF 6411 #define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20) 6412 #define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1) 6413 #define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF 6414 #define R_028A48_PA_SC_MODE_CNTL_0 0x028A48 6415 #define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0) 6416 #define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1) 6417 #define C_028A48_MSAA_ENABLE 0xFFFFFFFE 6418 #define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1) 6419 #define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1) 6420 #define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD 6421 #define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2) 6422 #define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1) 6423 #define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB 6424 #define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3) 6425 #define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1) 6426 #define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7 6427 #define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C 6428 #define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0) 6429 #define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1) 6430 #define C_028A4C_WALK_SIZE 0xFFFFFFFE 6431 #define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1) 6432 #define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1) 6433 #define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD 6434 #define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2) 6435 #define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1) 6436 #define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB 6437 #define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3) 6438 #define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1) 6439 #define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7 6440 #define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4) 6441 #define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07) 6442 #define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F 6443 #define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7) 6444 #define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1) 6445 #define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F 6446 #define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8) 6447 #define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1) 6448 #define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF 6449 #define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9) 6450 #define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1) 6451 #define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF 6452 #define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10) 6453 #define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1) 6454 #define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF 6455 #define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11) 6456 #define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1) 6457 #define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF 6458 #define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12) 6459 #define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1) 6460 #define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF 6461 #define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13) 6462 #define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1) 6463 #define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF 6464 #define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14) 6465 #define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1) 6466 #define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF 6467 #define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15) 6468 #define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1) 6469 #define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF 6470 #define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16) 6471 #define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1) 6472 #define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF 6473 #define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) & 0x1) << 17) 6474 #define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) >> 17) & 0x1) 6475 #define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC 0xFFFDFFFF 6476 #define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25) 6477 #define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1) 6478 #define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF 6479 #define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26) 6480 #define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1) 6481 #define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF 6482 #define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27) 6483 #define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1) 6484 #define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF 6485 #define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28) 6486 #define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07) 6487 #define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF 6488 #define R_028A50_VGT_ENHANCE 0x028A50 6489 #define R_028A54_VGT_GS_PER_ES 0x028A54 6490 #define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0) 6491 #define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF) 6492 #define C_028A54_GS_PER_ES 0xFFFFF800 6493 #define R_028A58_VGT_ES_PER_GS 0x028A58 6494 #define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0) 6495 #define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF) 6496 #define C_028A58_ES_PER_GS 0xFFFFF800 6497 #define R_028A5C_VGT_GS_PER_VS 0x028A5C 6498 #define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0) 6499 #define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F) 6500 #define C_028A5C_GS_PER_VS 0xFFFFFFF0 6501 #define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60 6502 #define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0) 6503 #define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF) 6504 #define C_028A60_OFFSET 0xFFFF8000 6505 #define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64 6506 #define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0) 6507 #define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF) 6508 #define C_028A64_OFFSET 0xFFFF8000 6509 #define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68 6510 #define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0) 6511 #define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF) 6512 #define C_028A68_OFFSET 0xFFFF8000 6513 #define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C 6514 #define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0) 6515 #define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F) 6516 #define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0 6517 #define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8) 6518 #define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F) 6519 #define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF 6520 #define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16) 6521 #define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F) 6522 #define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF 6523 #define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22) 6524 #define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F) 6525 #define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF 6526 #define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31) 6527 #define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1) 6528 #define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF 6529 #define R_028A70_IA_ENHANCE 0x028A70 6530 #define R_028A74_VGT_DMA_SIZE 0x028A74 6531 #define R_028A78_VGT_DMA_MAX_SIZE 0x028A78 6532 #define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C 6533 #define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0) 6534 #define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03) 6535 #define C_028A7C_INDEX_TYPE 0xFFFFFFFC 6536 #define V_028A7C_VGT_INDEX_16 0x00 6537 #define V_028A7C_VGT_INDEX_32 0x01 6538 #define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2) 6539 #define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03) 6540 #define C_028A7C_SWAP_MODE 0xFFFFFFF3 6541 #define V_028A7C_VGT_DMA_SWAP_NONE 0x00 6542 #define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01 6543 #define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02 6544 #define V_028A7C_VGT_DMA_SWAP_WORD 0x03 6545 #define R_028A84_VGT_PRIMITIVEID_EN 0x028A84 6546 #define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0) 6547 #define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1) 6548 #define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE 6549 #define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1) 6550 #define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) 6551 #define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD 6552 #define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88 6553 #define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C 6554 #define R_028A90_VGT_EVENT_INITIATOR 0x028A90 6555 #define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0) 6556 #define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F) 6557 #define C_028A90_EVENT_TYPE 0xFFFFFFC0 6558 #define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01 6559 #define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02 6560 #define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03 6561 #define V_028A90_CACHE_FLUSH_TS 0x04 6562 #define V_028A90_CONTEXT_DONE 0x05 6563 #define V_028A90_CACHE_FLUSH 0x06 6564 #define V_028A90_CS_PARTIAL_FLUSH 0x07 6565 #define V_028A90_VGT_STREAMOUT_SYNC 0x08 6566 #define V_028A90_VGT_STREAMOUT_RESET 0x0A 6567 #define V_028A90_END_OF_PIPE_INCR_DE 0x0B 6568 #define V_028A90_END_OF_PIPE_IB_END 0x0C 6569 #define V_028A90_RST_PIX_CNT 0x0D 6570 #define V_028A90_VS_PARTIAL_FLUSH 0x0F 6571 #define V_028A90_PS_PARTIAL_FLUSH 0x10 6572 #define V_028A90_FLUSH_HS_OUTPUT 0x11 6573 #define V_028A90_FLUSH_LS_OUTPUT 0x12 6574 #define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 6575 #define V_028A90_ZPASS_DONE 0x15 6576 #define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16 6577 #define V_028A90_PERFCOUNTER_START 0x17 6578 #define V_028A90_PERFCOUNTER_STOP 0x18 6579 #define V_028A90_PIPELINESTAT_START 0x19 6580 #define V_028A90_PIPELINESTAT_STOP 0x1A 6581 #define V_028A90_PERFCOUNTER_SAMPLE 0x1B 6582 #define V_028A90_FLUSH_ES_OUTPUT 0x1C 6583 #define V_028A90_FLUSH_GS_OUTPUT 0x1D 6584 #define V_028A90_SAMPLE_PIPELINESTAT 0x1E 6585 #define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F 6586 #define V_028A90_SAMPLE_STREAMOUTSTATS 0x20 6587 #define V_028A90_RESET_VTX_CNT 0x21 6588 #define V_028A90_BLOCK_CONTEXT_DONE 0x22 6589 #define V_028A90_CS_CONTEXT_DONE 0x23 6590 #define V_028A90_VGT_FLUSH 0x24 6591 #define V_028A90_SC_SEND_DB_VPZ 0x27 6592 #define V_028A90_BOTTOM_OF_PIPE_TS 0x28 6593 #define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A 6594 #define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B 6595 #define V_028A90_FLUSH_AND_INV_DB_META 0x2C 6596 #define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D 6597 #define V_028A90_FLUSH_AND_INV_CB_META 0x2E 6598 #define V_028A90_CS_DONE 0x2F 6599 #define V_028A90_PS_DONE 0x30 6600 #define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31 6601 #define V_028A90_THREAD_TRACE_START 0x33 6602 #define V_028A90_THREAD_TRACE_STOP 0x34 6603 #define V_028A90_THREAD_TRACE_MARKER 0x35 6604 #define V_028A90_THREAD_TRACE_FLUSH 0x36 6605 #define V_028A90_THREAD_TRACE_FINISH 0x37 6606 #define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18) 6607 #define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF) 6608 #define C_028A90_ADDRESS_HI 0xF803FFFF 6609 #define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27) 6610 #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1) 6611 #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF 6612 #define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94 6613 #define S_028A94_RESET_EN(x) (((x) & 0x1) << 0) 6614 #define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1) 6615 #define C_028A94_RESET_EN 0xFFFFFFFE 6616 #define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0 6617 #define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4 6618 #define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8 6619 #define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0) 6620 #define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF) 6621 #define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000 6622 #define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16) 6623 #define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1) 6624 #define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF 6625 #define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17) 6626 #define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1) 6627 #define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF 6628 #define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18) 6629 #define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1) 6630 #define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF 6631 #define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19) 6632 #define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1) 6633 #define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF 6634 #define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC 6635 #define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 6636 #define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 6637 #define C_028AAC_ITEMSIZE 0xFFFF8000 6638 #define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0 6639 #define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 6640 #define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 6641 #define C_028AB0_ITEMSIZE 0xFFFF8000 6642 #define R_028AB4_VGT_REUSE_OFF 0x028AB4 6643 #define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0) 6644 #define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1) 6645 #define C_028AB4_REUSE_OFF 0xFFFFFFFE 6646 #define R_028AB8_VGT_VTX_CNT_EN 0x028AB8 6647 #define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0) 6648 #define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1) 6649 #define C_028AB8_VTX_CNT_EN 0xFFFFFFFE 6650 #define R_028ABC_DB_HTILE_SURFACE 0x028ABC 6651 #define S_028ABC_LINEAR(x) (((x) & 0x1) << 0) 6652 #define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1) 6653 #define C_028ABC_LINEAR 0xFFFFFFFE 6654 #define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1) 6655 #define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1) 6656 #define C_028ABC_FULL_CACHE 0xFFFFFFFD 6657 #define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2) 6658 #define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1) 6659 #define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB 6660 #define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3) 6661 #define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1) 6662 #define C_028ABC_PRELOAD 0xFFFFFFF7 6663 #define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4) 6664 #define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F) 6665 #define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F 6666 #define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10) 6667 #define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F) 6668 #define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF 6669 #define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16) 6670 #define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1) 6671 #define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF 6672 #define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0 6673 #define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0) 6674 #define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07) 6675 #define C_028AC0_COMPAREFUNC0 0xFFFFFFF8 6676 #define V_028AC0_REF_NEVER 0x00 6677 #define V_028AC0_REF_LESS 0x01 6678 #define V_028AC0_REF_EQUAL 0x02 6679 #define V_028AC0_REF_LEQUAL 0x03 6680 #define V_028AC0_REF_GREATER 0x04 6681 #define V_028AC0_REF_NOTEQUAL 0x05 6682 #define V_028AC0_REF_GEQUAL 0x06 6683 #define V_028AC0_REF_ALWAYS 0x07 6684 #define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4) 6685 #define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF) 6686 #define C_028AC0_COMPAREVALUE0 0xFFFFF00F 6687 #define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12) 6688 #define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF) 6689 #define C_028AC0_COMPAREMASK0 0xFFF00FFF 6690 #define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24) 6691 #define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1) 6692 #define C_028AC0_ENABLE0 0xFEFFFFFF 6693 #define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4 6694 #define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0) 6695 #define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07) 6696 #define C_028AC4_COMPAREFUNC1 0xFFFFFFF8 6697 #define V_028AC4_REF_NEVER 0x00 6698 #define V_028AC4_REF_LESS 0x01 6699 #define V_028AC4_REF_EQUAL 0x02 6700 #define V_028AC4_REF_LEQUAL 0x03 6701 #define V_028AC4_REF_GREATER 0x04 6702 #define V_028AC4_REF_NOTEQUAL 0x05 6703 #define V_028AC4_REF_GEQUAL 0x06 6704 #define V_028AC4_REF_ALWAYS 0x07 6705 #define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4) 6706 #define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF) 6707 #define C_028AC4_COMPAREVALUE1 0xFFFFF00F 6708 #define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12) 6709 #define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF) 6710 #define C_028AC4_COMPAREMASK1 0xFFF00FFF 6711 #define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24) 6712 #define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1) 6713 #define C_028AC4_ENABLE1 0xFEFFFFFF 6714 #define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8 6715 #define S_028AC8_START_X(x) (((x) & 0xFF) << 0) 6716 #define G_028AC8_START_X(x) (((x) >> 0) & 0xFF) 6717 #define C_028AC8_START_X 0xFFFFFF00 6718 #define S_028AC8_START_Y(x) (((x) & 0xFF) << 8) 6719 #define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF) 6720 #define C_028AC8_START_Y 0xFFFF00FF 6721 #define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16) 6722 #define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF) 6723 #define C_028AC8_MAX_X 0xFF00FFFF 6724 #define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24) 6725 #define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF) 6726 #define C_028AC8_MAX_Y 0x00FFFFFF 6727 #define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0 6728 #define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4 6729 #define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0) 6730 #define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF) 6731 #define C_028AD4_STRIDE 0xFFFFFC00 6732 #define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC 6733 #define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0 6734 #define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4 6735 #define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0) 6736 #define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF) 6737 #define C_028AE4_STRIDE 0xFFFFFC00 6738 #define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC 6739 #define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0 6740 #define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4 6741 #define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0) 6742 #define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF) 6743 #define C_028AF4_STRIDE 0xFFFFFC00 6744 #define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC 6745 #define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00 6746 #define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04 6747 #define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0) 6748 #define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF) 6749 #define C_028B04_STRIDE 0xFFFFFC00 6750 #define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C 6751 #define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28 6752 #define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C 6753 #define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30 6754 #define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0) 6755 #define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF) 6756 #define C_028B30_VERTEX_STRIDE 0xFFFFFE00 6757 #define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38 6758 #define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0) 6759 #define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF) 6760 #define C_028B38_MAX_VERT_OUT 0xFFFFF800 6761 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 6762 #define S_028B54_LS_EN(x) (((x) & 0x03) << 0) 6763 #define G_028B54_LS_EN(x) (((x) >> 0) & 0x03) 6764 #define C_028B54_LS_EN 0xFFFFFFFC 6765 #define V_028B54_LS_STAGE_OFF 0x00 6766 #define V_028B54_LS_STAGE_ON 0x01 6767 #define V_028B54_CS_STAGE_ON 0x02 6768 #define S_028B54_HS_EN(x) (((x) & 0x1) << 2) 6769 #define G_028B54_HS_EN(x) (((x) >> 2) & 0x1) 6770 #define C_028B54_HS_EN 0xFFFFFFFB 6771 #define S_028B54_ES_EN(x) (((x) & 0x03) << 3) 6772 #define G_028B54_ES_EN(x) (((x) >> 3) & 0x03) 6773 #define C_028B54_ES_EN 0xFFFFFFE7 6774 #define V_028B54_ES_STAGE_OFF 0x00 6775 #define V_028B54_ES_STAGE_DS 0x01 6776 #define V_028B54_ES_STAGE_REAL 0x02 6777 #define S_028B54_GS_EN(x) (((x) & 0x1) << 5) 6778 #define G_028B54_GS_EN(x) (((x) >> 5) & 0x1) 6779 #define C_028B54_GS_EN 0xFFFFFFDF 6780 #define S_028B54_VS_EN(x) (((x) & 0x03) << 6) 6781 #define G_028B54_VS_EN(x) (((x) >> 6) & 0x03) 6782 #define C_028B54_VS_EN 0xFFFFFF3F 6783 #define V_028B54_VS_STAGE_REAL 0x00 6784 #define V_028B54_VS_STAGE_DS 0x01 6785 #define V_028B54_VS_STAGE_COPY_SHADER 0x02 6786 #define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8) 6787 #define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1) 6788 #define C_028B54_DYNAMIC_HS 0xFFFFFEFF 6789 #define R_028B58_VGT_LS_HS_CONFIG 0x028B58 6790 #define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0) 6791 #define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF) 6792 #define C_028B58_NUM_PATCHES 0xFFFFFF00 6793 #define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8) 6794 #define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F) 6795 #define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF 6796 #define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14) 6797 #define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F) 6798 #define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF 6799 #define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C 6800 #define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 6801 #define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 6802 #define C_028B5C_ITEMSIZE 0xFFFF8000 6803 #define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60 6804 #define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 6805 #define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 6806 #define C_028B60_ITEMSIZE 0xFFFF8000 6807 #define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64 6808 #define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 6809 #define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 6810 #define C_028B64_ITEMSIZE 0xFFFF8000 6811 #define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68 6812 #define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 6813 #define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 6814 #define C_028B68_ITEMSIZE 0xFFFF8000 6815 #define R_028B6C_VGT_TF_PARAM 0x028B6C 6816 #define S_028B6C_TYPE(x) (((x) & 0x03) << 0) 6817 #define G_028B6C_TYPE(x) (((x) >> 0) & 0x03) 6818 #define C_028B6C_TYPE 0xFFFFFFFC 6819 #define V_028B6C_TESS_ISOLINE 0x00 6820 #define V_028B6C_TESS_TRIANGLE 0x01 6821 #define V_028B6C_TESS_QUAD 0x02 6822 #define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2) 6823 #define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07) 6824 #define C_028B6C_PARTITIONING 0xFFFFFFE3 6825 #define V_028B6C_PART_INTEGER 0x00 6826 #define V_028B6C_PART_POW2 0x01 6827 #define V_028B6C_PART_FRAC_ODD 0x02 6828 #define V_028B6C_PART_FRAC_EVEN 0x03 6829 #define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5) 6830 #define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07) 6831 #define C_028B6C_TOPOLOGY 0xFFFFFF1F 6832 #define V_028B6C_OUTPUT_POINT 0x00 6833 #define V_028B6C_OUTPUT_LINE 0x01 6834 #define V_028B6C_OUTPUT_TRIANGLE_CW 0x02 6835 #define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03 6836 #define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8) 6837 #define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1) 6838 #define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF 6839 #define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10) 6840 #define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F) 6841 #define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF 6842 #define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14) 6843 #define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1) 6844 #define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF 6845 #define R_028B70_DB_ALPHA_TO_MASK 0x028B70 6846 #define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0) 6847 #define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1) 6848 #define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE 6849 #define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8) 6850 #define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03) 6851 #define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF 6852 #define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10) 6853 #define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03) 6854 #define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF 6855 #define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12) 6856 #define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03) 6857 #define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF 6858 #define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14) 6859 #define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03) 6860 #define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF 6861 #define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16) 6862 #define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1) 6863 #define C_028B70_OFFSET_ROUND 0xFFFEFFFF 6864 #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78 6865 #define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0) 6866 #define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF) 6867 #define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00 6868 #define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8) 6869 #define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1) 6870 #define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF 6871 #define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C 6872 #define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80 6873 #define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84 6874 #define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88 6875 #define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C 6876 #define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90 6877 #define S_028B90_ENABLE(x) (((x) & 0x1) << 0) 6878 #define G_028B90_ENABLE(x) (((x) >> 0) & 0x1) 6879 #define C_028B90_ENABLE 0xFFFFFFFE 6880 #define S_028B90_CNT(x) (((x) & 0x7F) << 2) 6881 #define G_028B90_CNT(x) (((x) >> 2) & 0x7F) 6882 #define C_028B90_CNT 0xFFFFFE03 6883 #define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 6884 #define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0) 6885 #define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) 6886 #define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE 6887 #define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1) 6888 #define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) 6889 #define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD 6890 #define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2) 6891 #define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) 6892 #define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB 6893 #define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3) 6894 #define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) 6895 #define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 6896 #define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4) 6897 #define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) 6898 #define C_028B94_RAST_STREAM 0xFFFFFF8F 6899 #define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8) 6900 #define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) 6901 #define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF 6902 #define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31) 6903 #define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) 6904 #define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF 6905 #define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 6906 #define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0) 6907 #define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) 6908 #define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 6909 #define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4) 6910 #define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) 6911 #define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F 6912 #define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8) 6913 #define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) 6914 #define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF 6915 #define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12) 6916 #define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) 6917 #define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF 6918 #define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4 6919 #define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0) 6920 #define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F) 6921 #define C_028BD4_DISTANCE_0 0xFFFFFFF0 6922 #define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4) 6923 #define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F) 6924 #define C_028BD4_DISTANCE_1 0xFFFFFF0F 6925 #define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8) 6926 #define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F) 6927 #define C_028BD4_DISTANCE_2 0xFFFFF0FF 6928 #define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12) 6929 #define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F) 6930 #define C_028BD4_DISTANCE_3 0xFFFF0FFF 6931 #define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16) 6932 #define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F) 6933 #define C_028BD4_DISTANCE_4 0xFFF0FFFF 6934 #define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20) 6935 #define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F) 6936 #define C_028BD4_DISTANCE_5 0xFF0FFFFF 6937 #define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24) 6938 #define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F) 6939 #define C_028BD4_DISTANCE_6 0xF0FFFFFF 6940 #define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28) 6941 #define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F) 6942 #define C_028BD4_DISTANCE_7 0x0FFFFFFF 6943 #define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8 6944 #define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0) 6945 #define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F) 6946 #define C_028BD8_DISTANCE_8 0xFFFFFFF0 6947 #define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4) 6948 #define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F) 6949 #define C_028BD8_DISTANCE_9 0xFFFFFF0F 6950 #define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8) 6951 #define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F) 6952 #define C_028BD8_DISTANCE_10 0xFFFFF0FF 6953 #define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12) 6954 #define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F) 6955 #define C_028BD8_DISTANCE_11 0xFFFF0FFF 6956 #define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16) 6957 #define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F) 6958 #define C_028BD8_DISTANCE_12 0xFFF0FFFF 6959 #define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20) 6960 #define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F) 6961 #define C_028BD8_DISTANCE_13 0xFF0FFFFF 6962 #define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24) 6963 #define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F) 6964 #define C_028BD8_DISTANCE_14 0xF0FFFFFF 6965 #define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28) 6966 #define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F) 6967 #define C_028BD8_DISTANCE_15 0x0FFFFFFF 6968 #define R_028BDC_PA_SC_LINE_CNTL 0x028BDC 6969 #define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9) 6970 #define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) 6971 #define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF 6972 #define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10) 6973 #define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) 6974 #define C_028BDC_LAST_PIXEL 0xFFFFFBFF 6975 #define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11) 6976 #define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1) 6977 #define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF 6978 #define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12) 6979 #define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1) 6980 #define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF 6981 #define R_028BE0_PA_SC_AA_CONFIG 0x028BE0 6982 #define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x07) << 0) 6983 #define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07) 6984 #define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8 6985 #define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 6986 #define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 6987 #define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 6988 #define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0x0F) << 13) 6989 #define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F) 6990 #define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF 6991 #define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x07) << 20) 6992 #define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07) 6993 #define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF 6994 #define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x03) << 24) 6995 #define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03) 6996 #define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF 6997 #define R_028BE4_PA_SU_VTX_CNTL 0x028BE4 6998 #define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0) 6999 #define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1) 7000 #define C_028BE4_PIX_CENTER 0xFFFFFFFE 7001 #define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1) 7002 #define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03) 7003 #define C_028BE4_ROUND_MODE 0xFFFFFFF9 7004 #define V_028BE4_X_TRUNCATE 0x00 7005 #define V_028BE4_X_ROUND 0x01 7006 #define V_028BE4_X_ROUND_TO_EVEN 0x02 7007 #define V_028BE4_X_ROUND_TO_ODD 0x03 7008 #define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3) 7009 #define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07) 7010 #define C_028BE4_QUANT_MODE 0xFFFFFFC7 7011 #define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00 7012 #define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01 7013 #define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02 7014 #define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03 7015 #define V_028BE4_X_16_8_FIXED_POINT_1 0x04 7016 #define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05 7017 #define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06 7018 #define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07 7019 #define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8 7020 #define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC 7021 #define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0 7022 #define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4 7023 #define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8 7024 #define S_028BF8_S0_X(x) (((x) & 0x0F) << 0) 7025 #define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F) 7026 #define C_028BF8_S0_X 0xFFFFFFF0 7027 #define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4) 7028 #define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F) 7029 #define C_028BF8_S0_Y 0xFFFFFF0F 7030 #define S_028BF8_S1_X(x) (((x) & 0x0F) << 8) 7031 #define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F) 7032 #define C_028BF8_S1_X 0xFFFFF0FF 7033 #define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12) 7034 #define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F) 7035 #define C_028BF8_S1_Y 0xFFFF0FFF 7036 #define S_028BF8_S2_X(x) (((x) & 0x0F) << 16) 7037 #define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F) 7038 #define C_028BF8_S2_X 0xFFF0FFFF 7039 #define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20) 7040 #define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F) 7041 #define C_028BF8_S2_Y 0xFF0FFFFF 7042 #define S_028BF8_S3_X(x) (((x) & 0x0F) << 24) 7043 #define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F) 7044 #define C_028BF8_S3_X 0xF0FFFFFF 7045 #define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28) 7046 #define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F) 7047 #define C_028BF8_S3_Y 0x0FFFFFFF 7048 #define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC 7049 #define S_028BFC_S4_X(x) (((x) & 0x0F) << 0) 7050 #define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F) 7051 #define C_028BFC_S4_X 0xFFFFFFF0 7052 #define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4) 7053 #define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F) 7054 #define C_028BFC_S4_Y 0xFFFFFF0F 7055 #define S_028BFC_S5_X(x) (((x) & 0x0F) << 8) 7056 #define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F) 7057 #define C_028BFC_S5_X 0xFFFFF0FF 7058 #define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12) 7059 #define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F) 7060 #define C_028BFC_S5_Y 0xFFFF0FFF 7061 #define S_028BFC_S6_X(x) (((x) & 0x0F) << 16) 7062 #define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F) 7063 #define C_028BFC_S6_X 0xFFF0FFFF 7064 #define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20) 7065 #define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F) 7066 #define C_028BFC_S6_Y 0xFF0FFFFF 7067 #define S_028BFC_S7_X(x) (((x) & 0x0F) << 24) 7068 #define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F) 7069 #define C_028BFC_S7_X 0xF0FFFFFF 7070 #define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28) 7071 #define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F) 7072 #define C_028BFC_S7_Y 0x0FFFFFFF 7073 #define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00 7074 #define S_028C00_S8_X(x) (((x) & 0x0F) << 0) 7075 #define G_028C00_S8_X(x) (((x) >> 0) & 0x0F) 7076 #define C_028C00_S8_X 0xFFFFFFF0 7077 #define S_028C00_S8_Y(x) (((x) & 0x0F) << 4) 7078 #define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F) 7079 #define C_028C00_S8_Y 0xFFFFFF0F 7080 #define S_028C00_S9_X(x) (((x) & 0x0F) << 8) 7081 #define G_028C00_S9_X(x) (((x) >> 8) & 0x0F) 7082 #define C_028C00_S9_X 0xFFFFF0FF 7083 #define S_028C00_S9_Y(x) (((x) & 0x0F) << 12) 7084 #define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F) 7085 #define C_028C00_S9_Y 0xFFFF0FFF 7086 #define S_028C00_S10_X(x) (((x) & 0x0F) << 16) 7087 #define G_028C00_S10_X(x) (((x) >> 16) & 0x0F) 7088 #define C_028C00_S10_X 0xFFF0FFFF 7089 #define S_028C00_S10_Y(x) (((x) & 0x0F) << 20) 7090 #define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F) 7091 #define C_028C00_S10_Y 0xFF0FFFFF 7092 #define S_028C00_S11_X(x) (((x) & 0x0F) << 24) 7093 #define G_028C00_S11_X(x) (((x) >> 24) & 0x0F) 7094 #define C_028C00_S11_X 0xF0FFFFFF 7095 #define S_028C00_S11_Y(x) (((x) & 0x0F) << 28) 7096 #define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F) 7097 #define C_028C00_S11_Y 0x0FFFFFFF 7098 #define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04 7099 #define S_028C04_S12_X(x) (((x) & 0x0F) << 0) 7100 #define G_028C04_S12_X(x) (((x) >> 0) & 0x0F) 7101 #define C_028C04_S12_X 0xFFFFFFF0 7102 #define S_028C04_S12_Y(x) (((x) & 0x0F) << 4) 7103 #define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F) 7104 #define C_028C04_S12_Y 0xFFFFFF0F 7105 #define S_028C04_S13_X(x) (((x) & 0x0F) << 8) 7106 #define G_028C04_S13_X(x) (((x) >> 8) & 0x0F) 7107 #define C_028C04_S13_X 0xFFFFF0FF 7108 #define S_028C04_S13_Y(x) (((x) & 0x0F) << 12) 7109 #define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F) 7110 #define C_028C04_S13_Y 0xFFFF0FFF 7111 #define S_028C04_S14_X(x) (((x) & 0x0F) << 16) 7112 #define G_028C04_S14_X(x) (((x) >> 16) & 0x0F) 7113 #define C_028C04_S14_X 0xFFF0FFFF 7114 #define S_028C04_S14_Y(x) (((x) & 0x0F) << 20) 7115 #define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F) 7116 #define C_028C04_S14_Y 0xFF0FFFFF 7117 #define S_028C04_S15_X(x) (((x) & 0x0F) << 24) 7118 #define G_028C04_S15_X(x) (((x) >> 24) & 0x0F) 7119 #define C_028C04_S15_X 0xF0FFFFFF 7120 #define S_028C04_S15_Y(x) (((x) & 0x0F) << 28) 7121 #define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F) 7122 #define C_028C04_S15_Y 0x0FFFFFFF 7123 #define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08 7124 #define S_028C08_S0_X(x) (((x) & 0x0F) << 0) 7125 #define G_028C08_S0_X(x) (((x) >> 0) & 0x0F) 7126 #define C_028C08_S0_X 0xFFFFFFF0 7127 #define S_028C08_S0_Y(x) (((x) & 0x0F) << 4) 7128 #define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F) 7129 #define C_028C08_S0_Y 0xFFFFFF0F 7130 #define S_028C08_S1_X(x) (((x) & 0x0F) << 8) 7131 #define G_028C08_S1_X(x) (((x) >> 8) & 0x0F) 7132 #define C_028C08_S1_X 0xFFFFF0FF 7133 #define S_028C08_S1_Y(x) (((x) & 0x0F) << 12) 7134 #define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F) 7135 #define C_028C08_S1_Y 0xFFFF0FFF 7136 #define S_028C08_S2_X(x) (((x) & 0x0F) << 16) 7137 #define G_028C08_S2_X(x) (((x) >> 16) & 0x0F) 7138 #define C_028C08_S2_X 0xFFF0FFFF 7139 #define S_028C08_S2_Y(x) (((x) & 0x0F) << 20) 7140 #define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F) 7141 #define C_028C08_S2_Y 0xFF0FFFFF 7142 #define S_028C08_S3_X(x) (((x) & 0x0F) << 24) 7143 #define G_028C08_S3_X(x) (((x) >> 24) & 0x0F) 7144 #define C_028C08_S3_X 0xF0FFFFFF 7145 #define S_028C08_S3_Y(x) (((x) & 0x0F) << 28) 7146 #define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F) 7147 #define C_028C08_S3_Y 0x0FFFFFFF 7148 #define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C 7149 #define S_028C0C_S4_X(x) (((x) & 0x0F) << 0) 7150 #define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F) 7151 #define C_028C0C_S4_X 0xFFFFFFF0 7152 #define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4) 7153 #define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F) 7154 #define C_028C0C_S4_Y 0xFFFFFF0F 7155 #define S_028C0C_S5_X(x) (((x) & 0x0F) << 8) 7156 #define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F) 7157 #define C_028C0C_S5_X 0xFFFFF0FF 7158 #define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12) 7159 #define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F) 7160 #define C_028C0C_S5_Y 0xFFFF0FFF 7161 #define S_028C0C_S6_X(x) (((x) & 0x0F) << 16) 7162 #define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F) 7163 #define C_028C0C_S6_X 0xFFF0FFFF 7164 #define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20) 7165 #define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F) 7166 #define C_028C0C_S6_Y 0xFF0FFFFF 7167 #define S_028C0C_S7_X(x) (((x) & 0x0F) << 24) 7168 #define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F) 7169 #define C_028C0C_S7_X 0xF0FFFFFF 7170 #define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28) 7171 #define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F) 7172 #define C_028C0C_S7_Y 0x0FFFFFFF 7173 #define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10 7174 #define S_028C10_S8_X(x) (((x) & 0x0F) << 0) 7175 #define G_028C10_S8_X(x) (((x) >> 0) & 0x0F) 7176 #define C_028C10_S8_X 0xFFFFFFF0 7177 #define S_028C10_S8_Y(x) (((x) & 0x0F) << 4) 7178 #define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F) 7179 #define C_028C10_S8_Y 0xFFFFFF0F 7180 #define S_028C10_S9_X(x) (((x) & 0x0F) << 8) 7181 #define G_028C10_S9_X(x) (((x) >> 8) & 0x0F) 7182 #define C_028C10_S9_X 0xFFFFF0FF 7183 #define S_028C10_S9_Y(x) (((x) & 0x0F) << 12) 7184 #define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F) 7185 #define C_028C10_S9_Y 0xFFFF0FFF 7186 #define S_028C10_S10_X(x) (((x) & 0x0F) << 16) 7187 #define G_028C10_S10_X(x) (((x) >> 16) & 0x0F) 7188 #define C_028C10_S10_X 0xFFF0FFFF 7189 #define S_028C10_S10_Y(x) (((x) & 0x0F) << 20) 7190 #define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F) 7191 #define C_028C10_S10_Y 0xFF0FFFFF 7192 #define S_028C10_S11_X(x) (((x) & 0x0F) << 24) 7193 #define G_028C10_S11_X(x) (((x) >> 24) & 0x0F) 7194 #define C_028C10_S11_X 0xF0FFFFFF 7195 #define S_028C10_S11_Y(x) (((x) & 0x0F) << 28) 7196 #define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F) 7197 #define C_028C10_S11_Y 0x0FFFFFFF 7198 #define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14 7199 #define S_028C14_S12_X(x) (((x) & 0x0F) << 0) 7200 #define G_028C14_S12_X(x) (((x) >> 0) & 0x0F) 7201 #define C_028C14_S12_X 0xFFFFFFF0 7202 #define S_028C14_S12_Y(x) (((x) & 0x0F) << 4) 7203 #define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F) 7204 #define C_028C14_S12_Y 0xFFFFFF0F 7205 #define S_028C14_S13_X(x) (((x) & 0x0F) << 8) 7206 #define G_028C14_S13_X(x) (((x) >> 8) & 0x0F) 7207 #define C_028C14_S13_X 0xFFFFF0FF 7208 #define S_028C14_S13_Y(x) (((x) & 0x0F) << 12) 7209 #define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F) 7210 #define C_028C14_S13_Y 0xFFFF0FFF 7211 #define S_028C14_S14_X(x) (((x) & 0x0F) << 16) 7212 #define G_028C14_S14_X(x) (((x) >> 16) & 0x0F) 7213 #define C_028C14_S14_X 0xFFF0FFFF 7214 #define S_028C14_S14_Y(x) (((x) & 0x0F) << 20) 7215 #define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F) 7216 #define C_028C14_S14_Y 0xFF0FFFFF 7217 #define S_028C14_S15_X(x) (((x) & 0x0F) << 24) 7218 #define G_028C14_S15_X(x) (((x) >> 24) & 0x0F) 7219 #define C_028C14_S15_X 0xF0FFFFFF 7220 #define S_028C14_S15_Y(x) (((x) & 0x0F) << 28) 7221 #define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F) 7222 #define C_028C14_S15_Y 0x0FFFFFFF 7223 #define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18 7224 #define S_028C18_S0_X(x) (((x) & 0x0F) << 0) 7225 #define G_028C18_S0_X(x) (((x) >> 0) & 0x0F) 7226 #define C_028C18_S0_X 0xFFFFFFF0 7227 #define S_028C18_S0_Y(x) (((x) & 0x0F) << 4) 7228 #define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F) 7229 #define C_028C18_S0_Y 0xFFFFFF0F 7230 #define S_028C18_S1_X(x) (((x) & 0x0F) << 8) 7231 #define G_028C18_S1_X(x) (((x) >> 8) & 0x0F) 7232 #define C_028C18_S1_X 0xFFFFF0FF 7233 #define S_028C18_S1_Y(x) (((x) & 0x0F) << 12) 7234 #define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F) 7235 #define C_028C18_S1_Y 0xFFFF0FFF 7236 #define S_028C18_S2_X(x) (((x) & 0x0F) << 16) 7237 #define G_028C18_S2_X(x) (((x) >> 16) & 0x0F) 7238 #define C_028C18_S2_X 0xFFF0FFFF 7239 #define S_028C18_S2_Y(x) (((x) & 0x0F) << 20) 7240 #define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F) 7241 #define C_028C18_S2_Y 0xFF0FFFFF 7242 #define S_028C18_S3_X(x) (((x) & 0x0F) << 24) 7243 #define G_028C18_S3_X(x) (((x) >> 24) & 0x0F) 7244 #define C_028C18_S3_X 0xF0FFFFFF 7245 #define S_028C18_S3_Y(x) (((x) & 0x0F) << 28) 7246 #define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F) 7247 #define C_028C18_S3_Y 0x0FFFFFFF 7248 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C 7249 #define S_028C1C_S4_X(x) (((x) & 0x0F) << 0) 7250 #define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F) 7251 #define C_028C1C_S4_X 0xFFFFFFF0 7252 #define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4) 7253 #define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F) 7254 #define C_028C1C_S4_Y 0xFFFFFF0F 7255 #define S_028C1C_S5_X(x) (((x) & 0x0F) << 8) 7256 #define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F) 7257 #define C_028C1C_S5_X 0xFFFFF0FF 7258 #define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12) 7259 #define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F) 7260 #define C_028C1C_S5_Y 0xFFFF0FFF 7261 #define S_028C1C_S6_X(x) (((x) & 0x0F) << 16) 7262 #define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F) 7263 #define C_028C1C_S6_X 0xFFF0FFFF 7264 #define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20) 7265 #define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F) 7266 #define C_028C1C_S6_Y 0xFF0FFFFF 7267 #define S_028C1C_S7_X(x) (((x) & 0x0F) << 24) 7268 #define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F) 7269 #define C_028C1C_S7_X 0xF0FFFFFF 7270 #define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28) 7271 #define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F) 7272 #define C_028C1C_S7_Y 0x0FFFFFFF 7273 #define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20 7274 #define S_028C20_S8_X(x) (((x) & 0x0F) << 0) 7275 #define G_028C20_S8_X(x) (((x) >> 0) & 0x0F) 7276 #define C_028C20_S8_X 0xFFFFFFF0 7277 #define S_028C20_S8_Y(x) (((x) & 0x0F) << 4) 7278 #define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F) 7279 #define C_028C20_S8_Y 0xFFFFFF0F 7280 #define S_028C20_S9_X(x) (((x) & 0x0F) << 8) 7281 #define G_028C20_S9_X(x) (((x) >> 8) & 0x0F) 7282 #define C_028C20_S9_X 0xFFFFF0FF 7283 #define S_028C20_S9_Y(x) (((x) & 0x0F) << 12) 7284 #define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F) 7285 #define C_028C20_S9_Y 0xFFFF0FFF 7286 #define S_028C20_S10_X(x) (((x) & 0x0F) << 16) 7287 #define G_028C20_S10_X(x) (((x) >> 16) & 0x0F) 7288 #define C_028C20_S10_X 0xFFF0FFFF 7289 #define S_028C20_S10_Y(x) (((x) & 0x0F) << 20) 7290 #define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F) 7291 #define C_028C20_S10_Y 0xFF0FFFFF 7292 #define S_028C20_S11_X(x) (((x) & 0x0F) << 24) 7293 #define G_028C20_S11_X(x) (((x) >> 24) & 0x0F) 7294 #define C_028C20_S11_X 0xF0FFFFFF 7295 #define S_028C20_S11_Y(x) (((x) & 0x0F) << 28) 7296 #define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F) 7297 #define C_028C20_S11_Y 0x0FFFFFFF 7298 #define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24 7299 #define S_028C24_S12_X(x) (((x) & 0x0F) << 0) 7300 #define G_028C24_S12_X(x) (((x) >> 0) & 0x0F) 7301 #define C_028C24_S12_X 0xFFFFFFF0 7302 #define S_028C24_S12_Y(x) (((x) & 0x0F) << 4) 7303 #define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F) 7304 #define C_028C24_S12_Y 0xFFFFFF0F 7305 #define S_028C24_S13_X(x) (((x) & 0x0F) << 8) 7306 #define G_028C24_S13_X(x) (((x) >> 8) & 0x0F) 7307 #define C_028C24_S13_X 0xFFFFF0FF 7308 #define S_028C24_S13_Y(x) (((x) & 0x0F) << 12) 7309 #define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F) 7310 #define C_028C24_S13_Y 0xFFFF0FFF 7311 #define S_028C24_S14_X(x) (((x) & 0x0F) << 16) 7312 #define G_028C24_S14_X(x) (((x) >> 16) & 0x0F) 7313 #define C_028C24_S14_X 0xFFF0FFFF 7314 #define S_028C24_S14_Y(x) (((x) & 0x0F) << 20) 7315 #define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F) 7316 #define C_028C24_S14_Y 0xFF0FFFFF 7317 #define S_028C24_S15_X(x) (((x) & 0x0F) << 24) 7318 #define G_028C24_S15_X(x) (((x) >> 24) & 0x0F) 7319 #define C_028C24_S15_X 0xF0FFFFFF 7320 #define S_028C24_S15_Y(x) (((x) & 0x0F) << 28) 7321 #define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F) 7322 #define C_028C24_S15_Y 0x0FFFFFFF 7323 #define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28 7324 #define S_028C28_S0_X(x) (((x) & 0x0F) << 0) 7325 #define G_028C28_S0_X(x) (((x) >> 0) & 0x0F) 7326 #define C_028C28_S0_X 0xFFFFFFF0 7327 #define S_028C28_S0_Y(x) (((x) & 0x0F) << 4) 7328 #define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F) 7329 #define C_028C28_S0_Y 0xFFFFFF0F 7330 #define S_028C28_S1_X(x) (((x) & 0x0F) << 8) 7331 #define G_028C28_S1_X(x) (((x) >> 8) & 0x0F) 7332 #define C_028C28_S1_X 0xFFFFF0FF 7333 #define S_028C28_S1_Y(x) (((x) & 0x0F) << 12) 7334 #define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F) 7335 #define C_028C28_S1_Y 0xFFFF0FFF 7336 #define S_028C28_S2_X(x) (((x) & 0x0F) << 16) 7337 #define G_028C28_S2_X(x) (((x) >> 16) & 0x0F) 7338 #define C_028C28_S2_X 0xFFF0FFFF 7339 #define S_028C28_S2_Y(x) (((x) & 0x0F) << 20) 7340 #define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F) 7341 #define C_028C28_S2_Y 0xFF0FFFFF 7342 #define S_028C28_S3_X(x) (((x) & 0x0F) << 24) 7343 #define G_028C28_S3_X(x) (((x) >> 24) & 0x0F) 7344 #define C_028C28_S3_X 0xF0FFFFFF 7345 #define S_028C28_S3_Y(x) (((x) & 0x0F) << 28) 7346 #define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F) 7347 #define C_028C28_S3_Y 0x0FFFFFFF 7348 #define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C 7349 #define S_028C2C_S4_X(x) (((x) & 0x0F) << 0) 7350 #define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F) 7351 #define C_028C2C_S4_X 0xFFFFFFF0 7352 #define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4) 7353 #define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F) 7354 #define C_028C2C_S4_Y 0xFFFFFF0F 7355 #define S_028C2C_S5_X(x) (((x) & 0x0F) << 8) 7356 #define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F) 7357 #define C_028C2C_S5_X 0xFFFFF0FF 7358 #define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12) 7359 #define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F) 7360 #define C_028C2C_S5_Y 0xFFFF0FFF 7361 #define S_028C2C_S6_X(x) (((x) & 0x0F) << 16) 7362 #define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F) 7363 #define C_028C2C_S6_X 0xFFF0FFFF 7364 #define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20) 7365 #define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F) 7366 #define C_028C2C_S6_Y 0xFF0FFFFF 7367 #define S_028C2C_S7_X(x) (((x) & 0x0F) << 24) 7368 #define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F) 7369 #define C_028C2C_S7_X 0xF0FFFFFF 7370 #define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28) 7371 #define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F) 7372 #define C_028C2C_S7_Y 0x0FFFFFFF 7373 #define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30 7374 #define S_028C30_S8_X(x) (((x) & 0x0F) << 0) 7375 #define G_028C30_S8_X(x) (((x) >> 0) & 0x0F) 7376 #define C_028C30_S8_X 0xFFFFFFF0 7377 #define S_028C30_S8_Y(x) (((x) & 0x0F) << 4) 7378 #define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F) 7379 #define C_028C30_S8_Y 0xFFFFFF0F 7380 #define S_028C30_S9_X(x) (((x) & 0x0F) << 8) 7381 #define G_028C30_S9_X(x) (((x) >> 8) & 0x0F) 7382 #define C_028C30_S9_X 0xFFFFF0FF 7383 #define S_028C30_S9_Y(x) (((x) & 0x0F) << 12) 7384 #define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F) 7385 #define C_028C30_S9_Y 0xFFFF0FFF 7386 #define S_028C30_S10_X(x) (((x) & 0x0F) << 16) 7387 #define G_028C30_S10_X(x) (((x) >> 16) & 0x0F) 7388 #define C_028C30_S10_X 0xFFF0FFFF 7389 #define S_028C30_S10_Y(x) (((x) & 0x0F) << 20) 7390 #define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F) 7391 #define C_028C30_S10_Y 0xFF0FFFFF 7392 #define S_028C30_S11_X(x) (((x) & 0x0F) << 24) 7393 #define G_028C30_S11_X(x) (((x) >> 24) & 0x0F) 7394 #define C_028C30_S11_X 0xF0FFFFFF 7395 #define S_028C30_S11_Y(x) (((x) & 0x0F) << 28) 7396 #define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F) 7397 #define C_028C30_S11_Y 0x0FFFFFFF 7398 #define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34 7399 #define S_028C34_S12_X(x) (((x) & 0x0F) << 0) 7400 #define G_028C34_S12_X(x) (((x) >> 0) & 0x0F) 7401 #define C_028C34_S12_X 0xFFFFFFF0 7402 #define S_028C34_S12_Y(x) (((x) & 0x0F) << 4) 7403 #define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F) 7404 #define C_028C34_S12_Y 0xFFFFFF0F 7405 #define S_028C34_S13_X(x) (((x) & 0x0F) << 8) 7406 #define G_028C34_S13_X(x) (((x) >> 8) & 0x0F) 7407 #define C_028C34_S13_X 0xFFFFF0FF 7408 #define S_028C34_S13_Y(x) (((x) & 0x0F) << 12) 7409 #define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F) 7410 #define C_028C34_S13_Y 0xFFFF0FFF 7411 #define S_028C34_S14_X(x) (((x) & 0x0F) << 16) 7412 #define G_028C34_S14_X(x) (((x) >> 16) & 0x0F) 7413 #define C_028C34_S14_X 0xFFF0FFFF 7414 #define S_028C34_S14_Y(x) (((x) & 0x0F) << 20) 7415 #define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F) 7416 #define C_028C34_S14_Y 0xFF0FFFFF 7417 #define S_028C34_S15_X(x) (((x) & 0x0F) << 24) 7418 #define G_028C34_S15_X(x) (((x) >> 24) & 0x0F) 7419 #define C_028C34_S15_X 0xF0FFFFFF 7420 #define S_028C34_S15_Y(x) (((x) & 0x0F) << 28) 7421 #define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F) 7422 #define C_028C34_S15_Y 0x0FFFFFFF 7423 #define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38 7424 #define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0) 7425 #define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF) 7426 #define C_028C38_AA_MASK_X0Y0 0xFFFF0000 7427 #define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16) 7428 #define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF) 7429 #define C_028C38_AA_MASK_X1Y0 0x0000FFFF 7430 #define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C 7431 #define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0) 7432 #define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF) 7433 #define C_028C3C_AA_MASK_X0Y1 0xFFFF0000 7434 #define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16) 7435 #define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF) 7436 #define C_028C3C_AA_MASK_X1Y1 0x0000FFFF 7437 #define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58 7438 #define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0) 7439 #define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) 7440 #define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00 7441 #define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C 7442 #define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0) 7443 #define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F) 7444 #define C_028C5C_DEALLOC_DIST 0xFFFFFF80 7445 #define R_028C60_CB_COLOR0_BASE 0x028C60 7446 #define R_028C64_CB_COLOR0_PITCH 0x028C64 7447 #define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0) 7448 #define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF) 7449 #define C_028C64_TILE_MAX 0xFFFFF800 7450 #define R_028C68_CB_COLOR0_SLICE 0x028C68 7451 #define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 7452 #define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 7453 #define C_028C68_TILE_MAX 0xFFC00000 7454 #define R_028C6C_CB_COLOR0_VIEW 0x028C6C 7455 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 7456 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 7457 #define C_028C6C_SLICE_START 0xFFFFF800 7458 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 7459 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 7460 #define C_028C6C_SLICE_MAX 0xFF001FFF 7461 #define R_028C70_CB_COLOR0_INFO 0x028C70 7462 #define S_028C70_ENDIAN(x) (((x) & 0x03) << 0) 7463 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03) 7464 #define C_028C70_ENDIAN 0xFFFFFFFC 7465 #define V_028C70_ENDIAN_NONE 0x00 7466 #define V_028C70_ENDIAN_8IN16 0x01 7467 #define V_028C70_ENDIAN_8IN32 0x02 7468 #define V_028C70_ENDIAN_8IN64 0x03 7469 #define S_028C70_FORMAT(x) (((x) & 0x1F) << 2) 7470 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F) 7471 #define C_028C70_FORMAT 0xFFFFFF83 7472 #define V_028C70_COLOR_INVALID 0x00 7473 #define V_028C70_COLOR_8 0x01 7474 #define V_028C70_COLOR_16 0x02 7475 #define V_028C70_COLOR_8_8 0x03 7476 #define V_028C70_COLOR_32 0x04 7477 #define V_028C70_COLOR_16_16 0x05 7478 #define V_028C70_COLOR_10_11_11 0x06 7479 #define V_028C70_COLOR_11_11_10 0x07 7480 #define V_028C70_COLOR_10_10_10_2 0x08 7481 #define V_028C70_COLOR_2_10_10_10 0x09 7482 #define V_028C70_COLOR_8_8_8_8 0x0A 7483 #define V_028C70_COLOR_32_32 0x0B 7484 #define V_028C70_COLOR_16_16_16_16 0x0C 7485 #define V_028C70_COLOR_32_32_32_32 0x0E 7486 #define V_028C70_COLOR_5_6_5 0x10 7487 #define V_028C70_COLOR_1_5_5_5 0x11 7488 #define V_028C70_COLOR_5_5_5_1 0x12 7489 #define V_028C70_COLOR_4_4_4_4 0x13 7490 #define V_028C70_COLOR_8_24 0x14 7491 #define V_028C70_COLOR_24_8 0x15 7492 #define V_028C70_COLOR_X24_8_32_FLOAT 0x16 7493 #define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7) 7494 #define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1) 7495 #define C_028C70_LINEAR_GENERAL 0xFFFFFF7F 7496 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8) 7497 #define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07) 7498 #define C_028C70_NUMBER_TYPE 0xFFFFF8FF 7499 #define V_028C70_NUMBER_UNORM 0x00 7500 #define V_028C70_NUMBER_SNORM 0x01 7501 #define V_028C70_NUMBER_UINT 0x04 7502 #define V_028C70_NUMBER_SINT 0x05 7503 #define V_028C70_NUMBER_SRGB 0x06 7504 #define V_028C70_NUMBER_FLOAT 0x07 7505 #define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11) 7506 #define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03) 7507 #define C_028C70_COMP_SWAP 0xFFFFE7FF 7508 #define V_028C70_SWAP_STD 0x00 7509 #define V_028C70_SWAP_ALT 0x01 7510 #define V_028C70_SWAP_STD_REV 0x02 7511 #define V_028C70_SWAP_ALT_REV 0x03 7512 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13) 7513 #define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1) 7514 #define C_028C70_FAST_CLEAR 0xFFFFDFFF 7515 #define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14) 7516 #define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1) 7517 #define C_028C70_COMPRESSION 0xFFFFBFFF 7518 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15) 7519 #define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1) 7520 #define C_028C70_BLEND_CLAMP 0xFFFF7FFF 7521 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16) 7522 #define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1) 7523 #define C_028C70_BLEND_BYPASS 0xFFFEFFFF 7524 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17) 7525 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1) 7526 #define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF 7527 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18) 7528 #define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1) 7529 #define C_028C70_ROUND_MODE 0xFFFBFFFF 7530 #define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19) 7531 #define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1) 7532 #define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF 7533 #define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20) 7534 #define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07) 7535 #define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF 7536 #define V_028C70_FORCE_OPT_AUTO 0x00 7537 #define V_028C70_FORCE_OPT_DISABLE 0x01 7538 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 7539 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 7540 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 7541 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 7542 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 7543 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 7544 #define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23) 7545 #define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07) 7546 #define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF 7547 #define V_028C70_FORCE_OPT_AUTO 0x00 7548 #define V_028C70_FORCE_OPT_DISABLE 0x01 7549 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 7550 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 7551 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 7552 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 7553 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 7554 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 7555 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 7556 #define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0) 7557 #define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F) 7558 #define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0 7559 #define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5) 7560 #define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F) 7561 #define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F 7562 #define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12) 7563 #define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07) 7564 #define C_028C74_NUM_SAMPLES 0xFFFF8FFF 7565 #define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15) 7566 #define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03) 7567 #define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF 7568 #define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17) 7569 #define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1) 7570 #define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF 7571 #define R_028C7C_CB_COLOR0_CMASK 0x028C7C 7572 #define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80 7573 #define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0) 7574 #define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF) 7575 #define C_028C80_TILE_MAX 0xFFFFC000 7576 #define R_028C84_CB_COLOR0_FMASK 0x028C84 7577 #define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88 7578 #define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 7579 #define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 7580 #define C_028C88_TILE_MAX 0xFFC00000 7581 #define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C 7582 #define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90 7583 #define R_028C9C_CB_COLOR1_BASE 0x028C9C 7584 #define R_028CA0_CB_COLOR1_PITCH 0x028CA0 7585 #define R_028CA4_CB_COLOR1_SLICE 0x028CA4 7586 #define R_028CA8_CB_COLOR1_VIEW 0x028CA8 7587 #define R_028CAC_CB_COLOR1_INFO 0x028CAC 7588 #define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0 7589 #define R_028CD4_CB_COLOR1_CMASK 0x028CB8 7590 #define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC 7591 #define R_028CC0_CB_COLOR1_FMASK 0x028CC0 7592 #define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4 7593 #define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8 7594 #define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC 7595 #define R_028CD8_CB_COLOR2_BASE 0x028CD8 7596 #define R_028CDC_CB_COLOR2_PITCH 0x028CDC 7597 #define R_028CE0_CB_COLOR2_SLICE 0x028CE0 7598 #define R_028CE4_CB_COLOR2_VIEW 0x028CE4 7599 #define R_028CE8_CB_COLOR2_INFO 0x028CE8 7600 #define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC 7601 #define R_028CF4_CB_COLOR2_CMASK 0x028CF4 7602 #define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8 7603 #define R_028CFC_CB_COLOR2_FMASK 0x028CFC 7604 #define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00 7605 #define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04 7606 #define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08 7607 #define R_028D14_CB_COLOR3_BASE 0x028D14 7608 #define R_028D18_CB_COLOR3_PITCH 0x028D18 7609 #define R_028D1C_CB_COLOR3_SLICE 0x028D1C 7610 #define R_028D20_CB_COLOR3_VIEW 0x028D20 7611 #define R_028D24_CB_COLOR3_INFO 0x028D24 7612 #define R_028D28_CB_COLOR3_ATTRIB 0x028D28 7613 #define R_028D30_CB_COLOR3_CMASK 0x028D30 7614 #define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34 7615 #define R_028D38_CB_COLOR3_FMASK 0x028D38 7616 #define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C 7617 #define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40 7618 #define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44 7619 #define R_028D50_CB_COLOR4_BASE 0x028D50 7620 #define R_028D54_CB_COLOR4_PITCH 0x028D54 7621 #define R_028D58_CB_COLOR4_SLICE 0x028D58 7622 #define R_028D5C_CB_COLOR4_VIEW 0x028D5C 7623 #define R_028D60_CB_COLOR4_INFO 0x028D60 7624 #define R_028D64_CB_COLOR4_ATTRIB 0x028D64 7625 #define R_028D6C_CB_COLOR4_CMASK 0x028D6C 7626 #define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70 7627 #define R_028D74_CB_COLOR4_FMASK 0x028D74 7628 #define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78 7629 #define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C 7630 #define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80 7631 #define R_028D8C_CB_COLOR5_BASE 0x028D8C 7632 #define R_028D90_CB_COLOR5_PITCH 0x028D90 7633 #define R_028D94_CB_COLOR5_SLICE 0x028D94 7634 #define R_028D98_CB_COLOR5_VIEW 0x028D98 7635 #define R_028D9C_CB_COLOR5_INFO 0x028D9C 7636 #define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0 7637 #define R_028DA8_CB_COLOR5_CMASK 0x028DA8 7638 #define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC 7639 #define R_028DB0_CB_COLOR5_FMASK 0x028DB0 7640 #define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4 7641 #define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8 7642 #define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC 7643 #define R_028DC8_CB_COLOR6_BASE 0x028DC8 7644 #define R_028DCC_CB_COLOR6_PITCH 0x028DCC 7645 #define R_028DD0_CB_COLOR6_SLICE 0x028DD0 7646 #define R_028DD4_CB_COLOR6_VIEW 0x028DD4 7647 #define R_028DD8_CB_COLOR6_INFO 0x028DD8 7648 #define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC 7649 #define R_028DE4_CB_COLOR6_CMASK 0x028DE4 7650 #define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8 7651 #define R_028DEC_CB_COLOR6_FMASK 0x028DEC 7652 #define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0 7653 #define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4 7654 #define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8 7655 #define R_028E04_CB_COLOR7_BASE 0x028E04 7656 #define R_028E08_CB_COLOR7_PITCH 0x028E08 7657 #define R_028E0C_CB_COLOR7_SLICE 0x028E0C 7658 #define R_028E10_CB_COLOR7_VIEW 0x028E10 7659 #define R_028E14_CB_COLOR7_INFO 0x028E14 7660 #define R_028E18_CB_COLOR7_ATTRIB 0x028E18 7661 #define R_028E20_CB_COLOR7_CMASK 0x028E20 7662 #define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24 7663 #define R_028E28_CB_COLOR7_FMASK 0x028E28 7664 #define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C 7665 #define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30 7666 #define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34 7667 7668 #endif /* _SID_H */ 7669 7670
