1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // Documentation for the disassembler can be found in X86Disassembler.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86Disassembler.h" 18 #include "X86DisassemblerDecoder.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 using namespace llvm::X86Disassembler; 31 32 #define DEBUG_TYPE "x86-disassembler" 33 34 #define GET_REGINFO_ENUM 35 #include "X86GenRegisterInfo.inc" 36 #define GET_INSTRINFO_ENUM 37 #include "X86GenInstrInfo.inc" 38 #define GET_SUBTARGETINFO_ENUM 39 #include "X86GenSubtargetInfo.inc" 40 41 void llvm::X86Disassembler::Debug(const char *file, unsigned line, 42 const char *s) { 43 dbgs() << file << ":" << line << ": " << s; 44 } 45 46 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode, 47 const void *mii) { 48 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii); 49 return MII->getName(Opcode); 50 } 51 52 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s)); 53 54 namespace llvm { 55 56 // Fill-ins to make the compiler happy. These constants are never actually 57 // assigned; they are just filler to make an automatically-generated switch 58 // statement work. 59 namespace X86 { 60 enum { 61 BX_SI = 500, 62 BX_DI = 501, 63 BP_SI = 502, 64 BP_DI = 503, 65 sib = 504, 66 sib64 = 505 67 }; 68 } 69 70 extern Target TheX86_32Target, TheX86_64Target; 71 72 } 73 74 static bool translateInstruction(MCInst &target, 75 InternalInstruction &source, 76 const MCDisassembler *Dis); 77 78 X86GenericDisassembler::X86GenericDisassembler( 79 const MCSubtargetInfo &STI, 80 MCContext &Ctx, 81 std::unique_ptr<const MCInstrInfo> MII) 82 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 83 switch (STI.getFeatureBits() & 84 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) { 85 case X86::Mode16Bit: 86 fMode = MODE_16BIT; 87 break; 88 case X86::Mode32Bit: 89 fMode = MODE_32BIT; 90 break; 91 case X86::Mode64Bit: 92 fMode = MODE_64BIT; 93 break; 94 default: 95 llvm_unreachable("Invalid CPU mode"); 96 } 97 } 98 99 struct Region { 100 ArrayRef<uint8_t> Bytes; 101 uint64_t Base; 102 Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {} 103 }; 104 105 /// A callback function that wraps the readByte method from Region. 106 /// 107 /// @param Arg - The generic callback parameter. In this case, this should 108 /// be a pointer to a Region. 109 /// @param Byte - A pointer to the byte to be read. 110 /// @param Address - The address to be read. 111 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) { 112 auto *R = static_cast<const Region *>(Arg); 113 ArrayRef<uint8_t> Bytes = R->Bytes; 114 unsigned Index = Address - R->Base; 115 if (Bytes.size() <= Index) 116 return -1; 117 *Byte = Bytes[Index]; 118 return 0; 119 } 120 121 /// logger - a callback function that wraps the operator<< method from 122 /// raw_ostream. 123 /// 124 /// @param arg - The generic callback parameter. This should be a pointe 125 /// to a raw_ostream. 126 /// @param log - A string to be logged. logger() adds a newline. 127 static void logger(void* arg, const char* log) { 128 if (!arg) 129 return; 130 131 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 132 vStream << log << "\n"; 133 } 134 135 // 136 // Public interface for the disassembler 137 // 138 139 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( 140 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 141 raw_ostream &VStream, raw_ostream &CStream) const { 142 CommentStream = &CStream; 143 144 InternalInstruction InternalInstr; 145 146 dlog_t LoggerFn = logger; 147 if (&VStream == &nulls()) 148 LoggerFn = nullptr; // Disable logging completely if it's going to nulls(). 149 150 Region R(Bytes, Address); 151 152 int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R, 153 LoggerFn, (void *)&VStream, 154 (const void *)MII.get(), Address, fMode); 155 156 if (Ret) { 157 Size = InternalInstr.readerCursor - Address; 158 return Fail; 159 } else { 160 Size = InternalInstr.length; 161 return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail; 162 } 163 } 164 165 // 166 // Private code that translates from struct InternalInstructions to MCInsts. 167 // 168 169 /// translateRegister - Translates an internal register to the appropriate LLVM 170 /// register, and appends it as an operand to an MCInst. 171 /// 172 /// @param mcInst - The MCInst to append to. 173 /// @param reg - The Reg to append. 174 static void translateRegister(MCInst &mcInst, Reg reg) { 175 #define ENTRY(x) X86::x, 176 uint8_t llvmRegnums[] = { 177 ALL_REGS 178 0 179 }; 180 #undef ENTRY 181 182 uint8_t llvmRegnum = llvmRegnums[reg]; 183 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 184 } 185 186 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 187 /// immediate Value in the MCInst. 188 /// 189 /// @param Value - The immediate Value, has had any PC adjustment made by 190 /// the caller. 191 /// @param isBranch - If the instruction is a branch instruction 192 /// @param Address - The starting address of the instruction 193 /// @param Offset - The byte offset to this immediate in the instruction 194 /// @param Width - The byte width of this immediate in the instruction 195 /// 196 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was 197 /// called then that function is called to get any symbolic information for the 198 /// immediate in the instruction using the Address, Offset and Width. If that 199 /// returns non-zero then the symbolic information it returns is used to create 200 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() 201 /// returns zero and isBranch is true then a symbol look up for immediate Value 202 /// is done and if a symbol is found an MCExpr is created with that, else 203 /// an MCExpr with the immediate Value is created. This function returns true 204 /// if it adds an operand to the MCInst and false otherwise. 205 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 206 uint64_t Address, uint64_t Offset, 207 uint64_t Width, MCInst &MI, 208 const MCDisassembler *Dis) { 209 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 210 Offset, Width); 211 } 212 213 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 214 /// referenced by a load instruction with the base register that is the rip. 215 /// These can often be addresses in a literal pool. The Address of the 216 /// instruction and its immediate Value are used to determine the address 217 /// being referenced in the literal pool entry. The SymbolLookUp call back will 218 /// return a pointer to a literal 'C' string if the referenced address is an 219 /// address into a section with 'C' string literals. 220 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, 221 const void *Decoder) { 222 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 223 Dis->tryAddingPcLoadReferenceComment(Value, Address); 224 } 225 226 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 227 0, // SEG_OVERRIDE_NONE 228 X86::CS, 229 X86::SS, 230 X86::DS, 231 X86::ES, 232 X86::FS, 233 X86::GS 234 }; 235 236 /// translateSrcIndex - Appends a source index operand to an MCInst. 237 /// 238 /// @param mcInst - The MCInst to append to. 239 /// @param insn - The internal instruction. 240 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { 241 unsigned baseRegNo; 242 243 if (insn.mode == MODE_64BIT) 244 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI; 245 else if (insn.mode == MODE_32BIT) 246 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI; 247 else { 248 assert(insn.mode == MODE_16BIT); 249 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI; 250 } 251 MCOperand baseReg = MCOperand::CreateReg(baseRegNo); 252 mcInst.addOperand(baseReg); 253 254 MCOperand segmentReg; 255 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); 256 mcInst.addOperand(segmentReg); 257 return false; 258 } 259 260 /// translateDstIndex - Appends a destination index operand to an MCInst. 261 /// 262 /// @param mcInst - The MCInst to append to. 263 /// @param insn - The internal instruction. 264 265 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { 266 unsigned baseRegNo; 267 268 if (insn.mode == MODE_64BIT) 269 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI; 270 else if (insn.mode == MODE_32BIT) 271 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI; 272 else { 273 assert(insn.mode == MODE_16BIT); 274 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI; 275 } 276 MCOperand baseReg = MCOperand::CreateReg(baseRegNo); 277 mcInst.addOperand(baseReg); 278 return false; 279 } 280 281 /// translateImmediate - Appends an immediate operand to an MCInst. 282 /// 283 /// @param mcInst - The MCInst to append to. 284 /// @param immediate - The immediate value to append. 285 /// @param operand - The operand, as stored in the descriptor table. 286 /// @param insn - The internal instruction. 287 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 288 const OperandSpecifier &operand, 289 InternalInstruction &insn, 290 const MCDisassembler *Dis) { 291 // Sign-extend the immediate if necessary. 292 293 OperandType type = (OperandType)operand.type; 294 295 bool isBranch = false; 296 uint64_t pcrel = 0; 297 if (type == TYPE_RELv) { 298 isBranch = true; 299 pcrel = insn.startLocation + 300 insn.immediateOffset + insn.immediateSize; 301 switch (insn.displacementSize) { 302 default: 303 break; 304 case 1: 305 if(immediate & 0x80) 306 immediate |= ~(0xffull); 307 break; 308 case 2: 309 if(immediate & 0x8000) 310 immediate |= ~(0xffffull); 311 break; 312 case 4: 313 if(immediate & 0x80000000) 314 immediate |= ~(0xffffffffull); 315 break; 316 case 8: 317 break; 318 } 319 } 320 // By default sign-extend all X86 immediates based on their encoding. 321 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || 322 type == TYPE_IMM64 || type == TYPE_IMMv) { 323 switch (operand.encoding) { 324 default: 325 break; 326 case ENCODING_IB: 327 if(immediate & 0x80) 328 immediate |= ~(0xffull); 329 break; 330 case ENCODING_IW: 331 if(immediate & 0x8000) 332 immediate |= ~(0xffffull); 333 break; 334 case ENCODING_ID: 335 if(immediate & 0x80000000) 336 immediate |= ~(0xffffffffull); 337 break; 338 case ENCODING_IO: 339 break; 340 } 341 } else if (type == TYPE_IMM3) { 342 // Check for immediates that printSSECC can't handle. 343 if (immediate >= 8) { 344 unsigned NewOpc; 345 switch (mcInst.getOpcode()) { 346 default: llvm_unreachable("unexpected opcode"); 347 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; 348 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; 349 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; 350 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; 351 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; 352 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; 353 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; 354 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; 355 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; 356 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break; 357 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break; 358 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break; 359 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break; 360 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break; 361 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break; 362 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break; 363 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break; 364 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break; 365 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break; 366 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break; 367 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break; 368 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break; 369 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break; 370 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break; 371 } 372 // Switch opcode to the one that doesn't get special printing. 373 mcInst.setOpcode(NewOpc); 374 } 375 } else if (type == TYPE_IMM5) { 376 // Check for immediates that printAVXCC can't handle. 377 if (immediate >= 32) { 378 unsigned NewOpc; 379 switch (mcInst.getOpcode()) { 380 default: llvm_unreachable("unexpected opcode"); 381 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break; 382 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break; 383 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break; 384 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break; 385 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break; 386 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break; 387 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break; 388 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break; 389 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break; 390 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break; 391 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break; 392 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break; 393 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break; 394 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break; 395 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break; 396 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break; 397 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break; 398 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break; 399 case X86::VCMPSDZrm: NewOpc = X86::VCMPSDZrmi_alt; break; 400 case X86::VCMPSDZrr: NewOpc = X86::VCMPSDZrri_alt; break; 401 case X86::VCMPSSZrm: NewOpc = X86::VCMPSSZrmi_alt; break; 402 case X86::VCMPSSZrr: NewOpc = X86::VCMPSSZrri_alt; break; 403 } 404 // Switch opcode to the one that doesn't get special printing. 405 mcInst.setOpcode(NewOpc); 406 } 407 } else if (type == TYPE_AVX512ICC) { 408 if (immediate >= 8 || ((immediate & 0x3) == 3)) { 409 unsigned NewOpc; 410 switch (mcInst.getOpcode()) { 411 default: llvm_unreachable("unexpected opcode"); 412 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break; 413 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break; 414 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break; 415 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break; 416 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break; 417 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break; 418 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break; 419 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break; 420 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break; 421 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break; 422 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break; 423 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break; 424 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break; 425 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break; 426 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break; 427 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break; 428 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break; 429 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break; 430 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break; 431 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break; 432 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break; 433 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break; 434 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break; 435 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break; 436 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break; 437 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break; 438 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break; 439 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break; 440 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break; 441 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break; 442 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break; 443 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break; 444 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break; 445 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break; 446 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break; 447 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break; 448 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break; 449 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break; 450 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break; 451 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break; 452 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break; 453 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break; 454 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break; 455 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break; 456 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break; 457 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break; 458 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break; 459 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break; 460 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break; 461 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break; 462 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break; 463 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break; 464 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break; 465 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break; 466 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break; 467 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break; 468 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break; 469 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break; 470 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break; 471 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break; 472 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break; 473 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break; 474 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break; 475 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break; 476 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break; 477 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break; 478 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break; 479 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break; 480 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break; 481 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break; 482 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break; 483 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break; 484 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break; 485 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break; 486 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break; 487 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break; 488 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break; 489 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break; 490 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break; 491 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break; 492 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break; 493 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break; 494 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break; 495 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break; 496 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break; 497 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break; 498 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break; 499 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break; 500 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break; 501 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break; 502 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break; 503 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break; 504 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break; 505 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break; 506 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break; 507 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break; 508 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break; 509 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break; 510 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break; 511 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break; 512 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break; 513 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break; 514 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break; 515 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break; 516 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break; 517 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break; 518 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break; 519 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break; 520 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break; 521 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break; 522 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break; 523 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break; 524 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break; 525 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break; 526 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break; 527 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break; 528 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break; 529 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break; 530 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break; 531 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break; 532 } 533 // Switch opcode to the one that doesn't get special printing. 534 mcInst.setOpcode(NewOpc); 535 } 536 } 537 538 switch (type) { 539 case TYPE_XMM32: 540 case TYPE_XMM64: 541 case TYPE_XMM128: 542 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 543 return; 544 case TYPE_XMM256: 545 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 546 return; 547 case TYPE_XMM512: 548 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4))); 549 return; 550 case TYPE_REL8: 551 isBranch = true; 552 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 553 if(immediate & 0x80) 554 immediate |= ~(0xffull); 555 break; 556 case TYPE_REL32: 557 case TYPE_REL64: 558 isBranch = true; 559 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 560 if(immediate & 0x80000000) 561 immediate |= ~(0xffffffffull); 562 break; 563 default: 564 // operand is 64 bits wide. Do nothing. 565 break; 566 } 567 568 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, 569 insn.immediateOffset, insn.immediateSize, 570 mcInst, Dis)) 571 mcInst.addOperand(MCOperand::CreateImm(immediate)); 572 573 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || 574 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { 575 MCOperand segmentReg; 576 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); 577 mcInst.addOperand(segmentReg); 578 } 579 } 580 581 /// translateRMRegister - Translates a register stored in the R/M field of the 582 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 583 /// @param mcInst - The MCInst to append to. 584 /// @param insn - The internal instruction to extract the R/M field 585 /// from. 586 /// @return - 0 on success; -1 otherwise 587 static bool translateRMRegister(MCInst &mcInst, 588 InternalInstruction &insn) { 589 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 590 debug("A R/M register operand may not have a SIB byte"); 591 return true; 592 } 593 594 switch (insn.eaBase) { 595 default: 596 debug("Unexpected EA base register"); 597 return true; 598 case EA_BASE_NONE: 599 debug("EA_BASE_NONE for ModR/M base"); 600 return true; 601 #define ENTRY(x) case EA_BASE_##x: 602 ALL_EA_BASES 603 #undef ENTRY 604 debug("A R/M register operand may not have a base; " 605 "the operand must be a register."); 606 return true; 607 #define ENTRY(x) \ 608 case EA_REG_##x: \ 609 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 610 ALL_REGS 611 #undef ENTRY 612 } 613 614 return false; 615 } 616 617 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 618 /// fields of an internal instruction (and possibly its SIB byte) to a memory 619 /// operand in LLVM's format, and appends it to an MCInst. 620 /// 621 /// @param mcInst - The MCInst to append to. 622 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 623 /// from. 624 /// @return - 0 on success; nonzero otherwise 625 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 626 const MCDisassembler *Dis) { 627 // Addresses in an MCInst are represented as five operands: 628 // 1. basereg (register) The R/M base, or (if there is a SIB) the 629 // SIB base 630 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 631 // scale amount 632 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 633 // the index (which is multiplied by the 634 // scale amount) 635 // 4. displacement (immediate) 0, or the displacement if there is one 636 // 5. segmentreg (register) x86_registerNONE for now, but could be set 637 // if we have segment overrides 638 639 MCOperand baseReg; 640 MCOperand scaleAmount; 641 MCOperand indexReg; 642 MCOperand displacement; 643 MCOperand segmentReg; 644 uint64_t pcrel = 0; 645 646 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 647 if (insn.sibBase != SIB_BASE_NONE) { 648 switch (insn.sibBase) { 649 default: 650 debug("Unexpected sibBase"); 651 return true; 652 #define ENTRY(x) \ 653 case SIB_BASE_##x: \ 654 baseReg = MCOperand::CreateReg(X86::x); break; 655 ALL_SIB_BASES 656 #undef ENTRY 657 } 658 } else { 659 baseReg = MCOperand::CreateReg(0); 660 } 661 662 // Check whether we are handling VSIB addressing mode for GATHER. 663 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and 664 // we should use SIB_INDEX_XMM4|YMM4 for VSIB. 665 // I don't see a way to get the correct IndexReg in readSIB: 666 // We can tell whether it is VSIB or SIB after instruction ID is decoded, 667 // but instruction ID may not be decoded yet when calling readSIB. 668 uint32_t Opcode = mcInst.getOpcode(); 669 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm || 670 Opcode == X86::VGATHERDPDYrm || 671 Opcode == X86::VGATHERQPDrm || 672 Opcode == X86::VGATHERDPSrm || 673 Opcode == X86::VGATHERQPSrm || 674 Opcode == X86::VPGATHERDQrm || 675 Opcode == X86::VPGATHERDQYrm || 676 Opcode == X86::VPGATHERQQrm || 677 Opcode == X86::VPGATHERDDrm || 678 Opcode == X86::VPGATHERQDrm); 679 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm || 680 Opcode == X86::VGATHERDPSYrm || 681 Opcode == X86::VGATHERQPSYrm || 682 Opcode == X86::VGATHERDPDZrm || 683 Opcode == X86::VPGATHERDQZrm || 684 Opcode == X86::VPGATHERQQYrm || 685 Opcode == X86::VPGATHERDDYrm || 686 Opcode == X86::VPGATHERQDYrm); 687 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm || 688 Opcode == X86::VGATHERDPSZrm || 689 Opcode == X86::VGATHERQPSZrm || 690 Opcode == X86::VPGATHERQQZrm || 691 Opcode == X86::VPGATHERDDZrm || 692 Opcode == X86::VPGATHERQDZrm); 693 if (IndexIs128 || IndexIs256 || IndexIs512) { 694 unsigned IndexOffset = insn.sibIndex - 695 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); 696 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 : 697 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0; 698 insn.sibIndex = (SIBIndex)(IndexBase + 699 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset)); 700 } 701 702 if (insn.sibIndex != SIB_INDEX_NONE) { 703 switch (insn.sibIndex) { 704 default: 705 debug("Unexpected sibIndex"); 706 return true; 707 #define ENTRY(x) \ 708 case SIB_INDEX_##x: \ 709 indexReg = MCOperand::CreateReg(X86::x); break; 710 EA_BASES_32BIT 711 EA_BASES_64BIT 712 REGS_XMM 713 REGS_YMM 714 REGS_ZMM 715 #undef ENTRY 716 } 717 } else { 718 indexReg = MCOperand::CreateReg(0); 719 } 720 721 scaleAmount = MCOperand::CreateImm(insn.sibScale); 722 } else { 723 switch (insn.eaBase) { 724 case EA_BASE_NONE: 725 if (insn.eaDisplacement == EA_DISP_NONE) { 726 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 727 return true; 728 } 729 if (insn.mode == MODE_64BIT){ 730 pcrel = insn.startLocation + 731 insn.displacementOffset + insn.displacementSize; 732 tryAddingPcLoadReferenceComment(insn.startLocation + 733 insn.displacementOffset, 734 insn.displacement + pcrel, Dis); 735 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 736 } 737 else 738 baseReg = MCOperand::CreateReg(0); 739 740 indexReg = MCOperand::CreateReg(0); 741 break; 742 case EA_BASE_BX_SI: 743 baseReg = MCOperand::CreateReg(X86::BX); 744 indexReg = MCOperand::CreateReg(X86::SI); 745 break; 746 case EA_BASE_BX_DI: 747 baseReg = MCOperand::CreateReg(X86::BX); 748 indexReg = MCOperand::CreateReg(X86::DI); 749 break; 750 case EA_BASE_BP_SI: 751 baseReg = MCOperand::CreateReg(X86::BP); 752 indexReg = MCOperand::CreateReg(X86::SI); 753 break; 754 case EA_BASE_BP_DI: 755 baseReg = MCOperand::CreateReg(X86::BP); 756 indexReg = MCOperand::CreateReg(X86::DI); 757 break; 758 default: 759 indexReg = MCOperand::CreateReg(0); 760 switch (insn.eaBase) { 761 default: 762 debug("Unexpected eaBase"); 763 return true; 764 // Here, we will use the fill-ins defined above. However, 765 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 766 // sib and sib64 were handled in the top-level if, so they're only 767 // placeholders to keep the compiler happy. 768 #define ENTRY(x) \ 769 case EA_BASE_##x: \ 770 baseReg = MCOperand::CreateReg(X86::x); break; 771 ALL_EA_BASES 772 #undef ENTRY 773 #define ENTRY(x) case EA_REG_##x: 774 ALL_REGS 775 #undef ENTRY 776 debug("A R/M memory operand may not be a register; " 777 "the base field must be a base."); 778 return true; 779 } 780 } 781 782 scaleAmount = MCOperand::CreateImm(1); 783 } 784 785 displacement = MCOperand::CreateImm(insn.displacement); 786 787 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); 788 789 mcInst.addOperand(baseReg); 790 mcInst.addOperand(scaleAmount); 791 mcInst.addOperand(indexReg); 792 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false, 793 insn.startLocation, insn.displacementOffset, 794 insn.displacementSize, mcInst, Dis)) 795 mcInst.addOperand(displacement); 796 mcInst.addOperand(segmentReg); 797 return false; 798 } 799 800 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 801 /// byte of an instruction to LLVM form, and appends it to an MCInst. 802 /// 803 /// @param mcInst - The MCInst to append to. 804 /// @param operand - The operand, as stored in the descriptor table. 805 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 806 /// from. 807 /// @return - 0 on success; nonzero otherwise 808 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 809 InternalInstruction &insn, const MCDisassembler *Dis) { 810 switch (operand.type) { 811 default: 812 debug("Unexpected type for a R/M operand"); 813 return true; 814 case TYPE_R8: 815 case TYPE_R16: 816 case TYPE_R32: 817 case TYPE_R64: 818 case TYPE_Rv: 819 case TYPE_MM64: 820 case TYPE_XMM: 821 case TYPE_XMM32: 822 case TYPE_XMM64: 823 case TYPE_XMM128: 824 case TYPE_XMM256: 825 case TYPE_XMM512: 826 case TYPE_VK1: 827 case TYPE_VK8: 828 case TYPE_VK16: 829 case TYPE_DEBUGREG: 830 case TYPE_CONTROLREG: 831 return translateRMRegister(mcInst, insn); 832 case TYPE_M: 833 case TYPE_M8: 834 case TYPE_M16: 835 case TYPE_M32: 836 case TYPE_M64: 837 case TYPE_M128: 838 case TYPE_M256: 839 case TYPE_M512: 840 case TYPE_Mv: 841 case TYPE_M32FP: 842 case TYPE_M64FP: 843 case TYPE_M80FP: 844 case TYPE_M1616: 845 case TYPE_M1632: 846 case TYPE_M1664: 847 case TYPE_LEA: 848 return translateRMMemory(mcInst, insn, Dis); 849 } 850 } 851 852 /// translateFPRegister - Translates a stack position on the FPU stack to its 853 /// LLVM form, and appends it to an MCInst. 854 /// 855 /// @param mcInst - The MCInst to append to. 856 /// @param stackPos - The stack position to translate. 857 static void translateFPRegister(MCInst &mcInst, 858 uint8_t stackPos) { 859 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos)); 860 } 861 862 /// translateMaskRegister - Translates a 3-bit mask register number to 863 /// LLVM form, and appends it to an MCInst. 864 /// 865 /// @param mcInst - The MCInst to append to. 866 /// @param maskRegNum - Number of mask register from 0 to 7. 867 /// @return - false on success; true otherwise. 868 static bool translateMaskRegister(MCInst &mcInst, 869 uint8_t maskRegNum) { 870 if (maskRegNum >= 8) { 871 debug("Invalid mask register number"); 872 return true; 873 } 874 875 mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum)); 876 return false; 877 } 878 879 /// translateOperand - Translates an operand stored in an internal instruction 880 /// to LLVM's format and appends it to an MCInst. 881 /// 882 /// @param mcInst - The MCInst to append to. 883 /// @param operand - The operand, as stored in the descriptor table. 884 /// @param insn - The internal instruction. 885 /// @return - false on success; true otherwise. 886 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 887 InternalInstruction &insn, 888 const MCDisassembler *Dis) { 889 switch (operand.encoding) { 890 default: 891 debug("Unhandled operand encoding during translation"); 892 return true; 893 case ENCODING_REG: 894 translateRegister(mcInst, insn.reg); 895 return false; 896 case ENCODING_WRITEMASK: 897 return translateMaskRegister(mcInst, insn.writemask); 898 CASE_ENCODING_RM: 899 return translateRM(mcInst, operand, insn, Dis); 900 case ENCODING_CB: 901 case ENCODING_CW: 902 case ENCODING_CD: 903 case ENCODING_CP: 904 case ENCODING_CO: 905 case ENCODING_CT: 906 debug("Translation of code offsets isn't supported."); 907 return true; 908 case ENCODING_IB: 909 case ENCODING_IW: 910 case ENCODING_ID: 911 case ENCODING_IO: 912 case ENCODING_Iv: 913 case ENCODING_Ia: 914 translateImmediate(mcInst, 915 insn.immediates[insn.numImmediatesTranslated++], 916 operand, 917 insn, 918 Dis); 919 return false; 920 case ENCODING_SI: 921 return translateSrcIndex(mcInst, insn); 922 case ENCODING_DI: 923 return translateDstIndex(mcInst, insn); 924 case ENCODING_RB: 925 case ENCODING_RW: 926 case ENCODING_RD: 927 case ENCODING_RO: 928 case ENCODING_Rv: 929 translateRegister(mcInst, insn.opcodeRegister); 930 return false; 931 case ENCODING_FP: 932 translateFPRegister(mcInst, insn.modRM & 7); 933 return false; 934 case ENCODING_VVVV: 935 translateRegister(mcInst, insn.vvvv); 936 return false; 937 case ENCODING_DUP: 938 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], 939 insn, Dis); 940 } 941 } 942 943 /// translateInstruction - Translates an internal instruction and all its 944 /// operands to an MCInst. 945 /// 946 /// @param mcInst - The MCInst to populate with the instruction's data. 947 /// @param insn - The internal instruction. 948 /// @return - false on success; true otherwise. 949 static bool translateInstruction(MCInst &mcInst, 950 InternalInstruction &insn, 951 const MCDisassembler *Dis) { 952 if (!insn.spec) { 953 debug("Instruction has no specification"); 954 return true; 955 } 956 957 mcInst.setOpcode(insn.instructionID); 958 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 959 // prefix bytes should be disassembled as xrelease and xacquire then set the 960 // opcode to those instead of the rep and repne opcodes. 961 if (insn.xAcquireRelease) { 962 if(mcInst.getOpcode() == X86::REP_PREFIX) 963 mcInst.setOpcode(X86::XRELEASE_PREFIX); 964 else if(mcInst.getOpcode() == X86::REPNE_PREFIX) 965 mcInst.setOpcode(X86::XACQUIRE_PREFIX); 966 } 967 968 insn.numImmediatesTranslated = 0; 969 970 for (const auto &Op : insn.operands) { 971 if (Op.encoding != ENCODING_NONE) { 972 if (translateOperand(mcInst, Op, insn, Dis)) { 973 return true; 974 } 975 } 976 } 977 978 return false; 979 } 980 981 static MCDisassembler *createX86Disassembler(const Target &T, 982 const MCSubtargetInfo &STI, 983 MCContext &Ctx) { 984 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); 985 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII)); 986 } 987 988 extern "C" void LLVMInitializeX86Disassembler() { 989 // Register the disassembler. 990 TargetRegistry::RegisterMCDisassembler(TheX86_32Target, 991 createX86Disassembler); 992 TargetRegistry::RegisterMCDisassembler(TheX86_64Target, 993 createX86Disassembler); 994 } 995
