Home | History | Annotate | Download | only in AArch64 
      1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 // When allowed by the instruction, replace a dead definition of a GPR with
     10 // the zero register. This makes the code a bit friendlier towards the
     11 // hardware's register renamer.
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "AArch64.h"
     15 #include "AArch64RegisterInfo.h"
     16 #include "llvm/ADT/Statistic.h"
     17 #include "llvm/CodeGen/MachineFunction.h"
     18 #include "llvm/CodeGen/MachineFunctionPass.h"
     19 #include "llvm/CodeGen/MachineInstr.h"
     20 #include "llvm/Support/Debug.h"
     21 #include "llvm/Support/raw_ostream.h"
     22 #include "llvm/Target/TargetSubtargetInfo.h"
     23 using namespace llvm;
     24 
     25 #define DEBUG_TYPE "aarch64-dead-defs"
     26 
     27 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
     28 
     29 namespace {
     30 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
     31 private:
     32   const TargetRegisterInfo *TRI;
     33   bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
     34   bool processMachineBasicBlock(MachineBasicBlock &MBB);
     35   bool usesFrameIndex(const MachineInstr &MI);
     36 public:
     37   static char ID; // Pass identification, replacement for typeid.
     38   explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
     39 
     40   bool runOnMachineFunction(MachineFunction &F) override;
     41 
     42   const char *getPassName() const override { return "Dead register definitions"; }
     43 
     44   void getAnalysisUsage(AnalysisUsage &AU) const override {
     45     AU.setPreservesCFG();
     46     MachineFunctionPass::getAnalysisUsage(AU);
     47   }
     48 };
     49 char AArch64DeadRegisterDefinitions::ID = 0;
     50 } // end anonymous namespace
     51 
     52 bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
     53     unsigned Reg, const MachineInstr &MI) {
     54   for (const MachineOperand &MO : MI.implicit_operands())
     55     if (MO.isReg() && MO.isDef())
     56       if (TRI->regsOverlap(Reg, MO.getReg()))
     57         return true;
     58   return false;
     59 }
     60 
     61 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
     62   for (const MachineOperand &Op : MI.uses())
     63     if (Op.isFI())
     64       return true;
     65   return false;
     66 }
     67 
     68 bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
     69     MachineBasicBlock &MBB) {
     70   bool Changed = false;
     71   for (MachineInstr &MI : MBB) {
     72     if (usesFrameIndex(MI)) {
     73       // We need to skip this instruction because while it appears to have a
     74       // dead def it uses a frame index which might expand into a multi
     75       // instruction sequence during EPI.
     76       DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
     77       continue;
     78     }
     79     for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
     80       MachineOperand &MO = MI.getOperand(i);
     81       if (MO.isReg() && MO.isDead() && MO.isDef()) {
     82         assert(!MO.isImplicit() && "Unexpected implicit def!");
     83         DEBUG(dbgs() << "  Dead def operand #" << i << " in:\n    ";
     84               MI.print(dbgs()));
     85         // Be careful not to change the register if it's a tied operand.
     86         if (MI.isRegTiedToUseOperand(i)) {
     87           DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
     88           continue;
     89         }
     90         // Don't change the register if there's an implicit def of a subreg or
     91         // supperreg.
     92         if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
     93           DEBUG(dbgs() << "    Ignoring, implicitly defines overlap reg.\n");
     94           continue;
     95         }
     96         // Make sure the instruction take a register class that contains
     97         // the zero register and replace it if so.
     98         unsigned NewReg;
     99         switch (MI.getDesc().OpInfo[i].RegClass) {
    100         default:
    101           DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
    102           continue;
    103         case AArch64::GPR32RegClassID:
    104           NewReg = AArch64::WZR;
    105           break;
    106         case AArch64::GPR64RegClassID:
    107           NewReg = AArch64::XZR;
    108           break;
    109         }
    110         DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
    111         MO.setReg(NewReg);
    112         DEBUG(MI.print(dbgs()));
    113         ++NumDeadDefsReplaced;
    114       }
    115     }
    116   }
    117   return Changed;
    118 }
    119 
    120 // Scan the function for instructions that have a dead definition of a
    121 // register. Replace that register with the zero register when possible.
    122 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
    123   TRI = MF.getSubtarget().getRegisterInfo();
    124   bool Changed = false;
    125   DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
    126 
    127   for (auto &MBB : MF)
    128     if (processMachineBasicBlock(MBB))
    129       Changed = true;
    130   return Changed;
    131 }
    132 
    133 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
    134   return new AArch64DeadRegisterDefinitions();
    135 }
    136