1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMAsmBackend.h" 13 #include "MCTargetDesc/ARMAsmBackendDarwin.h" 14 #include "MCTargetDesc/ARMAsmBackendELF.h" 15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDirectives.h" 23 #include "llvm/MC/MCELFObjectWriter.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCFixupKindInfo.h" 26 #include "llvm/MC/MCMachObjectWriter.h" 27 #include "llvm/MC/MCObjectWriter.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/MC/MCSubtargetInfo.h" 31 #include "llvm/MC/MCValue.h" 32 #include "llvm/Support/ELF.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/MachO.h" 35 #include "llvm/Support/raw_ostream.h" 36 using namespace llvm; 37 38 namespace { 39 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 40 public: 41 ARMELFObjectWriter(uint8_t OSABI) 42 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 43 /*HasRelocationAddend*/ false) {} 44 }; 45 46 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 47 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 48 // This table *must* be in the order that the fixup_* kinds are defined in 49 // ARMFixupKinds.h. 50 // 51 // Name Offset (bits) Size (bits) Flags 52 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 53 {"fixup_t2_ldst_pcrel_12", 0, 32, 54 MCFixupKindInfo::FKF_IsPCRel | 55 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 56 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 57 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 58 {"fixup_t2_pcrel_10", 0, 32, 59 MCFixupKindInfo::FKF_IsPCRel | 60 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 61 {"fixup_thumb_adr_pcrel_10", 0, 8, 62 MCFixupKindInfo::FKF_IsPCRel | 63 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 64 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 65 {"fixup_t2_adr_pcrel_12", 0, 32, 66 MCFixupKindInfo::FKF_IsPCRel | 67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 68 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 69 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 70 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 71 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 72 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 73 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 74 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 75 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 76 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 77 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 78 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 79 {"fixup_arm_thumb_cp", 0, 8, 80 MCFixupKindInfo::FKF_IsPCRel | 81 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 82 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 83 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 84 // - 19. 85 {"fixup_arm_movt_hi16", 0, 20, 0}, 86 {"fixup_arm_movw_lo16", 0, 20, 0}, 87 {"fixup_t2_movt_hi16", 0, 20, 0}, 88 {"fixup_t2_movw_lo16", 0, 20, 0}, 89 }; 90 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 91 // This table *must* be in the order that the fixup_* kinds are defined in 92 // ARMFixupKinds.h. 93 // 94 // Name Offset (bits) Size (bits) Flags 95 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 96 {"fixup_t2_ldst_pcrel_12", 0, 32, 97 MCFixupKindInfo::FKF_IsPCRel | 98 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 99 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 100 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 101 {"fixup_t2_pcrel_10", 0, 32, 102 MCFixupKindInfo::FKF_IsPCRel | 103 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 104 {"fixup_thumb_adr_pcrel_10", 8, 8, 105 MCFixupKindInfo::FKF_IsPCRel | 106 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 107 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 108 {"fixup_t2_adr_pcrel_12", 0, 32, 109 MCFixupKindInfo::FKF_IsPCRel | 110 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 111 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 112 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 113 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 114 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 115 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 116 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 117 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 118 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 119 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 120 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 121 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 122 {"fixup_arm_thumb_cp", 8, 8, 123 MCFixupKindInfo::FKF_IsPCRel | 124 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 125 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 126 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 127 // - 19. 128 {"fixup_arm_movt_hi16", 12, 20, 0}, 129 {"fixup_arm_movw_lo16", 12, 20, 0}, 130 {"fixup_t2_movt_hi16", 12, 20, 0}, 131 {"fixup_t2_movw_lo16", 12, 20, 0}, 132 }; 133 134 if (Kind < FirstTargetFixupKind) 135 return MCAsmBackend::getFixupKindInfo(Kind); 136 137 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 138 "Invalid kind!"); 139 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 140 } 141 142 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 143 switch (Flag) { 144 default: 145 break; 146 case MCAF_Code16: 147 setIsThumb(true); 148 break; 149 case MCAF_Code32: 150 setIsThumb(false); 151 break; 152 } 153 } 154 } // end anonymous namespace 155 156 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const { 157 bool HasThumb2 = STI->getFeatureBits() & ARM::FeatureThumb2; 158 159 switch (Op) { 160 default: 161 return Op; 162 case ARM::tBcc: 163 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 164 case ARM::tLDRpci: 165 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 166 case ARM::tADR: 167 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 168 case ARM::tB: 169 return HasThumb2 ? (unsigned)ARM::t2B : Op; 170 case ARM::tCBZ: 171 return ARM::tHINT; 172 case ARM::tCBNZ: 173 return ARM::tHINT; 174 } 175 } 176 177 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 178 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 179 return true; 180 return false; 181 } 182 183 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 184 const MCRelaxableFragment *DF, 185 const MCAsmLayout &Layout) const { 186 switch ((unsigned)Fixup.getKind()) { 187 case ARM::fixup_arm_thumb_br: { 188 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 189 // low bit being an implied zero. There's an implied +4 offset for the 190 // branch, so we adjust the other way here to determine what's 191 // encodable. 192 // 193 // Relax if the value is too big for a (signed) i8. 194 int64_t Offset = int64_t(Value) - 4; 195 return Offset > 2046 || Offset < -2048; 196 } 197 case ARM::fixup_arm_thumb_bcc: { 198 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 199 // low bit being an implied zero. There's an implied +4 offset for the 200 // branch, so we adjust the other way here to determine what's 201 // encodable. 202 // 203 // Relax if the value is too big for a (signed) i8. 204 int64_t Offset = int64_t(Value) - 4; 205 return Offset > 254 || Offset < -256; 206 } 207 case ARM::fixup_thumb_adr_pcrel_10: 208 case ARM::fixup_arm_thumb_cp: { 209 // If the immediate is negative, greater than 1020, or not a multiple 210 // of four, the wide version of the instruction must be used. 211 int64_t Offset = int64_t(Value) - 4; 212 return Offset > 1020 || Offset < 0 || Offset & 3; 213 } 214 case ARM::fixup_arm_thumb_cb: 215 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 216 // instruction it is is actually out of range for the instruction. 217 // It will be changed to a NOP. 218 int64_t Offset = (Value & ~1); 219 return Offset == 2; 220 } 221 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 222 } 223 224 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 225 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 226 227 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 228 if (RelaxedOp == Inst.getOpcode()) { 229 SmallString<256> Tmp; 230 raw_svector_ostream OS(Tmp); 231 Inst.dump_pretty(OS); 232 OS << "\n"; 233 report_fatal_error("unexpected instruction to relax: " + OS.str()); 234 } 235 236 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 237 // have to change the operands too. 238 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 239 RelaxedOp == ARM::tHINT) { 240 Res.setOpcode(RelaxedOp); 241 Res.addOperand(MCOperand::CreateImm(0)); 242 Res.addOperand(MCOperand::CreateImm(14)); 243 Res.addOperand(MCOperand::CreateReg(0)); 244 return; 245 } 246 247 // The rest of instructions we're relaxing have the same operands. 248 // We just need to update to the proper opcode. 249 Res = Inst; 250 Res.setOpcode(RelaxedOp); 251 } 252 253 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 254 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 255 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 256 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 257 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 258 if (isThumb()) { 259 const uint16_t nopEncoding = 260 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 261 uint64_t NumNops = Count / 2; 262 for (uint64_t i = 0; i != NumNops; ++i) 263 OW->Write16(nopEncoding); 264 if (Count & 1) 265 OW->Write8(0); 266 return true; 267 } 268 // ARM mode 269 const uint32_t nopEncoding = 270 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 271 uint64_t NumNops = Count / 4; 272 for (uint64_t i = 0; i != NumNops; ++i) 273 OW->Write32(nopEncoding); 274 // FIXME: should this function return false when unable to write exactly 275 // 'Count' bytes with NOP encodings? 276 switch (Count % 4) { 277 default: 278 break; // No leftover bytes to write 279 case 1: 280 OW->Write8(0); 281 break; 282 case 2: 283 OW->Write16(0); 284 break; 285 case 3: 286 OW->Write16(0); 287 OW->Write8(0xa0); 288 break; 289 } 290 291 return true; 292 } 293 294 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 295 if (IsLittleEndian) { 296 // Note that the halfwords are stored high first and low second in thumb; 297 // so we need to swap the fixup value here to map properly. 298 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 299 Swapped |= (Value & 0x0000FFFF) << 16; 300 return Swapped; 301 } else 302 return Value; 303 } 304 305 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 306 bool IsLittleEndian) { 307 uint32_t Value; 308 309 if (IsLittleEndian) { 310 Value = (SecondHalf & 0xFFFF) << 16; 311 Value |= (FirstHalf & 0xFFFF); 312 } else { 313 Value = (SecondHalf & 0xFFFF); 314 Value |= (FirstHalf & 0xFFFF) << 16; 315 } 316 317 return Value; 318 } 319 320 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 321 bool IsPCRel, MCContext *Ctx, 322 bool IsLittleEndian) { 323 unsigned Kind = Fixup.getKind(); 324 switch (Kind) { 325 default: 326 llvm_unreachable("Unknown fixup kind!"); 327 case FK_Data_1: 328 case FK_Data_2: 329 case FK_Data_4: 330 return Value; 331 case FK_SecRel_2: 332 return Value; 333 case FK_SecRel_4: 334 return Value; 335 case ARM::fixup_arm_movt_hi16: 336 if (!IsPCRel) 337 Value >>= 16; 338 // Fallthrough 339 case ARM::fixup_arm_movw_lo16: { 340 unsigned Hi4 = (Value & 0xF000) >> 12; 341 unsigned Lo12 = Value & 0x0FFF; 342 // inst{19-16} = Hi4; 343 // inst{11-0} = Lo12; 344 Value = (Hi4 << 16) | (Lo12); 345 return Value; 346 } 347 case ARM::fixup_t2_movt_hi16: 348 if (!IsPCRel) 349 Value >>= 16; 350 // Fallthrough 351 case ARM::fixup_t2_movw_lo16: { 352 unsigned Hi4 = (Value & 0xF000) >> 12; 353 unsigned i = (Value & 0x800) >> 11; 354 unsigned Mid3 = (Value & 0x700) >> 8; 355 unsigned Lo8 = Value & 0x0FF; 356 // inst{19-16} = Hi4; 357 // inst{26} = i; 358 // inst{14-12} = Mid3; 359 // inst{7-0} = Lo8; 360 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 361 return swapHalfWords(Value, IsLittleEndian); 362 } 363 case ARM::fixup_arm_ldst_pcrel_12: 364 // ARM PC-relative values are offset by 8. 365 Value -= 4; 366 // FALLTHROUGH 367 case ARM::fixup_t2_ldst_pcrel_12: { 368 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 369 Value -= 4; 370 bool isAdd = true; 371 if ((int64_t)Value < 0) { 372 Value = -Value; 373 isAdd = false; 374 } 375 if (Ctx && Value >= 4096) 376 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 377 Value |= isAdd << 23; 378 379 // Same addressing mode as fixup_arm_pcrel_10, 380 // but with 16-bit halfwords swapped. 381 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 382 return swapHalfWords(Value, IsLittleEndian); 383 384 return Value; 385 } 386 case ARM::fixup_thumb_adr_pcrel_10: 387 return ((Value - 4) >> 2) & 0xff; 388 case ARM::fixup_arm_adr_pcrel_12: { 389 // ARM PC-relative values are offset by 8. 390 Value -= 8; 391 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 392 if ((int64_t)Value < 0) { 393 Value = -Value; 394 opc = 2; // 0b0010 395 } 396 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) 397 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 398 // Encode the immediate and shift the opcode into place. 399 return ARM_AM::getSOImmVal(Value) | (opc << 21); 400 } 401 402 case ARM::fixup_t2_adr_pcrel_12: { 403 Value -= 4; 404 unsigned opc = 0; 405 if ((int64_t)Value < 0) { 406 Value = -Value; 407 opc = 5; 408 } 409 410 uint32_t out = (opc << 21); 411 out |= (Value & 0x800) << 15; 412 out |= (Value & 0x700) << 4; 413 out |= (Value & 0x0FF); 414 415 return swapHalfWords(out, IsLittleEndian); 416 } 417 418 case ARM::fixup_arm_condbranch: 419 case ARM::fixup_arm_uncondbranch: 420 case ARM::fixup_arm_uncondbl: 421 case ARM::fixup_arm_condbl: 422 case ARM::fixup_arm_blx: 423 // These values don't encode the low two bits since they're always zero. 424 // Offset by 8 just as above. 425 if (const MCSymbolRefExpr *SRE = 426 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 427 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 428 return 0; 429 return 0xffffff & ((Value - 8) >> 2); 430 case ARM::fixup_t2_uncondbranch: { 431 Value = Value - 4; 432 Value >>= 1; // Low bit is not encoded. 433 434 uint32_t out = 0; 435 bool I = Value & 0x800000; 436 bool J1 = Value & 0x400000; 437 bool J2 = Value & 0x200000; 438 J1 ^= I; 439 J2 ^= I; 440 441 out |= I << 26; // S bit 442 out |= !J1 << 13; // J1 bit 443 out |= !J2 << 11; // J2 bit 444 out |= (Value & 0x1FF800) << 5; // imm6 field 445 out |= (Value & 0x0007FF); // imm11 field 446 447 return swapHalfWords(out, IsLittleEndian); 448 } 449 case ARM::fixup_t2_condbranch: { 450 Value = Value - 4; 451 Value >>= 1; // Low bit is not encoded. 452 453 uint64_t out = 0; 454 out |= (Value & 0x80000) << 7; // S bit 455 out |= (Value & 0x40000) >> 7; // J2 bit 456 out |= (Value & 0x20000) >> 4; // J1 bit 457 out |= (Value & 0x1F800) << 5; // imm6 field 458 out |= (Value & 0x007FF); // imm11 field 459 460 return swapHalfWords(out, IsLittleEndian); 461 } 462 case ARM::fixup_arm_thumb_bl: { 463 // The value doesn't encode the low bit (always zero) and is offset by 464 // four. The 32-bit immediate value is encoded as 465 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 466 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 467 // The value is encoded into disjoint bit positions in the destination 468 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 469 // J = either J1 or J2 bit 470 // 471 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 472 // 473 // Note that the halfwords are stored high first, low second; so we need 474 // to transpose the fixup value here to map properly. 475 uint32_t offset = (Value - 4) >> 1; 476 uint32_t signBit = (offset & 0x800000) >> 23; 477 uint32_t I1Bit = (offset & 0x400000) >> 22; 478 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 479 uint32_t I2Bit = (offset & 0x200000) >> 21; 480 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 481 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 482 uint32_t imm11Bits = (offset & 0x000007FF); 483 484 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 485 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 486 (uint16_t)imm11Bits); 487 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 488 } 489 case ARM::fixup_arm_thumb_blx: { 490 // The value doesn't encode the low two bits (always zero) and is offset by 491 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 492 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 493 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 494 // The value is encoded into disjoint bit positions in the destination 495 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 496 // J = either J1 or J2 bit, 0 = zero. 497 // 498 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 499 // 500 // Note that the halfwords are stored high first, low second; so we need 501 // to transpose the fixup value here to map properly. 502 uint32_t offset = (Value - 2) >> 2; 503 if (const MCSymbolRefExpr *SRE = 504 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 505 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 506 offset = 0; 507 uint32_t signBit = (offset & 0x400000) >> 22; 508 uint32_t I1Bit = (offset & 0x200000) >> 21; 509 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 510 uint32_t I2Bit = (offset & 0x100000) >> 20; 511 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 512 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 513 uint32_t imm10LBits = (offset & 0x3FF); 514 515 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 516 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 517 ((uint16_t)imm10LBits) << 1); 518 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 519 } 520 case ARM::fixup_arm_thumb_cp: 521 // Offset by 4, and don't encode the low two bits. Two bytes of that 522 // 'off by 4' is implicitly handled by the half-word ordering of the 523 // Thumb encoding, so we only need to adjust by 2 here. 524 return ((Value - 2) >> 2) & 0xff; 525 case ARM::fixup_arm_thumb_cb: { 526 // Offset by 4 and don't encode the lower bit, which is always 0. 527 uint32_t Binary = (Value - 4) >> 1; 528 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 529 } 530 case ARM::fixup_arm_thumb_br: 531 // Offset by 4 and don't encode the lower bit, which is always 0. 532 return ((Value - 4) >> 1) & 0x7ff; 533 case ARM::fixup_arm_thumb_bcc: 534 // Offset by 4 and don't encode the lower bit, which is always 0. 535 return ((Value - 4) >> 1) & 0xff; 536 case ARM::fixup_arm_pcrel_10_unscaled: { 537 Value = Value - 8; // ARM fixups offset by an additional word and don't 538 // need to adjust for the half-word ordering. 539 bool isAdd = true; 540 if ((int64_t)Value < 0) { 541 Value = -Value; 542 isAdd = false; 543 } 544 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 545 if (Ctx && Value >= 256) 546 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 547 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 548 return Value | (isAdd << 23); 549 } 550 case ARM::fixup_arm_pcrel_10: 551 Value = Value - 4; // ARM fixups offset by an additional word and don't 552 // need to adjust for the half-word ordering. 553 // Fall through. 554 case ARM::fixup_t2_pcrel_10: { 555 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 556 Value = Value - 4; 557 bool isAdd = true; 558 if ((int64_t)Value < 0) { 559 Value = -Value; 560 isAdd = false; 561 } 562 // These values don't encode the low two bits since they're always zero. 563 Value >>= 2; 564 if (Ctx && Value >= 256) 565 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 566 Value |= isAdd << 23; 567 568 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 569 // swapped. 570 if (Kind == ARM::fixup_t2_pcrel_10) 571 return swapHalfWords(Value, IsLittleEndian); 572 573 return Value; 574 } 575 } 576 } 577 578 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 579 const MCAsmLayout &Layout, 580 const MCFixup &Fixup, 581 const MCFragment *DF, 582 const MCValue &Target, uint64_t &Value, 583 bool &IsResolved) { 584 const MCSymbolRefExpr *A = Target.getSymA(); 585 // Some fixups to thumb function symbols need the low bit (thumb bit) 586 // twiddled. 587 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 588 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 589 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 590 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 591 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 592 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 593 if (A) { 594 const MCSymbol &Sym = A->getSymbol(); 595 if (Asm.isThumbFunc(&Sym)) 596 Value |= 1; 597 } 598 } 599 // For Thumb1 BL instruction, it is possible to be a long jump between 600 // the basic blocks of the same function. Thus, we would like to resolve 601 // the offset when the destination has the same MCFragment. 602 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 603 const MCSymbol &Sym = A->getSymbol(); 604 const MCSymbolData &SymData = Asm.getSymbolData(Sym); 605 IsResolved = (SymData.getFragment() == DF); 606 } 607 // We must always generate a relocation for BL/BLX instructions if we have 608 // a symbol to reference, as the linker relies on knowing the destination 609 // symbol's thumb-ness to get interworking right. 610 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 611 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 612 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 613 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 614 IsResolved = false; 615 616 // Try to get the encoded value for the fixup as-if we're mapping it into 617 // the instruction. This allows adjustFixupValue() to issue a diagnostic 618 // if the value aren't invalid. 619 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(), 620 IsLittleEndian); 621 } 622 623 /// getFixupKindNumBytes - The number of bytes the fixup may change. 624 static unsigned getFixupKindNumBytes(unsigned Kind) { 625 switch (Kind) { 626 default: 627 llvm_unreachable("Unknown fixup kind!"); 628 629 case FK_Data_1: 630 case ARM::fixup_arm_thumb_bcc: 631 case ARM::fixup_arm_thumb_cp: 632 case ARM::fixup_thumb_adr_pcrel_10: 633 return 1; 634 635 case FK_Data_2: 636 case ARM::fixup_arm_thumb_br: 637 case ARM::fixup_arm_thumb_cb: 638 return 2; 639 640 case ARM::fixup_arm_pcrel_10_unscaled: 641 case ARM::fixup_arm_ldst_pcrel_12: 642 case ARM::fixup_arm_pcrel_10: 643 case ARM::fixup_arm_adr_pcrel_12: 644 case ARM::fixup_arm_uncondbl: 645 case ARM::fixup_arm_condbl: 646 case ARM::fixup_arm_blx: 647 case ARM::fixup_arm_condbranch: 648 case ARM::fixup_arm_uncondbranch: 649 return 3; 650 651 case FK_Data_4: 652 case ARM::fixup_t2_ldst_pcrel_12: 653 case ARM::fixup_t2_condbranch: 654 case ARM::fixup_t2_uncondbranch: 655 case ARM::fixup_t2_pcrel_10: 656 case ARM::fixup_t2_adr_pcrel_12: 657 case ARM::fixup_arm_thumb_bl: 658 case ARM::fixup_arm_thumb_blx: 659 case ARM::fixup_arm_movt_hi16: 660 case ARM::fixup_arm_movw_lo16: 661 case ARM::fixup_t2_movt_hi16: 662 case ARM::fixup_t2_movw_lo16: 663 return 4; 664 665 case FK_SecRel_2: 666 return 2; 667 case FK_SecRel_4: 668 return 4; 669 } 670 } 671 672 /// getFixupKindContainerSizeBytes - The number of bytes of the 673 /// container involved in big endian. 674 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 675 switch (Kind) { 676 default: 677 llvm_unreachable("Unknown fixup kind!"); 678 679 case FK_Data_1: 680 return 1; 681 case FK_Data_2: 682 return 2; 683 case FK_Data_4: 684 return 4; 685 686 case ARM::fixup_arm_thumb_bcc: 687 case ARM::fixup_arm_thumb_cp: 688 case ARM::fixup_thumb_adr_pcrel_10: 689 case ARM::fixup_arm_thumb_br: 690 case ARM::fixup_arm_thumb_cb: 691 // Instruction size is 2 bytes. 692 return 2; 693 694 case ARM::fixup_arm_pcrel_10_unscaled: 695 case ARM::fixup_arm_ldst_pcrel_12: 696 case ARM::fixup_arm_pcrel_10: 697 case ARM::fixup_arm_adr_pcrel_12: 698 case ARM::fixup_arm_uncondbl: 699 case ARM::fixup_arm_condbl: 700 case ARM::fixup_arm_blx: 701 case ARM::fixup_arm_condbranch: 702 case ARM::fixup_arm_uncondbranch: 703 case ARM::fixup_t2_ldst_pcrel_12: 704 case ARM::fixup_t2_condbranch: 705 case ARM::fixup_t2_uncondbranch: 706 case ARM::fixup_t2_pcrel_10: 707 case ARM::fixup_t2_adr_pcrel_12: 708 case ARM::fixup_arm_thumb_bl: 709 case ARM::fixup_arm_thumb_blx: 710 case ARM::fixup_arm_movt_hi16: 711 case ARM::fixup_arm_movw_lo16: 712 case ARM::fixup_t2_movt_hi16: 713 case ARM::fixup_t2_movw_lo16: 714 // Instruction size is 4 bytes. 715 return 4; 716 } 717 } 718 719 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 720 unsigned DataSize, uint64_t Value, 721 bool IsPCRel) const { 722 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 723 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian); 724 if (!Value) 725 return; // Doesn't change encoding. 726 727 unsigned Offset = Fixup.getOffset(); 728 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 729 730 // Used to point to big endian bytes. 731 unsigned FullSizeBytes; 732 if (!IsLittleEndian) { 733 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 734 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); 735 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 736 } 737 738 // For each byte of the fragment that the fixup touches, mask in the bits from 739 // the fixup value. The Value has been "split up" into the appropriate 740 // bitfields above. 741 for (unsigned i = 0; i != NumBytes; ++i) { 742 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 743 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 744 } 745 } 746 747 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 748 const MCRegisterInfo &MRI, StringRef TT, 749 StringRef CPU, bool isLittle) { 750 Triple TheTriple(TT); 751 752 switch (TheTriple.getObjectFormat()) { 753 default: 754 llvm_unreachable("unsupported object format"); 755 case Triple::MachO: { 756 MachO::CPUSubTypeARM CS = 757 StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName()) 758 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T) 759 .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ) 760 .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6) 761 .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M) 762 .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM) 763 .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K) 764 .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M) 765 .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S) 766 .Default(MachO::CPU_SUBTYPE_ARM_V7); 767 768 return new ARMAsmBackendDarwin(T, TT, CS); 769 } 770 case Triple::COFF: 771 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 772 return new ARMAsmBackendWinCOFF(T, TT); 773 case Triple::ELF: 774 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 775 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 776 return new ARMAsmBackendELF(T, TT, OSABI, isLittle); 777 } 778 } 779 780 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 781 const MCRegisterInfo &MRI, 782 StringRef TT, StringRef CPU) { 783 return createARMAsmBackend(T, MRI, TT, CPU, true); 784 } 785 786 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 787 const MCRegisterInfo &MRI, 788 StringRef TT, StringRef CPU) { 789 return createARMAsmBackend(T, MRI, TT, CPU, false); 790 } 791 792 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 793 const MCRegisterInfo &MRI, 794 StringRef TT, StringRef CPU) { 795 return createARMAsmBackend(T, MRI, TT, CPU, true); 796 } 797 798 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 799 const MCRegisterInfo &MRI, 800 StringRef TT, StringRef CPU) { 801 return createARMAsmBackend(T, MRI, TT, CPU, false); 802 } 803
