1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the XCore target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "XCore.h" 15 #include "XCoreTargetMachine.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/SelectionDAGISel.h" 22 #include "llvm/IR/CallingConv.h" 23 #include "llvm/IR/Constants.h" 24 #include "llvm/IR/DerivedTypes.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/Intrinsics.h" 27 #include "llvm/IR/LLVMContext.h" 28 #include "llvm/Support/Compiler.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/raw_ostream.h" 32 #include "llvm/Target/TargetLowering.h" 33 using namespace llvm; 34 35 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine 36 /// instructions for SelectionDAG operations. 37 /// 38 namespace { 39 class XCoreDAGToDAGISel : public SelectionDAGISel { 40 41 public: 42 XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) 43 : SelectionDAGISel(TM, OptLevel) {} 44 45 SDNode *Select(SDNode *N) override; 46 SDNode *SelectBRIND(SDNode *N); 47 48 /// getI32Imm - Return a target constant with the specified value, of type 49 /// i32. 50 inline SDValue getI32Imm(unsigned Imm) { 51 return CurDAG->getTargetConstant(Imm, MVT::i32); 52 } 53 54 inline bool immMskBitp(SDNode *inN) const { 55 ConstantSDNode *N = cast<ConstantSDNode>(inN); 56 uint32_t value = (uint32_t)N->getZExtValue(); 57 if (!isMask_32(value)) { 58 return false; 59 } 60 int msksize = 32 - countLeadingZeros(value); 61 return (msksize >= 1 && msksize <= 8) || 62 msksize == 16 || msksize == 24 || msksize == 32; 63 } 64 65 // Complex Pattern Selectors. 66 bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); 67 68 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 69 std::vector<SDValue> &OutOps) override; 70 71 const char *getPassName() const override { 72 return "XCore DAG->DAG Pattern Instruction Selection"; 73 } 74 75 // Include the pieces autogenerated from the target description. 76 #include "XCoreGenDAGISel.inc" 77 }; 78 } // end anonymous namespace 79 80 /// createXCoreISelDag - This pass converts a legalized DAG into a 81 /// XCore-specific DAG, ready for instruction scheduling. 82 /// 83 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, 84 CodeGenOpt::Level OptLevel) { 85 return new XCoreDAGToDAGISel(TM, OptLevel); 86 } 87 88 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, 89 SDValue &Offset) { 90 FrameIndexSDNode *FIN = nullptr; 91 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { 92 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 93 Offset = CurDAG->getTargetConstant(0, MVT::i32); 94 return true; 95 } 96 if (Addr.getOpcode() == ISD::ADD) { 97 ConstantSDNode *CN = nullptr; 98 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 99 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 100 && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { 101 // Constant positive word offset from frame index 102 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 103 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); 104 return true; 105 } 106 } 107 return false; 108 } 109 110 bool XCoreDAGToDAGISel:: 111 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 112 std::vector<SDValue> &OutOps) { 113 SDValue Reg; 114 switch (ConstraintID) { 115 default: return true; 116 case InlineAsm::Constraint_m: // Memory. 117 switch (Op.getOpcode()) { 118 default: return true; 119 case XCoreISD::CPRelativeWrapper: 120 Reg = CurDAG->getRegister(XCore::CP, MVT::i32); 121 break; 122 case XCoreISD::DPRelativeWrapper: 123 Reg = CurDAG->getRegister(XCore::DP, MVT::i32); 124 break; 125 } 126 } 127 OutOps.push_back(Reg); 128 OutOps.push_back(Op.getOperand(0)); 129 return false; 130 } 131 132 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) { 133 SDLoc dl(N); 134 switch (N->getOpcode()) { 135 default: break; 136 case ISD::Constant: { 137 uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue(); 138 if (immMskBitp(N)) { 139 // Transformation function: get the size of a mask 140 // Look for the first non-zero bit 141 SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val)); 142 return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, 143 MVT::i32, MskSize); 144 } 145 else if (!isUInt<16>(Val)) { 146 SDValue CPIdx = 147 CurDAG->getTargetConstantPool(ConstantInt::get( 148 Type::getInt32Ty(*CurDAG->getContext()), Val), 149 getTargetLowering()->getPointerTy()); 150 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 151 MVT::Other, CPIdx, 152 CurDAG->getEntryNode()); 153 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 154 MemOp[0] = MF->getMachineMemOperand( 155 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4); 156 cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1); 157 return node; 158 } 159 break; 160 } 161 case XCoreISD::LADD: { 162 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 163 N->getOperand(2) }; 164 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, 165 Ops); 166 } 167 case XCoreISD::LSUB: { 168 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 169 N->getOperand(2) }; 170 return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, 171 Ops); 172 } 173 case XCoreISD::MACCU: { 174 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 175 N->getOperand(2), N->getOperand(3) }; 176 return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32, 177 Ops); 178 } 179 case XCoreISD::MACCS: { 180 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 181 N->getOperand(2), N->getOperand(3) }; 182 return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, 183 Ops); 184 } 185 case XCoreISD::LMUL: { 186 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 187 N->getOperand(2), N->getOperand(3) }; 188 return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, 189 Ops); 190 } 191 case XCoreISD::CRC8: { 192 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; 193 return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, 194 Ops); 195 } 196 case ISD::BRIND: 197 if (SDNode *ResNode = SelectBRIND(N)) 198 return ResNode; 199 break; 200 // Other cases are autogenerated. 201 } 202 return SelectCode(N); 203 } 204 205 /// Given a chain return a new chain where any appearance of Old is replaced 206 /// by New. There must be at most one instruction between Old and Chain and 207 /// this instruction must be a TokenFactor. Returns an empty SDValue if 208 /// these conditions don't hold. 209 static SDValue 210 replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New) 211 { 212 if (Chain == Old) 213 return New; 214 if (Chain->getOpcode() != ISD::TokenFactor) 215 return SDValue(); 216 SmallVector<SDValue, 8> Ops; 217 bool found = false; 218 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) { 219 if (Chain->getOperand(i) == Old) { 220 Ops.push_back(New); 221 found = true; 222 } else { 223 Ops.push_back(Chain->getOperand(i)); 224 } 225 } 226 if (!found) 227 return SDValue(); 228 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops); 229 } 230 231 SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) { 232 SDLoc dl(N); 233 // (brind (int_xcore_checkevent (addr))) 234 SDValue Chain = N->getOperand(0); 235 SDValue Addr = N->getOperand(1); 236 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) 237 return nullptr; 238 unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue(); 239 if (IntNo != Intrinsic::xcore_checkevent) 240 return nullptr; 241 SDValue nextAddr = Addr->getOperand(2); 242 SDValue CheckEventChainOut(Addr.getNode(), 1); 243 if (!CheckEventChainOut.use_empty()) { 244 // If the chain out of the checkevent intrinsic is an operand of the 245 // indirect branch or used in a TokenFactor which is the operand of the 246 // indirect branch then build a new chain which uses the chain coming into 247 // the checkevent intrinsic instead. 248 SDValue CheckEventChainIn = Addr->getOperand(0); 249 SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut, 250 CheckEventChainIn); 251 if (!NewChain.getNode()) 252 return nullptr; 253 Chain = NewChain; 254 } 255 // Enable events on the thread using setsr 1 and then disable them immediately 256 // after with clrsr 1. If any resources owned by the thread are ready an event 257 // will be taken. If no resource is ready we branch to the address which was 258 // the operand to the checkevent intrinsic. 259 SDValue constOne = getI32Imm(1); 260 SDValue Glue = 261 SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, 262 constOne, Chain), 0); 263 Glue = 264 SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue, 265 constOne, Glue), 0); 266 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && 267 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { 268 return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, 269 nextAddr->getOperand(0), Glue); 270 } 271 return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); 272 } 273
