1 /* 2 * Copyright 2009 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric (at) anholt.net> 25 * 26 */ 27 28 #include "main/macros.h" 29 #include "intel_batchbuffer.h" 30 #include "brw_context.h" 31 #include "brw_state.h" 32 #include "brw_defines.h" 33 34 /** 35 * When the GS is not in use, we assign the entire URB space to the VS. When 36 * the GS is in use, we split the URB space evenly between the VS and the GS. 37 * This is not ideal, but it's simple. 38 * 39 * URB size / 2 URB size / 2 40 * _____________-______________ _____________-______________ 41 * / \ / \ 42 * +-------------------------------------------------------------+ 43 * | Vertex Shader Entries | Geometry Shader Entries | 44 * +-------------------------------------------------------------+ 45 * 46 * Sandybridge GT1 has 32kB of URB space, while GT2 has 64kB. 47 * (See the Sandybridge PRM, Volume 2, Part 1, Section 1.4.7: 3DSTATE_URB.) 48 */ 49 static void 50 gen6_upload_urb( struct brw_context *brw ) 51 { 52 struct intel_context *intel = &brw->intel; 53 int nr_vs_entries, nr_gs_entries; 54 int total_urb_size = brw->urb.size * 1024; /* in bytes */ 55 56 /* CACHE_NEW_VS_PROG */ 57 brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); 58 59 /* We use the same VUE layout for VS outputs and GS outputs (as it's what 60 * the SF and Clipper expect), so we can simply make the GS URB entry size 61 * the same as for the VS. This may technically be too large in cases 62 * where we have few vertex attributes and a lot of varyings, since the VS 63 * size is determined by the larger of the two. For now, it's safe. 64 */ 65 brw->urb.gs_size = brw->urb.vs_size; 66 67 /* Calculate how many entries fit in each stage's section of the URB */ 68 if (brw->gs.prog_active) { 69 nr_vs_entries = (total_urb_size/2) / (brw->urb.vs_size * 128); 70 nr_gs_entries = (total_urb_size/2) / (brw->urb.gs_size * 128); 71 } else { 72 nr_vs_entries = total_urb_size / (brw->urb.vs_size * 128); 73 nr_gs_entries = 0; 74 } 75 76 /* Then clamp to the maximum allowed by the hardware */ 77 if (nr_vs_entries > brw->urb.max_vs_entries) 78 nr_vs_entries = brw->urb.max_vs_entries; 79 80 if (nr_gs_entries > brw->urb.max_gs_entries) 81 nr_gs_entries = brw->urb.max_gs_entries; 82 83 /* Finally, both must be a multiple of 4 (see 3DSTATE_URB in the PRM). */ 84 brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); 85 brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); 86 87 assert(brw->urb.nr_vs_entries >= 24); 88 assert(brw->urb.nr_vs_entries % 4 == 0); 89 assert(brw->urb.nr_gs_entries % 4 == 0); 90 assert(brw->urb.vs_size < 5); 91 assert(brw->urb.gs_size < 5); 92 93 BEGIN_BATCH(3); 94 OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); 95 OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) | 96 ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT)); 97 OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | 98 ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT)); 99 ADVANCE_BATCH(); 100 101 /* From the PRM Volume 2 part 1, section 1.4.7: 102 * 103 * Because of a urb corruption caused by allocating a previous gsunits 104 * urb entry to vsunit software is required to send a "GS NULL 105 * Fence"(Send URB fence with VS URB size == 1 and GS URB size == 0) plus 106 * a dummy DRAW call before any case where VS will be taking over GS URB 107 * space. 108 * 109 * It is not clear exactly what this means ("URB fence" is a command that 110 * doesn't exist on Gen6). So for now we just do a full pipeline flush as 111 * a workaround. 112 */ 113 if (brw->urb.gen6_gs_previously_active && !brw->gs.prog_active) 114 intel_batchbuffer_emit_mi_flush(intel); 115 brw->urb.gen6_gs_previously_active = brw->gs.prog_active; 116 } 117 118 const struct brw_tracked_state gen6_urb = { 119 .dirty = { 120 .mesa = 0, 121 .brw = BRW_NEW_CONTEXT, 122 .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG), 123 }, 124 .emit = gen6_upload_urb, 125 }; 126
