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      1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file provides X86 specific target descriptions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "X86MCTargetDesc.h"
     15 #include "InstPrinter/X86ATTInstPrinter.h"
     16 #include "InstPrinter/X86IntelInstPrinter.h"
     17 #include "X86MCAsmInfo.h"
     18 #include "llvm/ADT/Triple.h"
     19 #include "llvm/MC/MCCodeGenInfo.h"
     20 #include "llvm/MC/MCInstrAnalysis.h"
     21 #include "llvm/MC/MCInstrInfo.h"
     22 #include "llvm/MC/MCRegisterInfo.h"
     23 #include "llvm/MC/MCStreamer.h"
     24 #include "llvm/MC/MCSubtargetInfo.h"
     25 #include "llvm/MC/MachineLocation.h"
     26 #include "llvm/Support/ErrorHandling.h"
     27 #include "llvm/Support/Host.h"
     28 #include "llvm/Support/TargetRegistry.h"
     29 
     30 #if _MSC_VER
     31 #include <intrin.h>
     32 #endif
     33 
     34 using namespace llvm;
     35 
     36 #define GET_REGINFO_MC_DESC
     37 #include "X86GenRegisterInfo.inc"
     38 
     39 #define GET_INSTRINFO_MC_DESC
     40 #include "X86GenInstrInfo.inc"
     41 
     42 #define GET_SUBTARGETINFO_MC_DESC
     43 #include "X86GenSubtargetInfo.inc"
     44 
     45 std::string X86_MC::ParseX86Triple(StringRef TT) {
     46   Triple TheTriple(TT);
     47   std::string FS;
     48   if (TheTriple.getArch() == Triple::x86_64)
     49     FS = "+64bit-mode,-32bit-mode,-16bit-mode";
     50   else if (TheTriple.getEnvironment() != Triple::CODE16)
     51     FS = "-64bit-mode,+32bit-mode,-16bit-mode";
     52   else
     53     FS = "-64bit-mode,-32bit-mode,+16bit-mode";
     54 
     55   return FS;
     56 }
     57 
     58 unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
     59   if (TT.getArch() == Triple::x86_64)
     60     return DWARFFlavour::X86_64;
     61 
     62   if (TT.isOSDarwin())
     63     return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
     64   if (TT.isOSCygMing())
     65     // Unsupported by now, just quick fallback
     66     return DWARFFlavour::X86_32_Generic;
     67   return DWARFFlavour::X86_32_Generic;
     68 }
     69 
     70 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
     71   // FIXME: TableGen these.
     72   for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
     73     unsigned SEH = MRI->getEncodingValue(Reg);
     74     MRI->mapLLVMRegToSEHReg(Reg, SEH);
     75   }
     76 }
     77 
     78 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
     79                                                   StringRef FS) {
     80   std::string ArchFS = X86_MC::ParseX86Triple(TT);
     81   if (!FS.empty()) {
     82     if (!ArchFS.empty())
     83       ArchFS = (Twine(ArchFS) + "," + FS).str();
     84     else
     85       ArchFS = FS;
     86   }
     87 
     88   std::string CPUName = CPU;
     89   if (CPUName.empty())
     90     CPUName = "generic";
     91 
     92   MCSubtargetInfo *X = new MCSubtargetInfo();
     93   InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
     94   return X;
     95 }
     96 
     97 static MCInstrInfo *createX86MCInstrInfo() {
     98   MCInstrInfo *X = new MCInstrInfo();
     99   InitX86MCInstrInfo(X);
    100   return X;
    101 }
    102 
    103 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
    104   Triple TheTriple(TT);
    105   unsigned RA = (TheTriple.getArch() == Triple::x86_64)
    106     ? X86::RIP     // Should have dwarf #16.
    107     : X86::EIP;    // Should have dwarf #8.
    108 
    109   MCRegisterInfo *X = new MCRegisterInfo();
    110   InitX86MCRegisterInfo(X, RA,
    111                         X86_MC::getDwarfRegFlavour(TheTriple, false),
    112                         X86_MC::getDwarfRegFlavour(TheTriple, true),
    113                         RA);
    114   X86_MC::InitLLVM2SEHRegisterMapping(X);
    115   return X;
    116 }
    117 
    118 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
    119   Triple TheTriple(TT);
    120   bool is64Bit = TheTriple.getArch() == Triple::x86_64;
    121 
    122   MCAsmInfo *MAI;
    123   if (TheTriple.isOSBinFormatMachO()) {
    124     if (is64Bit)
    125       MAI = new X86_64MCAsmInfoDarwin(TheTriple);
    126     else
    127       MAI = new X86MCAsmInfoDarwin(TheTriple);
    128   } else if (TheTriple.isOSBinFormatELF()) {
    129     // Force the use of an ELF container.
    130     MAI = new X86ELFMCAsmInfo(TheTriple);
    131   } else if (TheTriple.isWindowsMSVCEnvironment()) {
    132     MAI = new X86MCAsmInfoMicrosoft(TheTriple);
    133   } else if (TheTriple.isOSCygMing() ||
    134              TheTriple.isWindowsItaniumEnvironment()) {
    135     MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
    136   } else {
    137     // The default is ELF.
    138     MAI = new X86ELFMCAsmInfo(TheTriple);
    139   }
    140 
    141   // Initialize initial frame state.
    142   // Calculate amount of bytes used for return address storing
    143   int stackGrowth = is64Bit ? -8 : -4;
    144 
    145   // Initial state of the frame pointer is esp+stackGrowth.
    146   unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
    147   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
    148       nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
    149   MAI->addInitialFrameState(Inst);
    150 
    151   // Add return address to move list
    152   unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
    153   MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
    154       nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
    155   MAI->addInitialFrameState(Inst2);
    156 
    157   return MAI;
    158 }
    159 
    160 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
    161                                              CodeModel::Model CM,
    162                                              CodeGenOpt::Level OL) {
    163   MCCodeGenInfo *X = new MCCodeGenInfo();
    164 
    165   Triple T(TT);
    166   bool is64Bit = T.getArch() == Triple::x86_64;
    167 
    168   if (RM == Reloc::Default) {
    169     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
    170     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
    171     // use static relocation model by default.
    172     if (T.isOSDarwin()) {
    173       if (is64Bit)
    174         RM = Reloc::PIC_;
    175       else
    176         RM = Reloc::DynamicNoPIC;
    177     } else if (T.isOSWindows() && is64Bit)
    178       RM = Reloc::PIC_;
    179     else
    180       RM = Reloc::Static;
    181   }
    182 
    183   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
    184   // is defined as a model for code which may be used in static or dynamic
    185   // executables but not necessarily a shared library. On X86-32 we just
    186   // compile in -static mode, in x86-64 we use PIC.
    187   if (RM == Reloc::DynamicNoPIC) {
    188     if (is64Bit)
    189       RM = Reloc::PIC_;
    190     else if (!T.isOSDarwin())
    191       RM = Reloc::Static;
    192   }
    193 
    194   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
    195   // the Mach-O file format doesn't support it.
    196   if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
    197     RM = Reloc::PIC_;
    198 
    199   // For static codegen, if we're not already set, use Small codegen.
    200   if (CM == CodeModel::Default)
    201     CM = CodeModel::Small;
    202   else if (CM == CodeModel::JITDefault)
    203     // 64-bit JIT places everything in the same buffer except external funcs.
    204     CM = is64Bit ? CodeModel::Large : CodeModel::Small;
    205 
    206   X->InitMCCodeGenInfo(RM, CM, OL);
    207   return X;
    208 }
    209 
    210 static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
    211                                              unsigned SyntaxVariant,
    212                                              const MCAsmInfo &MAI,
    213                                              const MCInstrInfo &MII,
    214                                              const MCRegisterInfo &MRI) {
    215   if (SyntaxVariant == 0)
    216     return new X86ATTInstPrinter(MAI, MII, MRI);
    217   if (SyntaxVariant == 1)
    218     return new X86IntelInstPrinter(MAI, MII, MRI);
    219   return nullptr;
    220 }
    221 
    222 static MCRelocationInfo *createX86MCRelocationInfo(StringRef TT,
    223                                                    MCContext &Ctx) {
    224   Triple TheTriple(TT);
    225   if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
    226     return createX86_64MachORelocationInfo(Ctx);
    227   else if (TheTriple.isOSBinFormatELF())
    228     return createX86_64ELFRelocationInfo(Ctx);
    229   // Default to the stock relocation info.
    230   return llvm::createMCRelocationInfo(TT, Ctx);
    231 }
    232 
    233 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
    234   return new MCInstrAnalysis(Info);
    235 }
    236 
    237 // Force static initialization.
    238 extern "C" void LLVMInitializeX86TargetMC() {
    239   for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
    240     // Register the MC asm info.
    241     RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
    242 
    243     // Register the MC codegen info.
    244     RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
    245 
    246     // Register the MC instruction info.
    247     TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
    248 
    249     // Register the MC register info.
    250     TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
    251 
    252     // Register the MC subtarget info.
    253     TargetRegistry::RegisterMCSubtargetInfo(*T,
    254                                             X86_MC::createX86MCSubtargetInfo);
    255 
    256     // Register the MC instruction analyzer.
    257     TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
    258 
    259     // Register the code emitter.
    260     TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
    261 
    262     // Register the object streamer.
    263     TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
    264 
    265     // Register the MCInstPrinter.
    266     TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
    267 
    268     // Register the MC relocation info.
    269     TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
    270   }
    271 
    272   // Register the asm backend.
    273   TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
    274                                        createX86_32AsmBackend);
    275   TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
    276                                        createX86_64AsmBackend);
    277 }
    278