1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 /*! 21 ************************************************************************** 22 * \file ih264d_utils.c 23 * 24 * \brief 25 * Contains routines that handle of start and end of pic processing 26 * 27 * \date 28 * 19/12/2002 29 * 30 * \author AI 31 ************************************************************************** 32 */ 33 34 #include <string.h> 35 #include "ih264_typedefs.h" 36 #include "ithread.h" 37 #include "ih264d_deblocking.h" 38 #include "ih264d_parse_slice.h" 39 #include "ih264d_parse_cavlc.h" 40 #include "ih264d_dpb_manager.h" 41 #include "ih264d_defs.h" 42 #include "ih264d_structs.h" 43 #include "ih264d_mem_request.h" 44 #include "ih264_typedefs.h" 45 #include "ih264_macros.h" 46 #include "ih264_platform_macros.h" 47 #include "ih264d_tables.h" 48 #include "ih264d_debug.h" 49 #include "ih264d_mb_utils.h" 50 #include "ih264d_error_handler.h" 51 #include "ih264d_dpb_manager.h" 52 #include "ih264d_utils.h" 53 #include "ih264d_defs.h" 54 #include "ih264d_tables.h" 55 #include "ih264d_inter_pred.h" 56 #include "ih264d_dpb_manager.h" 57 #include "iv.h" 58 #include "ivd.h" 59 #include "ih264d_format_conv.h" 60 #include "ih264_error.h" 61 #include "ih264_disp_mgr.h" 62 #include "ih264_buf_mgr.h" 63 #include "ih264d_utils.h" 64 65 /*! 66 ************************************************************************** 67 * \if Function name : ih264d_is_end_of_pic \endif 68 * 69 * \brief 70 * Determines whether current slice is first slice of a new picture as 71 * defined in 7.4.1.2.4 of 14496-10. 72 * 73 * \return 74 * Return 1 if current slice is first slice of a new picture 75 * Otherwise it returns 0 76 ************************************************************************** 77 */ 78 UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num, 79 UWORD8 u1_nal_ref_idc, 80 pocstruct_t *ps_cur_poc, 81 pocstruct_t *ps_prev_poc, 82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/ 83 UWORD8 u1_pic_order_cnt_type, 84 UWORD8 u1_nal_unit_type, 85 UWORD32 u4_idr_pic_id, 86 UWORD8 u1_field_pic_flag, 87 UWORD8 u1_bottom_field_flag) 88 { 89 WORD8 i1_is_end_of_pic; 90 WORD8 a, b, c, d, e, f, g, h; 91 92 a = b = c = d = e = f = g = h = 0; 93 a = (ps_prev_slice->u2_frame_num != u2_frame_num); 94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag); 95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag) 96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag); 97 d = 98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0) 99 || (u1_nal_ref_idc != 0 100 && ps_prev_slice->u1_nal_ref_idc 101 == 0); 102 if(!a) 103 { 104 if((u1_pic_order_cnt_type == 0) 105 && (ps_prev_slice->u1_pic_order_cnt_type == 0)) 106 { 107 e = 108 ((ps_cur_poc->i4_pic_order_cnt_lsb 109 != ps_prev_poc->i4_pic_order_cnt_lsb) 110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom 111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom)); 112 } 113 114 if((u1_pic_order_cnt_type == 1) 115 && (ps_prev_slice->u1_pic_order_cnt_type == 1)) 116 { 117 f = 118 ((ps_cur_poc->i4_delta_pic_order_cnt[0] 119 != ps_prev_poc->i4_delta_pic_order_cnt[0]) 120 || (ps_cur_poc->i4_delta_pic_order_cnt[1] 121 != ps_prev_poc->i4_delta_pic_order_cnt[1])); 122 } 123 } 124 125 if((u1_nal_unit_type == IDR_SLICE_NAL) 126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL)) 127 { 128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id); 129 } 130 131 if((u1_nal_unit_type == IDR_SLICE_NAL) 132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL)) 133 { 134 h = 1; 135 } 136 i1_is_end_of_pic = a + b + c + d + e + f + g + h; 137 return (i1_is_end_of_pic); 138 } 139 140 /*! 141 ************************************************************************** 142 * \if Function name : ih264d_decode_pic_order_cnt \endif 143 * 144 * \brief 145 * Calculates picture order count of picture. 146 * 147 * \return 148 * Returns the pic order count of the picture to which current 149 * Slice belongs. 150 * 151 ************************************************************************** 152 */ 153 WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice, 154 UWORD32 u2_frame_num, 155 pocstruct_t *ps_prev_poc, 156 pocstruct_t *ps_cur_poc, 157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/ 158 dec_pic_params_t * ps_pps, 159 UWORD8 u1_nal_ref_idc, 160 UWORD8 u1_bottom_field_flag, 161 UWORD8 u1_field_pic_flag, 162 WORD32 *pi4_poc) 163 { 164 WORD16 i1_pic_msb; 165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0; 166 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 167 WORD32 i4_prev_frame_num_ofst; 168 169 switch(ps_seq->u1_pic_order_cnt_type) 170 { 171 case 0: 172 /* POC TYPE 0 */ 173 if(u1_is_idr_slice) 174 { 175 ps_prev_poc->i4_pic_order_cnt_msb = 0; 176 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 177 } 178 if(ps_prev_poc->u1_mmco_equalto5) 179 { 180 if(ps_prev_poc->u1_bot_field != 1) 181 { 182 ps_prev_poc->i4_pic_order_cnt_msb = 0; 183 ps_prev_poc->i4_pic_order_cnt_lsb = 184 ps_prev_poc->i4_top_field_order_count; 185 } 186 else 187 { 188 ps_prev_poc->i4_pic_order_cnt_msb = 0; 189 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 190 } 191 } 192 193 if((ps_cur_poc->i4_pic_order_cnt_lsb 194 < ps_prev_poc->i4_pic_order_cnt_lsb) 195 && ((ps_prev_poc->i4_pic_order_cnt_lsb 196 - ps_cur_poc->i4_pic_order_cnt_lsb) 197 >= (ps_seq->i4_max_pic_order_cntLsb 198 >> 1))) 199 { 200 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 201 + ps_seq->i4_max_pic_order_cntLsb; 202 } 203 else if((ps_cur_poc->i4_pic_order_cnt_lsb 204 > ps_prev_poc->i4_pic_order_cnt_lsb) 205 && ((ps_cur_poc->i4_pic_order_cnt_lsb 206 - ps_prev_poc->i4_pic_order_cnt_lsb) 207 >= (ps_seq->i4_max_pic_order_cntLsb 208 >> 1))) 209 { 210 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 211 - ps_seq->i4_max_pic_order_cntLsb; 212 } 213 else 214 { 215 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb; 216 } 217 218 if(!u1_field_pic_flag || !u1_bottom_field_flag) 219 i4_top_field_order_cnt = i1_pic_msb 220 + ps_cur_poc->i4_pic_order_cnt_lsb; 221 222 if(!u1_field_pic_flag) 223 { 224 i4_bottom_field_order_cnt = i4_top_field_order_cnt 225 + ps_cur_poc->i4_delta_pic_order_cnt_bottom; 226 } 227 else if(u1_bottom_field_flag) 228 { 229 i4_bottom_field_order_cnt = i1_pic_msb 230 + ps_cur_poc->i4_pic_order_cnt_lsb; 231 } 232 ps_cur_poc->i4_pic_order_cnt_msb = i1_pic_msb; 233 break; 234 235 case 1: 236 { 237 /* POC TYPE 1 */ 238 UWORD8 i; 239 WORD32 prev_frame_num; 240 WORD32 frame_num_ofst; 241 WORD32 abs_frm_num; 242 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle; 243 WORD32 expected_delta_poc_cycle; 244 WORD32 expected_poc; 245 246 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 247 if(!u1_is_idr_slice) 248 { 249 if(ps_cur_slice->u1_mmco_equalto5) 250 { 251 prev_frame_num = 0; 252 i4_prev_frame_num_ofst = 0; 253 } 254 else 255 { 256 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 257 } 258 } 259 else 260 i4_prev_frame_num_ofst = 0; 261 262 /* 1. Derivation for FrameNumOffset */ 263 if(u1_is_idr_slice) 264 { 265 frame_num_ofst = 0; 266 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 267 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 268 } 269 else if(prev_frame_num > ((WORD32)u2_frame_num)) 270 { 271 frame_num_ofst = i4_prev_frame_num_ofst 272 + ps_seq->u2_u4_max_pic_num_minus1 + 1; 273 } 274 else 275 frame_num_ofst = i4_prev_frame_num_ofst; 276 277 /* 2. Derivation for absFrameNum */ 278 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle) 279 abs_frm_num = frame_num_ofst + u2_frame_num; 280 else 281 abs_frm_num = 0; 282 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0)) 283 abs_frm_num = abs_frm_num - 1; 284 285 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */ 286 expected_delta_poc_cycle = 0; 287 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle; 288 i++) 289 { 290 expected_delta_poc_cycle += 291 ps_seq->i4_ofst_for_ref_frame[i]; 292 } 293 294 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and 295 frame_num_in_poc_cycle are derived as : */ 296 /* 5. expectedPicOrderCnt is derived as : */ 297 if(abs_frm_num > 0) 298 { 299 poc_cycle_cnt = 300 DIV((abs_frm_num - 1), 301 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 302 frame_num_in_poc_cycle = 303 MOD((abs_frm_num - 1), 304 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 305 306 expected_poc = poc_cycle_cnt 307 * expected_delta_poc_cycle; 308 for(i = 0; i <= frame_num_in_poc_cycle; i++) 309 { 310 expected_poc = expected_poc 311 + ps_seq->i4_ofst_for_ref_frame[i]; 312 } 313 } 314 else 315 expected_poc = 0; 316 317 if(u1_nal_ref_idc == 0) 318 { 319 expected_poc = expected_poc 320 + ps_seq->i4_ofst_for_non_ref_pic; 321 } 322 323 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 324 if(!u1_field_pic_flag) 325 { 326 i4_top_field_order_cnt = expected_poc 327 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 328 i4_bottom_field_order_cnt = i4_top_field_order_cnt 329 + ps_seq->i4_ofst_for_top_to_bottom_field 330 + ps_cur_poc->i4_delta_pic_order_cnt[1]; 331 } 332 else if(!u1_bottom_field_flag) 333 { 334 i4_top_field_order_cnt = expected_poc 335 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 336 } 337 else 338 { 339 i4_bottom_field_order_cnt = expected_poc 340 + ps_seq->i4_ofst_for_top_to_bottom_field 341 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 342 } 343 /* Copy the current POC info into Previous POC structure */ 344 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 345 } 346 347 break; 348 case 2: 349 { 350 /* POC TYPE 2 */ 351 WORD32 prev_frame_num; 352 WORD32 frame_num_ofst; 353 WORD32 tmp_poc; 354 355 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 356 if(!u1_is_idr_slice) 357 { 358 if(ps_cur_slice->u1_mmco_equalto5) 359 { 360 prev_frame_num = 0; 361 i4_prev_frame_num_ofst = 0; 362 } 363 else 364 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 365 } 366 else 367 i4_prev_frame_num_ofst = 0; 368 369 /* 1. Derivation for FrameNumOffset */ 370 if(u1_is_idr_slice) 371 { 372 frame_num_ofst = 0; 373 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 374 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 375 } 376 else if(prev_frame_num > ((WORD32)u2_frame_num)) 377 { 378 frame_num_ofst = i4_prev_frame_num_ofst 379 + ps_seq->u2_u4_max_pic_num_minus1 + 1; 380 } 381 else 382 frame_num_ofst = i4_prev_frame_num_ofst; 383 384 /* 2. Derivation for tempPicOrderCnt */ 385 if(u1_is_idr_slice) 386 tmp_poc = 0; 387 else if(u1_nal_ref_idc == 0) 388 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1) 389 - 1; 390 else 391 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1); 392 393 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 394 if(!u1_field_pic_flag) 395 { 396 i4_top_field_order_cnt = tmp_poc; 397 i4_bottom_field_order_cnt = tmp_poc; 398 } 399 else if(!u1_bottom_field_flag) 400 i4_top_field_order_cnt = tmp_poc; 401 else 402 i4_bottom_field_order_cnt = tmp_poc; 403 404 /* Copy the current POC info into Previous POC structure */ 405 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst; 406 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 407 } 408 break; 409 default: 410 return ERROR_INV_POC_TYPE_T; 411 break; 412 } 413 414 if(!u1_field_pic_flag) // or a complementary field pair 415 { 416 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt); 417 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 418 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 419 } 420 else if(!u1_bottom_field_flag) 421 { 422 *pi4_poc = i4_top_field_order_cnt; 423 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 424 } 425 else 426 { 427 *pi4_poc = i4_bottom_field_order_cnt; 428 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 429 } 430 431 ps_pps->i4_avg_poc = *pi4_poc; 432 433 return OK; 434 } 435 436 /*! 437 ************************************************************************** 438 * \if Function name : ih264d_end_of_pic_processing \endif 439 * 440 * \brief 441 * Performs the end of picture processing. 442 * 443 * It performs deblocking on the current picture and sets the i4_status of 444 * current picture as decoded. 445 * 446 * \return 447 * 0 on Success and Error code otherwise. 448 ************************************************************************** 449 */ 450 WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec) 451 { 452 UWORD8 u1_pic_type, u1_nal_ref_idc; 453 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice; 454 WORD32 ret; 455 456 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL 457 unit of a particular picture, it shall be equal to 0 for all slice and 458 slice data partition NAL units of the picture. nal_ref_idc greater 459 than 0 indicates that the content of the NAL unit belongs to a decoded 460 picture that is stored and marked for use as a reference picture in the 461 decoded picture buffer. */ 462 463 /* 1. Do MMCO 464 2. Add Cur Pic to list of reference pics. 465 */ 466 467 /* Call MMCO */ 468 u1_pic_type = 0; 469 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc; 470 471 if(u1_nal_ref_idc) 472 { 473 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 474 { 475 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0) 476 { 477 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 478 479 { 480 ret = ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 481 ps_dec->ps_cur_pic, 482 ps_dec->u1_pic_buf_id, 483 ps_cur_slice->u2_frame_num); 484 if(ret != OK) 485 return ret; 486 } 487 } 488 else 489 { 490 /* Equivalent of inserting a pic directly as longterm Pic */ 491 492 { 493 ret = ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 494 ps_dec->ps_cur_pic, 495 ps_dec->u1_pic_buf_id, 496 ps_cur_slice->u2_frame_num); 497 if(ret != OK) 498 return ret; 499 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */ 500 ret = ih264d_delete_st_node_or_make_lt( 501 ps_dec->ps_dpb_mgr, 502 ps_cur_slice->u2_frame_num, 0, 503 ps_cur_slice->u1_field_pic_flag); 504 if(ret != OK) 505 return ret; 506 ps_dec->ps_dpb_mgr->u1_max_lt_pic_idx_plus1 = 1; 507 } 508 } 509 } 510 else 511 { 512 513 { 514 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num; 515 516 517 518 ret = ih264d_do_mmco_buffer( 519 ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr, 520 ps_dec->ps_cur_sps->u1_num_ref_frames, 521 u2_pic_num, 522 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1), 523 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic, 524 ps_dec->u1_pic_buf_id, 525 ps_cur_slice->u1_field_pic_flag, 526 ps_dec->e_dec_status); 527 if(ret != OK) 528 return ret; 529 } 530 } 531 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr); 532 } 533 534 if(ps_cur_slice->u1_field_pic_flag) 535 { 536 if(ps_cur_slice->u1_bottom_field_flag) 537 { 538 if(u1_nal_ref_idc) 539 u1_pic_type = u1_pic_type | BOT_REF; 540 u1_pic_type = u1_pic_type | BOT_FLD; 541 } 542 else 543 { 544 if(u1_nal_ref_idc) 545 u1_pic_type = u1_pic_type | TOP_REF; 546 u1_pic_type = u1_pic_type | TOP_FLD; 547 } 548 } 549 else 550 u1_pic_type = TOP_REF | BOT_REF; 551 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type; 552 553 #if ROW_ACCESSES_STAT 554 { 555 H264_DEC_DEBUG_PRINT("Row_Accesses_BeforeBB = %6d, Row_Accesses_AfterBB = %6d \n\n", 556 gui_Row_Accesses_BeforeBB, gui_Row_Accesses_AfterBB); 557 gui_Row_Accesses_BeforeBBTotal += gui_Row_Accesses_BeforeBB; 558 gui_Row_Accesses_AfterBBTotal += gui_Row_Accesses_AfterBB; 559 gui_Row_Accesses_AfterBB = 0; 560 gui_Row_Accesses_BeforeBB = 0; 561 } 562 #endif 563 564 if(ps_cur_slice->u1_field_pic_flag) 565 { 566 H264_DEC_DEBUG_PRINT("Toggling secondField\n"); 567 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field; 568 } 569 570 return OK; 571 } 572 573 /*****************************************************************************/ 574 /* */ 575 /* Function Name : init_dpb_size */ 576 /* */ 577 /* Description : This function calculates the DBP i4_size in frames */ 578 /* Inputs : ps_seq - current sequence params */ 579 /* */ 580 /* Globals : None */ 581 /* */ 582 /* Outputs : None */ 583 /* */ 584 /* Returns : DPB in frames */ 585 /* */ 586 /* Issues : None */ 587 /* */ 588 /* Revision History: */ 589 /* */ 590 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 591 /* 28 04 2005 NS Draft */ 592 /* */ 593 /*****************************************************************************/ 594 WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq, dec_struct_t *ps_dec) 595 { 596 WORD32 i4_size; 597 UWORD8 u1_level_idc; 598 599 u1_level_idc = ps_seq->u1_level_idc; //harcode for the time being 600 u1_level_idc = MIN(u1_level_idc, ps_dec->u4_level_at_init); 601 602 switch(u1_level_idc) 603 { 604 case 10: 605 i4_size = 152064; 606 break; 607 case 11: 608 i4_size = 345600; 609 break; 610 case 12: 611 i4_size = 912384; 612 break; 613 case 13: 614 i4_size = 912384; 615 break; 616 case 20: 617 i4_size = 912384; 618 break; 619 case 21: 620 i4_size = 1824768; 621 break; 622 case 22: 623 i4_size = 3110400; 624 break; 625 case 30: 626 i4_size = 3110400; 627 break; 628 case 31: 629 i4_size = 6912000; 630 break; 631 case 32: 632 i4_size = 7864320; 633 break; 634 case 40: 635 i4_size = 12582912; 636 break; 637 case 41: 638 i4_size = 12582912; 639 break; 640 case 42: 641 i4_size = 12582912; 642 break; 643 case 50: 644 i4_size = 42393600; 645 break; 646 case 51: 647 i4_size = 70778880; 648 break; 649 case 52: 650 i4_size = 70778880; 651 break; 652 default: 653 i4_size = 70778880; 654 break; 655 } 656 657 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag))); 658 i4_size /= 384; 659 i4_size = MIN(i4_size, 16); 660 i4_size = MAX(i4_size, 1); 661 return (i4_size); 662 } 663 664 WORD32 ih264d_get_dpb_size_new(UWORD32 u4_level_idc, 665 UWORD32 u2_frm_wd_in_mbs, 666 UWORD32 u2_frm_ht_in_mbs) 667 { 668 669 UWORD32 i4_size = 0; 670 671 switch(u4_level_idc) 672 { 673 case 10: 674 i4_size = 152064; 675 break; 676 case 11: 677 i4_size = 345600; 678 break; 679 case 12: 680 i4_size = 912384; 681 break; 682 case 13: 683 i4_size = 912384; 684 break; 685 case 20: 686 i4_size = 912384; 687 break; 688 case 21: 689 i4_size = 1824768; 690 break; 691 case 22: 692 i4_size = 3110400; 693 break; 694 case 30: 695 i4_size = 3110400; 696 break; 697 case 31: 698 i4_size = 6912000; 699 break; 700 case 32: 701 i4_size = 7864320; 702 break; 703 case 40: 704 i4_size = 12582912; 705 break; 706 case 41: 707 i4_size = 12582912; 708 break; 709 case 42: 710 i4_size = 12582912; 711 break; 712 case 50: 713 i4_size = 42393600; 714 break; 715 case 51: 716 i4_size = 70778880; 717 break; 718 case 52: 719 i4_size = 70778880; 720 break; 721 default: 722 { 723 i4_size = 70778880; 724 } 725 break; 726 } 727 728 i4_size = i4_size / (u2_frm_wd_in_mbs * (u2_frm_ht_in_mbs)); 729 i4_size = (i4_size + 383) / 384; 730 i4_size = MIN(i4_size, 16); 731 i4_size = MAX(i4_size, 1); 732 return (i4_size); 733 } 734 735 /*****************************************************************************/ 736 /* */ 737 /* Function Name : ih264d_max_possible_ref_pics */ 738 /* */ 739 /* Description : This function returns the maximum number of */ 740 /* reference buffers corresponding to the current Level */ 741 /* in accordance to "Table A-1 Level limits" in standard. */ 742 /* Please refer to Annex A - Profiles and Levels */ 743 /* Maximum Number of reference buffers are derived from */ 744 /* the dbpsize and max_mbs_in frame given in the table */ 745 /* Inputs : level number */ 746 /* */ 747 /* Revision History: */ 748 /* */ 749 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 750 /* 19 05 2005 SWRN Draft */ 751 /* */ 752 /*****************************************************************************/ 753 754 UWORD8 ih264d_max_possible_ref_pics(UWORD8 u1_level) 755 { 756 switch(u1_level) 757 { 758 case H264_LEVEL_1_0: 759 return (MAX_REF_LEVEL_1_0); 760 case H264_LEVEL_1_1: 761 return (MAX_REF_LEVEL_1_1); 762 case H264_LEVEL_1_2: 763 return (MAX_REF_LEVEL_1_2); 764 case H264_LEVEL_1_3: 765 return (MAX_REF_LEVEL_1_3); 766 case H264_LEVEL_2_0: 767 return (MAX_REF_LEVEL_2_0); 768 case H264_LEVEL_2_1: 769 return (MAX_REF_LEVEL_2_1); 770 case H264_LEVEL_2_2: 771 return (MAX_REF_LEVEL_2_2); 772 case H264_LEVEL_3_0: 773 return (MAX_REF_LEVEL_3_0); 774 } 775 776 return (H264_MAX_REF_PICS); 777 } 778 779 /***************************************************************************/ 780 /* If change in Level or the required PicBuffers i4_size is more than the */ 781 /* current one FREE the current PicBuffers and allocate affresh */ 782 /***************************************************************************/ 783 UWORD8 ih264d_is_sps_changed(prev_seq_params_t * ps_prv, 784 dec_seq_params_t * ps_cur) 785 { 786 787 if((ps_prv->u2_frm_wd_in_mbs != ps_cur->u2_frm_wd_in_mbs) 788 || (ps_prv->u1_level_idc != ps_cur->u1_level_idc) 789 || (ps_prv->u1_profile_idc != ps_cur->u1_profile_idc) 790 || (ps_cur->u2_frm_ht_in_mbs != ps_prv->u2_frm_ht_in_mbs) 791 || (ps_cur->u1_frame_mbs_only_flag 792 != ps_prv->u1_frame_mbs_only_flag) 793 || (ps_cur->u1_direct_8x8_inference_flag 794 != ps_prv->u1_direct_8x8_inference_flag)) 795 return 1; 796 797 return 0; 798 } 799 800 /**************************************************************************/ 801 /* This function initialises the value of ps_dec->u1_recon_mb_grp */ 802 /* ps_dec->u1_recon_mb_grp must satisfy the following criteria */ 803 /* - multiple of 2 (required for N/2 parse-mvpred design) */ 804 /* - multiple of 4 (if it is not a frame_mbs_only sequence), */ 805 /* in this case N/2 itself needs to be even for mbpair processing */ 806 /* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */ 807 /* should make a row to ensure proper MvTop transferring) */ 808 /**************************************************************************/ 809 WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec) 810 { 811 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps; 812 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag; 813 814 ps_dec->u1_recon_mb_grp = PARSE_MB_GROUP_4; 815 816 //NMB set to width in MBs for non-mbaff cases 817 if(0 == ps_seq->u1_mb_aff_flag) 818 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs; 819 820 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1; 821 822 if(!ps_dec->u1_recon_mb_grp) 823 { 824 return ERROR_MB_GROUP_ASSGN_T; 825 } 826 827 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp; 828 829 return OK; 830 } 831 832 /*! 833 ************************************************************************** 834 * \if Function name : ih264d_get_numbuf_dpb_bank \endif 835 * 836 * \brief 837 * Initializes the picture. 838 * 839 * \return 840 * 0 on Success and Error code otherwise 841 * 842 * \note 843 * This function is called when first slice of the 844 * NON -IDR picture is encountered. 845 ************************************************************************** 846 */ 847 WORD32 ih264d_get_numbuf_dpb_bank(dec_struct_t *ps_dec, UWORD32 u4_frame_wd, UWORD32 u4_frame_ht) 848 { 849 WORD32 i4_DPB_size; 850 WORD32 i4_pic_size; 851 WORD32 i4_num_buf_alloc; 852 UWORD32 Ysize; 853 UWORD32 UVsize; 854 UWORD32 one_frm_size; 855 856 857 i4_DPB_size = ps_dec->ps_mem_tab[MEM_REC_REF_PIC].u4_mem_size; 858 859 Ysize = u4_frame_wd * u4_frame_ht; 860 861 UVsize = Ysize >> 2; 862 863 { 864 if(ps_dec->u4_share_disp_buf == 1) 865 { 866 /* In case of buffers getting shared between application and library 867 there is no need of reference memtabs. Instead of setting the i4_size 868 to zero, it is reduced to a small i4_size to ensure that changes 869 in the code are minimal */ 870 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 871 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 872 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 873 { 874 Ysize = 64; 875 } 876 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 877 { 878 UVsize = 64; 879 } 880 881 } 882 } 883 884 one_frm_size = (((Ysize + 127) >> 7) << 7) 885 + ((((UVsize << 1) + 127) >> 7) << 7); 886 i4_num_buf_alloc = i4_DPB_size / (one_frm_size); 887 888 return i4_num_buf_alloc; 889 } 890 891 /*! 892 ************************************************************************** 893 * \if Function name : ih264d_get_numbuf_mv_bank \endif 894 * 895 * \brief 896 * Computes number of MVbank buffers that can be allocated. 897 * 898 * \return 899 * Number of MV bank buffers that can be allocated. 900 * 901 * \note 902 ************************************************************************** 903 */ 904 UWORD32 ih264d_get_numbuf_mv_bank(dec_struct_t *ps_dec, UWORD32 width, 905 UWORD32 height) 906 { 907 UWORD32 u4_mv_bank_size,one_frame_size; 908 UWORD32 u4_num_buf_alloc; 909 910 u4_mv_bank_size = ps_dec->ps_mem_tab[MEM_REC_MVBANK].u4_mem_size; 911 one_frame_size = sizeof(mv_pred_t) 912 * ((width * (height + PAD_MV_BANK_ROW)) >> 4); 913 u4_num_buf_alloc = u4_mv_bank_size / one_frame_size; 914 return u4_num_buf_alloc; 915 } 916 /*! 917 ************************************************************************** 918 * \if Function name : ih264d_init_pic \endif 919 * 920 * \brief 921 * Initializes the picture. 922 * 923 * \return 924 * 0 on Success and Error code otherwise 925 * 926 * \note 927 * This function is called when first slice of the 928 * NON -IDR picture is encountered. 929 ************************************************************************** 930 */ 931 WORD32 ih264d_init_pic(dec_struct_t *ps_dec, 932 UWORD16 u2_frame_num, 933 WORD32 i4_poc, 934 dec_pic_params_t *ps_pps) 935 { 936 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 937 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params; 938 WORD32 i4_pic_bufs; 939 WORD32 ret; 940 941 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num; 942 ps_dec->ps_cur_slice->i4_poc = i4_poc; 943 ps_dec->ps_cur_pps = ps_pps; 944 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec; 945 946 ps_dec->ps_cur_sps = ps_seq; 947 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1 948 + 1; 949 950 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht; 951 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd; 952 ps_dec->i4_pic_type = -1; 953 ps_dec->i4_frametype = -1; 954 ps_dec->i4_content_type = -1; 955 956 /*--------------------------------------------------------------------*/ 957 /* Get the value of MaxMbAddress and frmheight in Mbs */ 958 /*--------------------------------------------------------------------*/ 959 ps_seq->u2_max_mb_addr = 960 (ps_seq->u2_frm_wd_in_mbs 961 * (ps_dec->u2_pic_ht 962 >> (4 963 + ps_dec->ps_cur_slice->u1_field_pic_flag))) 964 - 1; 965 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht 966 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag)); 967 968 /***************************************************************************/ 969 /* If change in Level or the required PicBuffers i4_size is more than the */ 970 /* current one FREE the current PicBuffers and allocate affresh */ 971 /***************************************************************************/ 972 if(!ps_dec->u1_init_dec_flag 973 || ih264d_is_sps_changed(ps_prev_seq_params, ps_seq)) 974 { 975 976 977 ivd_video_decode_ip_t *ps_dec_in = ps_dec->pv_dec_in; 978 ivd_video_decode_op_t *ps_dec_out = ps_dec->pv_dec_out; 979 980 if(ps_dec->u4_share_disp_buf == 0) 981 { 982 i4_pic_bufs = ih264d_get_numbuf_dpb_bank(ps_dec, ps_dec->u2_frm_wd_y, 983 ps_dec->u2_frm_ht_y); 984 } 985 else 986 { 987 i4_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs; 988 } 989 990 ps_dec->u1_pic_bufs = CLIP_U8(i4_pic_bufs); 991 992 if(ps_dec->u4_share_disp_buf == 0) 993 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs, 994 (H264_MAX_REF_PICS * 2)); 995 996 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq, 997 ps_dec); 998 999 ps_dec->u1_max_dec_frame_buffering = MIN( 1000 ps_dec->u1_max_dec_frame_buffering, 1001 ps_dec->u4_num_ref_frames_at_init); 1002 ps_dec->u1_max_dec_frame_buffering = MIN( 1003 ps_dec->u1_max_dec_frame_buffering, 1004 ps_dec->u1_pic_bufs); 1005 1006 // ps_dec->u1_pic_bufs = ps_dec->i1_max_dec_frame_buffering; 1007 1008 /* Fix is for handling one pic in and one pic out incase of */ 1009 /* MMCO 5 or IDR */ 1010 1011 ps_dec->i4_display_delay = MIN(ps_dec->u4_num_reorder_frames_at_init, 1012 ps_dec->u1_max_dec_frame_buffering); 1013 1014 if(1 == ps_seq->u1_vui_parameters_present_flag) 1015 { 1016 if(ps_seq->u1_frame_mbs_only_flag == 1) 1017 ps_dec->i4_display_delay = MIN( 1018 (UWORD32 )ps_dec->i4_display_delay, 1019 ((UWORD32 )ps_seq->s_vui.u4_num_reorder_frames 1020 + 1)); 1021 else 1022 ps_dec->i4_display_delay = MIN( 1023 (UWORD32 )ps_dec->i4_display_delay, 1024 ((UWORD32 )ps_seq->s_vui.u4_num_reorder_frames 1025 + 1) * 2); 1026 } 1027 1028 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/ 1029 if(ps_dec->u1_init_dec_flag) 1030 { 1031 ih264d_release_pics_in_dpb((void *)ps_dec, 1032 ps_dec->u1_pic_bufs); 1033 ih264d_release_display_bufs(ps_dec); 1034 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 1035 } 1036 1037 /*********************************************************************/ 1038 /* Configuring decoder parameters based on level and then */ 1039 /* fresh pointer initialisation in decoder scratch and state buffers */ 1040 /*********************************************************************/ 1041 if(!ps_dec->u1_init_dec_flag || 1042 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0))) 1043 { 1044 ret = ih264d_init_dec_mb_grp(ps_dec); 1045 if(ret != OK) 1046 return ret; 1047 } 1048 1049 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs, 1050 ps_dec); 1051 if(ret != OK) 1052 return ret; 1053 1054 ih264d_get_memory_dec_params(ps_dec); 1055 1056 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd, 1057 ps_dec->u2_pic_ht); 1058 if(ret != OK) 1059 return ret; 1060 1061 /* In shared mode, set all of them as used by display */ 1062 if(ps_dec->u4_share_disp_buf == 1) 1063 { 1064 WORD32 i; 1065 1066 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1067 { 1068 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 1069 BUF_MGR_IO); 1070 } 1071 } 1072 1073 ps_dec->u1_init_dec_flag = 1; 1074 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs; 1075 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc; 1076 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc; 1077 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs; 1078 ps_prev_seq_params->u1_frame_mbs_only_flag = 1079 ps_seq->u1_frame_mbs_only_flag; 1080 ps_prev_seq_params->u1_direct_8x8_inference_flag = 1081 ps_seq->u1_direct_8x8_inference_flag; 1082 1083 ps_dec->i4_cur_display_seq = 0; 1084 ps_dec->i4_prev_max_display_seq = 0; 1085 ps_dec->i4_max_poc = 0; 1086 1087 { 1088 /* 0th entry of CtxtIncMbMap will be always be containing default values 1089 for CABAC context representing MB not available */ 1090 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1; 1091 UWORD8 *pu1_temp; 1092 WORD8 i; 1093 p_DefCtxt->u1_mb_type = CAB_SKIP; 1094 1095 p_DefCtxt->u1_cbp = 0x0f; 1096 p_DefCtxt->u1_intra_chroma_pred_mode = 0; 1097 1098 p_DefCtxt->u1_yuv_dc_csbp = 0x7; 1099 1100 p_DefCtxt->u1_transform8x8_ctxt = 0; 1101 1102 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx; 1103 for(i = 0; i < 4; i++, pu1_temp++) 1104 (*pu1_temp) = 0; 1105 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv; 1106 for(i = 0; i < 16; i++, pu1_temp++) 1107 (*pu1_temp) = 0; 1108 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt; 1109 } 1110 1111 } 1112 /* reset DBP commands read u4_flag */ 1113 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0; 1114 1115 return OK; 1116 } 1117 1118 /*****************************************************************************/ 1119 /* */ 1120 /* Function Name : ih264d_get_next_display_field */ 1121 /* */ 1122 /* Description : Application calls this module to get the next field */ 1123 /* to be displayed */ 1124 /* */ 1125 /* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */ 1126 /* 2. IH264DEC_DispUnit Pointer to the display struct */ 1127 /* */ 1128 /* Globals : */ 1129 /* */ 1130 /* */ 1131 /* Processing : None */ 1132 /* Outputs : None */ 1133 /* Returns : None */ 1134 /* Issues : None */ 1135 /* */ 1136 /* Revision History: */ 1137 /* */ 1138 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1139 /* 27 05 2005 Ittiam Draft */ 1140 /* */ 1141 /*****************************************************************************/ 1142 1143 WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec, 1144 ivd_out_bufdesc_t *ps_out_buffer, 1145 ivd_get_display_frame_op_t *pv_disp_op) 1146 { 1147 pic_buffer_t *pic_buf; 1148 1149 UWORD8 i1_cur_fld; 1150 WORD32 u4_api_ret = -1; 1151 WORD32 i4_disp_buf_id; 1152 iv_yuv_buf_t *ps_op_frm; 1153 1154 1155 1156 ps_op_frm = &(ps_dec->s_disp_frame_info); 1157 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1158 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get( 1159 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id); 1160 ps_dec->u4_num_fld_in_frm = 0; 1161 u4_api_ret = -1; 1162 pv_disp_op->u4_ts = -1; 1163 pv_disp_op->e_output_format = ps_dec->u1_chroma_format; 1164 1165 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0]; 1166 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1]; 1167 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2]; 1168 if(pic_buf != NULL) 1169 { 1170 pv_disp_op->e4_fld_type = 0; 1171 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id; 1172 1173 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1; 1174 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1; 1175 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width; 1176 1177 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1; 1178 1179 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y; 1180 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv; 1181 1182 /* ! */ 1183 pv_disp_op->u4_ts = pic_buf->u4_ts; 1184 1185 /* set the start of the Y, U and V buffer pointer for display */ 1186 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y; 1187 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv; 1188 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv; 1189 ps_dec->u4_num_fld_in_frm++; 1190 ps_dec->u4_num_fld_in_frm++; 1191 u4_api_ret = 0; 1192 1193 if(pic_buf->u1_picturetype == 0) 1194 pv_disp_op->u4_progressive_frame_flag = 1; 1195 else 1196 pv_disp_op->u4_progressive_frame_flag = 0; 1197 1198 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1199 pv_disp_op->u4_error_code = u4_api_ret; 1200 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk; 1201 1202 if(u4_api_ret) 1203 { 1204 pv_disp_op->u4_error_code = 1; //put a proper error code here 1205 } 1206 else 1207 { 1208 1209 //Release the buffer if being sent for display 1210 UWORD32 temp; 1211 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0; 1212 1213 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd, 1214 ps_op_frm->u4_y_strd); 1215 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 1216 >> 1; 1217 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 1218 >> 1; 1219 1220 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht; 1221 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 1222 >> 1; 1223 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 1224 >> 1; 1225 if(0 == ps_dec->u4_share_disp_buf) 1226 { 1227 pv_disp_op->s_disp_frm_buf.u4_y_strd = 1228 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1229 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1230 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 1231 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1232 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 1233 1234 } 1235 else 1236 { 1237 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd; 1238 } 1239 1240 if(ps_dec->u4_app_disp_width) 1241 { 1242 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX( 1243 ps_dec->u4_app_disp_width, 1244 pv_disp_op->s_disp_frm_buf.u4_y_strd); 1245 } 1246 1247 pv_disp_op->u4_error_code = 0; 1248 if(pv_disp_op->e_output_format == IV_YUV_420P) 1249 { 1250 UWORD32 i; 1251 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1252 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1253 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1254 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1255 1256 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1; 1257 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1; 1258 1259 if(1 == ps_dec->u4_share_disp_buf) 1260 { 1261 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1262 1263 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1264 { 1265 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1266 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1267 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1268 - pic_buf->u2_crop_offset_y) == buf) 1269 { 1270 buf = ps_dec->disp_bufs[i].buf[1]; 1271 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1272 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1273 + pic_buf->u2_crop_offset_uv; 1274 1275 buf = ps_dec->disp_bufs[i].buf[2]; 1276 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1277 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1278 + pic_buf->u2_crop_offset_uv; 1279 } 1280 } 1281 } 1282 1283 } 1284 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV) 1285 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU)) 1286 { 1287 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1288 pv_disp_op->s_disp_frm_buf.u4_y_strd; 1289 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1290 1291 if(1 == ps_dec->u4_share_disp_buf) 1292 { 1293 UWORD32 i; 1294 1295 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1296 1297 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1298 { 1299 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1300 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1301 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1302 - pic_buf->u2_crop_offset_y == buf) 1303 { 1304 buf = ps_dec->disp_bufs[i].buf[1]; 1305 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1306 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1307 + pic_buf->u2_crop_offset_uv; 1308 ; 1309 1310 buf = ps_dec->disp_bufs[i].buf[2]; 1311 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1312 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1313 + pic_buf->u2_crop_offset_uv; 1314 ; 1315 } 1316 } 1317 } 1318 pv_disp_op->s_disp_frm_buf.u4_u_wd = 1319 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1320 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1321 1322 } 1323 else if((pv_disp_op->e_output_format == IV_RGB_565) 1324 || (pv_disp_op->e_output_format == IV_YUV_422ILE)) 1325 { 1326 1327 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0; 1328 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1329 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0; 1330 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1331 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0; 1332 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0; 1333 1334 } 1335 1336 1337 } 1338 1339 return u4_api_ret; 1340 } 1341 1342 1343 /*****************************************************************************/ 1344 /* Function Name : ih264d_release_display_field */ 1345 /* */ 1346 /* Description : This function releases the display field that was returned */ 1347 /* here. */ 1348 /* Inputs : ps_dec - Decoder parameters */ 1349 /* Globals : None */ 1350 /* Processing : Refer bumping process in the standard */ 1351 /* Outputs : Assigns display sequence number. */ 1352 /* Returns : None */ 1353 /* */ 1354 /* Issues : None */ 1355 /* */ 1356 /* Revision History: */ 1357 /* */ 1358 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1359 /* 27 04 2005 NS Draft */ 1360 /* */ 1361 /*****************************************************************************/ 1362 void ih264d_release_display_field(dec_struct_t *ps_dec, 1363 ivd_get_display_frame_op_t *pv_disp_op) 1364 { 1365 if(1 == pv_disp_op->u4_error_code) 1366 { 1367 if(1 == ps_dec->u1_flushfrm) 1368 { 1369 UWORD32 i; 1370 1371 if(1 == ps_dec->u4_share_disp_buf) 1372 { 1373 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1374 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1375 { 1376 if(1 == ps_dec->u4_disp_buf_mapping[i]) 1377 { 1378 ih264_buf_mgr_release( 1379 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 1380 BUF_MGR_IO); 1381 ps_dec->u4_disp_buf_mapping[i] = 0; 1382 } 1383 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1384 1385 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1386 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1387 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1388 ps_dec->u4_disp_buf_mapping[i] = 1; 1389 } 1390 ps_dec->u1_flushfrm = 0; 1391 1392 } 1393 } 1394 else 1395 { 1396 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1397 1398 if(0 == ps_dec->u4_share_disp_buf) 1399 { 1400 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1401 pv_disp_op->u4_disp_buf_id, 1402 BUF_MGR_IO); 1403 1404 } 1405 else 1406 { 1407 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1; 1408 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1409 1410 } 1411 } 1412 /*****************************************************************************/ 1413 /* Function Name : ih264d_assign_display_seq */ 1414 /* */ 1415 /* Description : This function implments bumping process. Every outgoing */ 1416 /* frame from DPB is assigned a display sequence number */ 1417 /* which increases monotonically. System looks for this */ 1418 /* number to display a frame. */ 1419 /* here. */ 1420 /* Inputs : ps_dec - Decoder parameters */ 1421 /* Globals : None */ 1422 /* Processing : Refer bumping process in the standard */ 1423 /* Outputs : Assigns display sequence number. */ 1424 /* Returns : None */ 1425 /* */ 1426 /* Issues : None */ 1427 /* */ 1428 /* Revision History: */ 1429 /* */ 1430 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1431 /* 27 04 2005 NS Draft */ 1432 /* */ 1433 /*****************************************************************************/ 1434 WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec) 1435 { 1436 WORD32 i; 1437 WORD32 i4_min_poc; 1438 WORD32 i4_min_poc_buf_id; 1439 WORD32 i4_min_index; 1440 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1441 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1442 1443 i4_min_poc = 0x7fffffff; 1444 i4_min_poc_buf_id = -1; 1445 i4_min_index = -1; 1446 1447 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay) 1448 { 1449 for(i = 0; i < MAX_FRAMES; i++) 1450 { 1451 if((i4_poc_buf_id_map[i][0] != -1) 1452 && (DO_NOT_DISP 1453 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0])) 1454 { 1455 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1456 { 1457 i4_min_poc = i4_poc_buf_id_map[i][1]; 1458 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1459 i4_min_index = i; 1460 } 1461 } 1462 } 1463 1464 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id)) 1465 { 1466 ps_dec->i4_cur_display_seq++; 1467 ih264_disp_mgr_add( 1468 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1469 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1470 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1471 i4_poc_buf_id_map[i4_min_index][0] = -1; 1472 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1473 ps_dpb_mgr->i1_poc_buf_id_entries--; 1474 } 1475 else if(DO_NOT_DISP == i4_min_poc_buf_id) 1476 { 1477 WORD32 i4_error_code; 1478 i4_error_code = ERROR_GAPS_IN_FRM_NUM; 1479 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1480 return i4_error_code; 1481 } 1482 } 1483 return OK; 1484 } 1485 1486 /*****************************************************************************/ 1487 /* */ 1488 /* Function Name : ih264d_release_display_bufs */ 1489 /* */ 1490 /* Description : This function implments bumping process when mmco = 5. */ 1491 /* Each outgoing frame from DPB is assigned a display */ 1492 /* sequence number which increases monotonically. System */ 1493 /* looks for this number to display a frame. */ 1494 /* Inputs : ps_dec - Decoder parameters */ 1495 /* Globals : None */ 1496 /* Processing : Refer bumping process in the standard for mmco = 5 */ 1497 /* Outputs : Assigns display sequence number. */ 1498 /* Returns : None */ 1499 /* */ 1500 /* Issues : None */ 1501 /* */ 1502 /* Revision History: */ 1503 /* */ 1504 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1505 /* 27 04 2005 NS Draft */ 1506 /* */ 1507 /*****************************************************************************/ 1508 void ih264d_release_display_bufs(dec_struct_t *ps_dec) 1509 { 1510 WORD32 i, j; 1511 WORD32 i4_min_poc; 1512 WORD32 i4_min_poc_buf_id; 1513 WORD32 i4_min_index; 1514 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1515 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1516 1517 i4_min_poc = 0x7fffffff; 1518 i4_min_poc_buf_id = -1; 1519 i4_min_index = -1; 1520 1521 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1522 1523 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++) 1524 { 1525 i4_min_poc = 0x7fffffff; 1526 for(i = 0; i < MAX_FRAMES; i++) 1527 { 1528 if(i4_poc_buf_id_map[i][0] != -1) 1529 { 1530 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1531 { 1532 i4_min_poc = i4_poc_buf_id_map[i][1]; 1533 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1534 i4_min_index = i; 1535 } 1536 } 1537 } 1538 1539 if(DO_NOT_DISP != i4_min_poc_buf_id) 1540 { 1541 ps_dec->i4_cur_display_seq++; 1542 ih264_disp_mgr_add( 1543 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1544 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1545 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1546 i4_poc_buf_id_map[i4_min_index][0] = -1; 1547 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1548 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1549 } 1550 else 1551 { 1552 i4_poc_buf_id_map[i4_min_index][0] = -1; 1553 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1554 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1555 } 1556 } 1557 ps_dpb_mgr->i1_poc_buf_id_entries = 0; 1558 ps_dec->i4_prev_max_display_seq = ps_dec->i4_prev_max_display_seq 1559 + ps_dec->i4_max_poc + ps_dec->u1_max_dec_frame_buffering 1560 + 1; 1561 ps_dec->i4_max_poc = 0; 1562 } 1563 1564 /*****************************************************************************/ 1565 /* */ 1566 /* Function Name : ih264d_assign_pic_num */ 1567 /* */ 1568 /* Description : This function assigns pic num to each reference frame */ 1569 /* depending on the cur_frame_num as speified in section */ 1570 /* 8.2.4.1 */ 1571 /* */ 1572 /* Inputs : ps_dec */ 1573 /* */ 1574 /* Globals : NO globals used */ 1575 /* */ 1576 /* Processing : for all ST pictures */ 1577 /* if( FrameNum > cur_frame_num) */ 1578 /* PicNum = FrameNum - MaxFrameNum */ 1579 /* else */ 1580 /* PicNum = FrameNum */ 1581 /* */ 1582 /* Returns : void */ 1583 /* */ 1584 /* Issues : NO */ 1585 /* */ 1586 /* Revision History: */ 1587 /* */ 1588 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1589 /* 13 07 2002 Jay Draft */ 1590 /* */ 1591 /*****************************************************************************/ 1592 1593 void ih264d_assign_pic_num(dec_struct_t *ps_dec) 1594 { 1595 dpb_manager_t *ps_dpb_mgr; 1596 struct dpb_info_t *ps_next_dpb; 1597 WORD8 i; 1598 WORD32 i4_cur_frame_num, i4_max_frame_num; 1599 WORD32 i4_ref_frame_num; 1600 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag; 1601 1602 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1603 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num; 1604 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1605 1606 /* Start from ST head */ 1607 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head; 1608 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++) 1609 { 1610 WORD32 i4_pic_num; 1611 1612 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num; 1613 if(i4_ref_frame_num > i4_cur_frame_num) 1614 { 1615 /* RefPic Buf frame_num is before Current frame_num in decode order */ 1616 i4_pic_num = i4_ref_frame_num - i4_max_frame_num; 1617 } 1618 else 1619 { 1620 /* RefPic Buf frame_num is after Current frame_num in decode order */ 1621 i4_pic_num = i4_ref_frame_num; 1622 } 1623 1624 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num; 1625 ps_next_dpb->i4_frame_num = i4_pic_num; 1626 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1627 if(u1_fld_pic_flag) 1628 { 1629 /* Assign the pic num to top fields and bot fields */ 1630 1631 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2 1632 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag); 1633 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2 1634 + ps_dec->ps_cur_slice->u1_bottom_field_flag; 1635 } 1636 /* Chase the next link */ 1637 ps_next_dpb = ps_next_dpb->ps_prev_short; 1638 } 1639 1640 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag 1641 && ps_dpb_mgr->u1_num_gaps) 1642 { 1643 WORD32 i4_start_frm, i4_end_frm; 1644 /* Assign pic numbers for gaps */ 1645 for(i = 0; i < MAX_FRAMES; i++) 1646 { 1647 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i]; 1648 if(i4_start_frm != INVALID_FRAME_NUM) 1649 { 1650 if(i4_start_frm > i4_cur_frame_num) 1651 { 1652 /* gap's frame_num is before Current frame_num in 1653 decode order */ 1654 i4_start_frm -= i4_max_frame_num; 1655 } 1656 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm; 1657 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i]; 1658 1659 if(i4_end_frm > i4_cur_frame_num) 1660 { 1661 /* gap's frame_num is before Current frame_num in 1662 decode order */ 1663 i4_end_frm -= i4_max_frame_num; 1664 } 1665 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm; 1666 } 1667 } 1668 } 1669 } 1670 1671 /*! 1672 ************************************************************************** 1673 * \if Function name : ih264d_update_qp \endif 1674 * 1675 * \brief 1676 * Updates the values of QP and its related entities 1677 * 1678 * \return 1679 * 0 on Success and Error code otherwise 1680 * 1681 ************************************************************************** 1682 */ 1683 WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp) 1684 { 1685 WORD32 i_temp; 1686 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52; 1687 1688 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25)) 1689 return ERROR_INV_RANGE_QP_T; 1690 1691 ps_dec->u1_qp = i_temp; 1692 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6; 1693 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6; 1694 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset); 1695 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1696 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1697 1698 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset); 1699 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1700 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1701 1702 ps_dec->pu2_quant_scale_y = 1703 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6]; 1704 ps_dec->pu2_quant_scale_u = 1705 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6]; 1706 ps_dec->pu2_quant_scale_v = 1707 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6]; 1708 return OK; 1709 } 1710 1711 /*****************************************************************************/ 1712 /* */ 1713 /* Function Name : ih264d_decode_gaps_in_frame_num */ 1714 /* */ 1715 /* Description : This function decodes gaps in frame number */ 1716 /* */ 1717 /* Inputs : ps_dec Decoder parameters */ 1718 /* u2_frame_num current frame number */ 1719 /* */ 1720 /* Globals : None */ 1721 /* Processing : This functionality needs to be implemented */ 1722 /* Outputs : None */ 1723 /* Returns : None */ 1724 /* */ 1725 /* Issues : Not implemented */ 1726 /* */ 1727 /* Revision History: */ 1728 /* */ 1729 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1730 /* 06 05 2002 NS Draft */ 1731 /* */ 1732 /*****************************************************************************/ 1733 WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec, 1734 UWORD16 u2_frame_num) 1735 { 1736 UWORD32 u4_next_frm_num, u4_start_frm_num; 1737 UWORD32 u4_max_frm_num; 1738 pocstruct_t s_tmp_poc; 1739 WORD32 i4_poc; 1740 dec_slice_params_t *ps_cur_slice; 1741 1742 dec_pic_params_t *ps_pic_params; 1743 WORD8 i1_gap_idx; 1744 WORD32 *i4_gaps_start_frm_num; 1745 dpb_manager_t *ps_dpb_mgr; 1746 WORD32 i4_frame_gaps; 1747 WORD8 *pi1_gaps_per_seq; 1748 WORD32 ret; 1749 1750 ps_cur_slice = ps_dec->ps_cur_slice; 1751 if(ps_cur_slice->u1_field_pic_flag) 1752 { 1753 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num) 1754 return 0; 1755 } 1756 1757 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1; 1758 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1759 1760 // check 1761 if(u4_next_frm_num >= u4_max_frm_num) 1762 { 1763 u4_next_frm_num -= u4_max_frm_num; 1764 } 1765 1766 if(u4_next_frm_num == u2_frame_num) 1767 { 1768 return (0); 1769 } 1770 1771 // check 1772 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL) 1773 && (u4_next_frm_num >= u2_frame_num)) 1774 { 1775 return (0); 1776 } 1777 u4_start_frm_num = u4_next_frm_num; 1778 1779 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1780 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1781 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1782 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1783 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0; 1784 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0; 1785 1786 ps_cur_slice = ps_dec->ps_cur_slice; 1787 ps_pic_params = ps_dec->ps_cur_pps; 1788 ps_cur_slice->u1_field_pic_flag = 0; 1789 1790 i4_frame_gaps = 0; 1791 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1792 1793 /* Find a empty slot to store gap seqn info */ 1794 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num; 1795 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++) 1796 { 1797 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx]) 1798 break; 1799 } 1800 if(MAX_FRAMES == i1_gap_idx) 1801 { 1802 UWORD32 i4_error_code; 1803 i4_error_code = ERROR_DBP_MANAGER_T; 1804 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1805 return i4_error_code; 1806 } 1807 1808 i4_poc = 0; 1809 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num; 1810 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1; 1811 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq; 1812 pi1_gaps_per_seq[i1_gap_idx] = 0; 1813 while(u4_next_frm_num != u2_frame_num) 1814 { 1815 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1816 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type) 1817 { 1818 /* allocate a picture buffer and insert it as ST node */ 1819 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num, 1820 &ps_dec->s_prev_pic_poc, 1821 &s_tmp_poc, ps_cur_slice, 1822 ps_pic_params, 1, 0, 0, 1823 &i4_poc); 1824 if(ret != OK) 1825 return ret; 1826 1827 /* Display seq no calculations */ 1828 if(i4_poc >= ps_dec->i4_max_poc) 1829 ps_dec->i4_max_poc = i4_poc; 1830 /* IDR Picture or POC wrap around */ 1831 if(i4_poc == 0) 1832 { 1833 ps_dec->i4_prev_max_display_seq = 1834 ps_dec->i4_prev_max_display_seq 1835 + ps_dec->i4_max_poc 1836 + ps_dec->u1_max_dec_frame_buffering 1837 + 1; 1838 ps_dec->i4_max_poc = 0; 1839 } 1840 1841 ps_cur_slice->u1_mmco_equalto5 = 0; 1842 ps_cur_slice->u2_frame_num = u4_next_frm_num; 1843 } 1844 1845 // check 1846 if(ps_dpb_mgr->i1_poc_buf_id_entries 1847 >= ps_dec->u1_max_dec_frame_buffering) 1848 { 1849 ret = ih264d_assign_display_seq(ps_dec); 1850 if(ret != OK) 1851 return ret; 1852 } 1853 1854 ret = ih264d_insert_pic_in_display_list( 1855 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP, 1856 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc), 1857 u4_next_frm_num); 1858 if(ret != OK) 1859 return ret; 1860 1861 pi1_gaps_per_seq[i1_gap_idx]++; 1862 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr, 1863 ps_dec->ps_cur_sps->u1_num_ref_frames); 1864 if(ret != OK) 1865 return ret; 1866 1867 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1868 1869 u4_next_frm_num++; 1870 if(u4_next_frm_num >= u4_max_frm_num) 1871 { 1872 u4_next_frm_num -= u4_max_frm_num; 1873 } 1874 1875 i4_frame_gaps++; 1876 } 1877 1878 return OK; 1879 } 1880 1881 /*! 1882 ************************************************************************** 1883 * \if Function name : ih264d_create_pic_buffers \endif 1884 * 1885 * \brief 1886 * This function creates Picture Buffers. 1887 * 1888 * \return 1889 * 0 on Success and -1 on error 1890 ************************************************************************** 1891 */ 1892 WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf, 1893 dec_struct_t *ps_dec) 1894 { 1895 struct pic_buffer_t *ps_pic_buf; 1896 UWORD8 i; 1897 UWORD32 u4_luma_size, u4_chroma_size; 1898 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag; 1899 WORD32 j; 1900 UWORD32 u4_pic_buf_mem_used, u4_ref_buf_mem_used; 1901 UWORD8 *pu1_pic_buf_mem_base, *pu1_ref_buf_mem_base; 1902 1903 u4_pic_buf_mem_used = 0; 1904 pu1_pic_buf_mem_base = ps_dec->ps_mem_tab[MEM_REC_PIC_BUF_MGR].pv_base; 1905 1906 ps_dec->pv_disp_buf_mgr = (void *)(pu1_pic_buf_mem_base 1907 + u4_pic_buf_mem_used); 1908 u4_pic_buf_mem_used += sizeof(disp_mgr_t); 1909 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr); 1910 1911 ps_dec->pv_pic_buf_mgr = 1912 (void *)(pu1_pic_buf_mem_base + u4_pic_buf_mem_used); 1913 u4_pic_buf_mem_used += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1914 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 1915 1916 ps_pic_buf = (pic_buffer_t *)(pu1_pic_buf_mem_base + u4_pic_buf_mem_used); 1917 u4_pic_buf_mem_used += sizeof(struct pic_buffer_t) 1918 * (H264_MAX_REF_PICS * 2); 1919 1920 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 1921 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 1922 1923 { 1924 if(ps_dec->u4_share_disp_buf == 1) 1925 { 1926 /* In case of buffers getting shared between application and library 1927 there is no need of reference memtabs. Instead of setting the i4_size 1928 to zero, it is reduced to a small i4_size to ensure that changes 1929 in the code are minimal */ 1930 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1931 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 1932 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 1933 { 1934 u4_luma_size = 64; 1935 } 1936 1937 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1938 1939 { 1940 u4_chroma_size = 64; 1941 } 1942 1943 } 1944 } 1945 1946 pu1_ref_buf_mem_base = ps_dec->ps_mem_tab[MEM_REC_REF_PIC].pv_base; 1947 u4_ref_buf_mem_used = 0; 1948 1949 /* Allocate memory for refernce buffers */ 1950 for(i = 0; i < u1_num_of_buf; i++) 1951 { 1952 UWORD32 u4_offset; 1953 WORD32 buf_ret; 1954 UWORD8 *pu1_luma, *pu1_chroma; 1955 1956 pu1_luma = pu1_ref_buf_mem_base + u4_ref_buf_mem_used; 1957 u4_ref_buf_mem_used += u4_luma_size; 1958 pu1_chroma = pu1_ref_buf_mem_base + u4_ref_buf_mem_used; 1959 u4_ref_buf_mem_used += u4_chroma_size; 1960 1961 /* Offset to the start of the pic from the top left corner of the frame 1962 buffer */ 1963 1964 if((0 == ps_dec->u4_share_disp_buf) 1965 || (NULL == ps_dec->disp_bufs[i].buf[0])) 1966 { 1967 UWORD32 pad_len_h, pad_len_v; 1968 1969 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1970 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset; 1971 1972 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1)); 1973 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1974 1975 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1976 1977 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1978 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1979 1980 } 1981 else 1982 { 1983 UWORD32 pad_len_h, pad_len_v; 1984 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1985 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0] 1986 + u4_offset; 1987 1988 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset; 1989 1990 if(ps_dec->u1_chroma_format == IV_YUV_420P) 1991 { 1992 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1993 (PAD_LEN_Y_H >> 1)); 1994 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1995 1996 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1997 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1998 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1999 2000 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 2001 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 2002 2003 } 2004 else 2005 { 2006 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 2007 (PAD_LEN_Y_H >> 1)); 2008 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 2009 2010 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 2011 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 2012 + u4_offset; 2013 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 2014 + u4_offset; 2015 2016 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 2017 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 2018 2019 } 2020 2021 } 2022 2023 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y; 2024 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv; 2025 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y; 2026 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv; 2027 2028 ps_pic_buf->u1_pic_buf_id = i; 2029 2030 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 2031 ps_pic_buf, i); 2032 if(0 != buf_ret) 2033 { 2034 ps_dec->i4_error_code = ERROR_BUF_MGR; 2035 return ERROR_BUF_MGR; 2036 } 2037 2038 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf; 2039 ps_pic_buf++; 2040 } 2041 2042 if((u4_ref_buf_mem_used > ps_dec->ps_mem_tab[MEM_REC_REF_PIC].u4_mem_size) || 2043 (u4_pic_buf_mem_used > ps_dec->ps_mem_tab[MEM_REC_PIC_BUF_MGR].u4_mem_size)) 2044 { 2045 ps_dec->i4_error_code = ERROR_BUF_MGR; 2046 return ERROR_BUF_MGR; 2047 } 2048 2049 if(1 == ps_dec->u4_share_disp_buf) 2050 { 2051 for(i = 0; i < u1_num_of_buf; i++) 2052 ps_dec->u4_disp_buf_mapping[i] = 1; 2053 } 2054 return OK; 2055 } 2056 2057 /*! 2058 ************************************************************************** 2059 * \if Function name : ih264d_get_memory_dec_params \endif 2060 * 2061 * \brief 2062 * This function allocates memory required by Decoder. 2063 * 2064 * \param ps_dec: Pointer to dec_struct_t. 2065 * 2066 * \return 2067 * Returns i4_status as returned by MemManager. 2068 * 2069 ************************************************************************** 2070 */ 2071 WORD16 ih264d_get_memory_dec_params(dec_struct_t * ps_dec) 2072 { 2073 struct MemReq s_MemReq; 2074 struct MemBlock *p_MemBlock; 2075 2076 pred_info_t *ps_pred_frame; 2077 dec_mb_info_t *ps_frm_mb_info; 2078 dec_slice_struct_t *ps_dec_slice_buf; 2079 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map; 2080 UWORD16 *pu2_slice_num_map; 2081 2082 WORD16 *pi16_res_coeff; 2083 WORD16 i16_status = 0; 2084 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag); 2085 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y; 2086 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv; 2087 WORD8 c_i = 0; 2088 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps; 2089 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld; 2090 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs; 2091 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs; 2092 UWORD32 u4_blk_wd; 2093 UWORD32 ui_size = 0; 2094 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0; 2095 UWORD8 *pu1_buf; 2096 2097 ps_dec->ps_deblk_pic = ps_dec->ps_mem_tab[MEM_REC_DEBLK_MB_INFO].pv_base; 2098 memset(ps_dec->ps_deblk_pic, 0, ps_dec->ps_mem_tab[MEM_REC_DEBLK_MB_INFO].u4_mem_size); 2099 2100 ps_dec->pu1_dec_mb_map = ps_dec->ps_mem_tab[MEM_REC_PARSE_MAP].pv_base; 2101 2102 ps_dec->pu1_recon_mb_map = ps_dec->ps_mem_tab[MEM_REC_PROC_MAP].pv_base; 2103 2104 ps_dec->pu2_slice_num_map = 2105 ps_dec->ps_mem_tab[MEM_REC_SLICE_NUM_MAP].pv_base; 2106 2107 ps_dec->ps_dec_slice_buf = ps_dec->ps_mem_tab[MEM_REC_SLICE_HDR].pv_base; 2108 memset(ps_dec->ps_mem_tab[MEM_REC_SLICE_HDR].pv_base, 0, 2109 ps_dec->ps_mem_tab[MEM_REC_SLICE_HDR].u4_mem_size); 2110 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf; 2111 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs; 2112 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf; 2113 2114 ps_dec->ps_frm_mb_info = ps_dec->ps_mem_tab[MEM_REC_MB_INFO].pv_base; 2115 memset(ps_dec->ps_frm_mb_info, 0, ps_dec->ps_mem_tab[MEM_REC_MB_INFO].u4_mem_size); 2116 2117 ps_dec->ps_pred = ps_dec->ps_mem_tab[MEM_REC_PRED_INFO].pv_base; 2118 2119 ps_dec->pi2_coeff_data = ps_dec->ps_mem_tab[MEM_REC_COEFF_DATA].pv_base; 2120 2121 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE); 2122 2123 /*scratch memory allocations*/ 2124 { 2125 UWORD8 *pu1_scratch_mem_base; 2126 UWORD32 u4_scratch_mem_used; 2127 2128 pu1_scratch_mem_base = 2129 ps_dec->ps_mem_tab[MEM_REC_INTERNAL_SCRATCH].pv_base; 2130 u4_scratch_mem_used = 0; 2131 2132 ps_dec->ppv_map_ref_idx_to_poc = (void *)(pu1_scratch_mem_base 2133 + u4_scratch_mem_used); 2134 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2135 u4_scratch_mem_used += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) 2136 * sizeof(void *)); 2137 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2138 memset(ps_dec->ppv_map_ref_idx_to_poc, 0, (TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) 2139 * sizeof(void *)); 2140 2141 ps_dec->p_cabac_ctxt_table_t = (void *)(pu1_scratch_mem_base 2142 + u4_scratch_mem_used); 2143 u4_scratch_mem_used += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 2144 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2145 2146 ps_dec->ps_left_mb_ctxt_info = (void *)(pu1_scratch_mem_base 2147 + u4_scratch_mem_used); 2148 u4_scratch_mem_used += sizeof(ctxt_inc_mb_info_t); 2149 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2150 2151 ps_dec->pu4_defI_wts_ofsts = (void *)(pu1_scratch_mem_base 2152 + u4_scratch_mem_used); 2153 u4_scratch_mem_used += 2154 sizeof(UWORD32) 2155 * (ps_sps->u1_num_ref_frames 2156 * ps_sps->u1_num_ref_frames); 2157 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2158 2159 ps_dec->pu1_ref_buff = pu1_scratch_mem_base + u4_scratch_mem_used + MAX_REF_BUF_SIZE; 2160 u4_scratch_mem_used += MAX_REF_BUF_SIZE * 2; 2161 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2162 ps_dec->pi2_pred1 = 2163 (void *)(pu1_scratch_mem_base + u4_scratch_mem_used); 2164 u4_scratch_mem_used += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 2165 * PRED_BUFFER_HEIGHT * 2); 2166 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2167 2168 ps_dec->pu1_temp_mc_buffer = (void *)(pu1_scratch_mem_base 2169 + u4_scratch_mem_used); 2170 u4_scratch_mem_used += sizeof(UWORD8) * (MB_LUM_SIZE); 2171 2172 ps_dec->ps_parse_mb_data = (void *)(pu1_scratch_mem_base 2173 + u4_scratch_mem_used); 2174 u4_scratch_mem_used += sizeof(parse_pmbarams_t) 2175 * (ps_dec->u1_recon_mb_grp); 2176 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2177 2178 ps_dec->ps_parse_part_params = (void *)(pu1_scratch_mem_base 2179 + u4_scratch_mem_used); 2180 u4_scratch_mem_used += sizeof(parse_part_params_t) 2181 * ((ps_dec->u1_recon_mb_grp) << 4); 2182 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2183 2184 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = 2185 (struct pic_buffer_t*)(pu1_scratch_mem_base 2186 + u4_scratch_mem_used); 2187 u4_scratch_mem_used += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2188 2189 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2190 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = 2191 (struct pic_buffer_t*)(pu1_scratch_mem_base + u4_scratch_mem_used); 2192 u4_scratch_mem_used += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 2193 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2194 ps_dec->pu4_mbaff_wt_mat = (UWORD32 *)(pu1_scratch_mem_base + u4_scratch_mem_used); 2195 2196 u4_scratch_mem_used += (sizeof(UWORD32) * 3 2197 * (MAX_FRAMES * MAX_FRAMES)) 2198 << 3; 2199 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2200 2201 ps_dec->pu4_wts_ofsts_mat = (UWORD32 *)(pu1_scratch_mem_base + u4_scratch_mem_used); 2202 u4_scratch_mem_used += sizeof(UWORD32) * 2 * 3 2203 * (MAX_FRAMES * MAX_FRAMES); 2204 u4_scratch_mem_used = ALIGN64(u4_scratch_mem_used); 2205 } 2206 /********************************************************************/ 2207 /* check whether deblk memory used is less than the scratch buffer */ 2208 /* and assign deblocking pointers in the the reference buffers */ 2209 /********************************************************************/ 2210 { 2211 /************************************************************/ 2212 /* Post allocation Initialisations */ 2213 /************************************************************/ 2214 memset(ps_dec->ppv_map_ref_idx_to_poc, 0, 2215 (TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *)); 2216 ps_dec->ppv_map_ref_idx_to_poc += OFFSET_MAP_IDX_POC; 2217 2218 { 2219 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 2220 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 2221 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 2222 2223 ps_dec->ps_pred_start = ps_dec->ps_pred; 2224 ps_dec->u4_ref_buf_size = MAX_REF_BUF_SIZE; 2225 } 2226 2227 { 2228 UWORD8 i; 2229 struct pic_buffer_t *ps_init_dpb; 2230 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0]; 2231 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 2232 { 2233 ps_init_dpb->pu1_buf1 = NULL; 2234 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 2235 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb; 2236 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb; 2237 ps_init_dpb++; 2238 } 2239 2240 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0]; 2241 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 2242 { 2243 ps_init_dpb->pu1_buf1 = NULL; 2244 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 2245 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb; 2246 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb; 2247 ps_init_dpb++; 2248 } 2249 } 2250 } 2251 2252 /*persistent memory allocations*/ 2253 2254 { 2255 UWORD8 *pu1_persitent_mem_base; 2256 UWORD32 u4_persistent_mem_used; 2257 2258 pu1_persitent_mem_base = 2259 ps_dec->ps_mem_tab[MEM_REC_INTERNAL_PERSIST].pv_base; 2260 u4_persistent_mem_used = 0; 2261 2262 ps_dec->ps_deblk_top_mb = (void *)(pu1_persitent_mem_base 2263 + u4_persistent_mem_used); 2264 u4_persistent_mem_used += ((u4_wd_mbs 2265 * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld); 2266 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2267 2268 ps_dec->ps_left_mvpred_addr = (void *)(pu1_persitent_mem_base 2269 + u4_persistent_mem_used); 2270 u4_persistent_mem_used += (sizeof(neighbouradd_t) << 2); 2271 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2272 2273 ps_dec->p_ctxt_inc_mb_map = (void *)(pu1_persitent_mem_base 2274 + u4_persistent_mem_used); 2275 u4_persistent_mem_used += ((sizeof(ctxt_inc_mb_info_t)) 2276 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1)); 2277 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2278 2279 ps_dec->ps_mv_p[0] = (void *)(pu1_persitent_mem_base 2280 + u4_persistent_mem_used); 2281 u4_persistent_mem_used += (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 2282 * 16); 2283 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2284 2285 ps_dec->ps_mv_p[1] = (void *)(pu1_persitent_mem_base 2286 + u4_persistent_mem_used); 2287 u4_persistent_mem_used += (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 2288 * 16); 2289 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2290 2291 { 2292 UWORD8 i; 2293 for(i = 0; i < MV_SCRATCH_BUFS; i++) 2294 { 2295 2296 ps_dec->ps_mv_top_p[i] = (void *)(pu1_persitent_mem_base 2297 + u4_persistent_mem_used); 2298 u4_persistent_mem_used += (sizeof(mv_pred_t) 2299 * ps_dec->u1_recon_mb_grp * 4); 2300 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2301 2302 } 2303 } 2304 2305 { 2306 UWORD32 u4_numRows = MB_SIZE << 1; 2307 2308 /* Allocate memory for ping, pong and left reconstruction buffers */ 2309 u4_blk_wd = ((ps_dec->u1_recon_mb_grp << 4) >> 1) + 8; 2310 2311 ps_dec->pu1_y_scratch[0] = (void *)(pu1_persitent_mem_base 2312 + u4_persistent_mem_used); 2313 u4_persistent_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2314 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2315 2316 ps_dec->pu1_y_scratch[1] = (void *)(pu1_persitent_mem_base 2317 + u4_persistent_mem_used); 2318 u4_persistent_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2319 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2320 2321 u4_numRows = BLK8x8SIZE << 1; 2322 u4_blk_wd = ((ps_dec->u1_recon_mb_grp << 3) >> 1) + 8; 2323 2324 ps_dec->pu1_u_scratch[0] = (void *)(pu1_persitent_mem_base 2325 + u4_persistent_mem_used); 2326 u4_persistent_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2327 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2328 2329 ps_dec->pu1_v_scratch[0] = (void *)(pu1_persitent_mem_base 2330 + u4_persistent_mem_used); 2331 u4_persistent_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2332 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2333 2334 ps_dec->pu1_u_scratch[1] = (void *)(pu1_persitent_mem_base 2335 + u4_persistent_mem_used); 2336 u4_persistent_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2337 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2338 2339 ps_dec->pu1_v_scratch[1] = (void *)(pu1_persitent_mem_base 2340 + u4_persistent_mem_used); 2341 u4_persistent_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd; 2342 u4_persistent_mem_used += 32; 2343 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2344 2345 } 2346 2347 ps_dec->pu1_y_intra_pred_line = (void *)(pu1_persitent_mem_base 2348 + u4_persistent_mem_used); 2349 u4_persistent_mem_used += sizeof(UWORD8) * ((u4_wd_mbs + 1) * MB_SIZE) * 2; 2350 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2351 2352 ps_dec->pu1_u_intra_pred_line = (void *)(pu1_persitent_mem_base 2353 + u4_persistent_mem_used); 2354 u4_persistent_mem_used += sizeof(UWORD8) * ((u4_wd_mbs + 1) * MB_SIZE) * 2; 2355 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2356 2357 ps_dec->pu1_v_intra_pred_line = (void *)(pu1_persitent_mem_base 2358 + u4_persistent_mem_used); 2359 u4_persistent_mem_used += sizeof(UWORD8) * ((u4_wd_mbs + 1) * MB_SIZE) * 2; 2360 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2361 2362 ps_dec->ps_nbr_mb_row = (void *)(pu1_persitent_mem_base 2363 + u4_persistent_mem_used); 2364 if(ps_dec->u1_separate_parse) 2365 { 2366 u4_persistent_mem_used += sizeof(mb_neigbour_params_t) 2367 * ((u4_wd_mbs + 1) * u4_ht_mbs); 2368 memset(ps_dec->ps_nbr_mb_row, 0, sizeof(mb_neigbour_params_t) 2369 * ((u4_wd_mbs + 1) * u4_ht_mbs)); 2370 } 2371 else 2372 { 2373 u4_persistent_mem_used += sizeof(mb_neigbour_params_t) 2374 * ((u4_wd_mbs + 1) << uc_frmOrFld); 2375 memset(ps_dec->ps_nbr_mb_row, 0, sizeof(mb_neigbour_params_t) 2376 * ((u4_wd_mbs + 1) << uc_frmOrFld)); 2377 2378 } 2379 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2380 ps_dec->s_pad_mgr.pu1_row_y = (void *)(pu1_persitent_mem_base 2381 + u4_persistent_mem_used); 2382 u4_persistent_mem_used += ps_dec->u2_frm_wd_y; 2383 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2384 2385 ps_dec->s_pad_mgr.pu1_row_u = (void *)(pu1_persitent_mem_base 2386 + u4_persistent_mem_used); 2387 u4_persistent_mem_used += ps_dec->u2_frm_wd_uv; 2388 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2389 2390 ps_dec->s_pad_mgr.pu1_row_v = (void *)(pu1_persitent_mem_base 2391 + u4_persistent_mem_used); 2392 u4_persistent_mem_used += ps_dec->u2_frm_wd_uv; 2393 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2394 2395 ps_dec->s_pad_mgr.pu1_mb_y = (void *)(pu1_persitent_mem_base 2396 + u4_persistent_mem_used); 2397 u4_persistent_mem_used += ((MB_SIZE + 4) << uc_frmOrFld) * PAD_LEN_Y_H; 2398 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2399 2400 ps_dec->s_pad_mgr.pu1_mb_u = (void *)(pu1_persitent_mem_base 2401 + u4_persistent_mem_used); 2402 u4_persistent_mem_used += ((BLK8x8SIZE + 2) << uc_frmOrFld) 2403 * PAD_LEN_UV_H; 2404 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2405 2406 ps_dec->s_pad_mgr.pu1_mb_v = (void *)(pu1_persitent_mem_base 2407 + u4_persistent_mem_used); 2408 u4_persistent_mem_used += ((BLK8x8SIZE + 2) << uc_frmOrFld) 2409 * PAD_LEN_UV_H; 2410 u4_persistent_mem_used = ALIGN64(u4_persistent_mem_used); 2411 } 2412 2413 /*Post allocation initializations*/ 2414 memset(ps_dec->pu1_y_intra_pred_line, 0, 2415 sizeof(UWORD8) * u4_luma_wd + PAD_LEN_Y_H); 2416 memset(ps_dec->pu1_u_intra_pred_line, 0, 2417 sizeof(UWORD8) * u4_chroma_wd + PAD_LEN_UV_H); 2418 memset(ps_dec->pu1_v_intra_pred_line, 0, 2419 sizeof(UWORD8) * u4_chroma_wd + PAD_LEN_UV_H); 2420 2421 /* 0th entry of CtxtIncMbMap will be always be containing default values 2422 for CABAC context representing MB not available */ 2423 ps_dec->p_ctxt_inc_mb_map += 1; 2424 /* Post allocation Increment Actions */ 2425 2426 /***************************************************************************/ 2427 /*Initialize cabac context pointers for every SE that has fixed contextIdx */ 2428 /***************************************************************************/ 2429 { 2430 bin_ctxt_model_t * const p_cabac_ctxt_table_t = 2431 ps_dec->p_cabac_ctxt_table_t; 2432 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t = 2433 ps_dec->p_coeff_abs_level_minus1_t; 2434 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t; 2435 2436 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t 2437 + MB_FIELD_DECODING_FLAG; 2438 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t 2439 + PREV_INTRA4X4_PRED_MODE_FLAG; 2440 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t 2441 + REM_INTRA4X4_PRED_MODE; 2442 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t 2443 + INTRA_CHROMA_PRED_MODE; 2444 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA; 2445 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX; 2446 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X; 2447 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y; 2448 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0; 2449 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4; 2450 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8; 2451 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12; 2452 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16; 2453 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA; 2454 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA; 2455 2456 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2457 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET; 2458 2459 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2460 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET; 2461 2462 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t 2463 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET; 2464 2465 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2466 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET; 2467 2468 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2469 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET; 2470 2471 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t 2472 + COEFF_ABS_LEVEL_MINUS1_8X8 2473 + COEFF_ABS_LEVEL_CAT_5_OFFSET; 2474 2475 /********************************************************/ 2476 /* context for the high profile related syntax elements */ 2477 /* This is maintained seperately in s_high_profile */ 2478 /********************************************************/ 2479 { 2480 2481 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t 2482 + TRANSFORM_SIZE_8X8_FLAG; 2483 2484 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t 2485 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2486 2487 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame = 2488 p_cabac_ctxt_table_t 2489 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2490 2491 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 = 2492 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8; 2493 2494 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t 2495 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2496 2497 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field = 2498 p_cabac_ctxt_table_t 2499 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2500 2501 } 2502 2503 } 2504 return (i16_status); 2505 } 2506 2507 /*! 2508 ************************************************************************** 2509 * \if Function name : ih264d_create_mv_bank \endif 2510 * 2511 * \brief 2512 * This function creates MV bank. 2513 * 2514 * \param memType : Type of memory being handled 2515 * 0: Display Buffer 2516 * 1: Decoder Buffer 2517 * 2: Internal Buffer 2518 * \param u1_num_of_buf: Number of decode or display buffers. 2519 * \param u4_wd : Frame width. 2520 * \param u4_ht : Frame Height. 2521 * \param ps_pic_buf_api : Pointer to Picture Buffer API. 2522 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system. 2523 * 2524 * \return 2525 * 0 on Success and -1 on error 2526 * 2527 ************************************************************************** 2528 */ 2529 WORD32 ih264d_create_mv_bank(void *pv_dec, 2530 UWORD32 ui_width, 2531 UWORD32 ui_height) 2532 { 2533 UWORD8 i; 2534 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2535 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base; 2536 UWORD32 u4_mv_buf_mgr_mem_used, u4_mv_bank_mem_used; 2537 col_mv_buf_t *ps_col_mv; 2538 mv_pred_t *ps_mv; 2539 UWORD8 *pu1_col_zero_flag_buf; 2540 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec; 2541 WORD32 buf_ret; 2542 UWORD32 u4_num_bufs; 2543 2544 pu1_mv_buf_mgr_base = ps_dec->ps_mem_tab[MEM_REC_MV_BUF_MGR].pv_base; 2545 u4_mv_buf_mgr_mem_used = 0; 2546 col_flag_buffer_size = ((ui_width * ui_height) >> 4); 2547 2548 pu1_mv_bank_base = ps_dec->ps_mem_tab[MEM_REC_MVBANK].pv_base; 2549 u4_mv_bank_mem_used = 0; 2550 mvpred_buffer_size = sizeof(mv_pred_t) 2551 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4); 2552 2553 ps_dec->pv_mv_buf_mgr = (void *)(pu1_mv_buf_mgr_base + u4_mv_buf_mgr_mem_used); 2554 u4_mv_buf_mgr_mem_used += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 2555 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2556 2557 ps_col_mv = (col_mv_buf_t *)(pu1_mv_buf_mgr_base + u4_mv_buf_mgr_mem_used); 2558 u4_mv_buf_mgr_mem_used += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 2559 u4_mv_buf_mgr_mem_used = ALIGN128(u4_mv_buf_mgr_mem_used); 2560 2561 u4_num_bufs = ih264d_get_numbuf_mv_bank(ps_dec, ui_width, ui_height); 2562 2563 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2564 2565 for(i = 0 ; i < u4_num_bufs ; i++) 2566 { 2567 pu1_col_zero_flag_buf = pu1_mv_buf_mgr_base + u4_mv_buf_mgr_mem_used; 2568 u4_mv_buf_mgr_mem_used += col_flag_buffer_size; 2569 2570 ps_mv = (mv_pred_t *)(pu1_mv_bank_base + u4_mv_bank_mem_used); 2571 u4_mv_bank_mem_used += mvpred_buffer_size; 2572 2573 memset(ps_mv, 0, ((ui_width*OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t)); 2574 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4; 2575 2576 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf; 2577 ps_col_mv->pv_mv = (void *)ps_mv; 2578 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i); 2579 if(0 != buf_ret) 2580 { 2581 ps_dec->i4_error_code = ERROR_BUF_MGR; 2582 return ERROR_BUF_MGR; 2583 } 2584 ps_col_mv++; 2585 } 2586 2587 if((u4_mv_buf_mgr_mem_used > ps_dec->ps_mem_tab[MEM_REC_MV_BUF_MGR].u4_mem_size) || 2588 (u4_mv_bank_mem_used > ps_dec->ps_mem_tab[MEM_REC_MVBANK].u4_mem_size)) 2589 { 2590 ps_dec->i4_error_code = ERROR_BUF_MGR; 2591 return ERROR_BUF_MGR; 2592 } 2593 2594 return OK; 2595 2596 } 2597 2598 2599 void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4, 2600 WORD16 *pi2_out_coeff_data, 2601 UWORD8 *pu1_inv_scan) 2602 { 2603 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map; 2604 WORD32 idx; 2605 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0]; 2606 2607 while(u2_sig_coeff_map) 2608 { 2609 idx = CLZ(u2_sig_coeff_map); 2610 2611 idx = 31 - idx; 2612 RESET_BIT(u2_sig_coeff_map,idx); 2613 2614 idx = pu1_inv_scan[idx]; 2615 pi2_out_coeff_data[idx] = *pi2_coeff_data++; 2616 2617 } 2618 } 2619
