1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 16 17 18 #include "ARMFrameLowering.h" 19 #include "ARMISelLowering.h" 20 #include "ARMInstrInfo.h" 21 #include "ARMSelectionDAGInfo.h" 22 #include "ARMSubtarget.h" 23 #include "MCTargetDesc/ARMMCTargetDesc.h" 24 #include "Thumb1FrameLowering.h" 25 #include "Thumb1InstrInfo.h" 26 #include "Thumb2InstrInfo.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/DataLayout.h" 29 #include "llvm/MC/MCInstrItineraries.h" 30 #include "llvm/Target/TargetSubtargetInfo.h" 31 #include <string> 32 33 #define GET_SUBTARGETINFO_HEADER 34 #include "ARMGenSubtargetInfo.inc" 35 36 namespace llvm { 37 class GlobalValue; 38 class StringRef; 39 class TargetOptions; 40 class ARMBaseTargetMachine; 41 42 class ARMSubtarget : public ARMGenSubtargetInfo { 43 protected: 44 enum ARMProcFamilyEnum { 45 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, 46 CortexA17, CortexR4, CortexR4F, CortexR5, Swift, CortexA53, CortexA57, Krait, 47 }; 48 enum ARMProcClassEnum { 49 None, AClass, RClass, MClass 50 }; 51 52 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 53 ARMProcFamilyEnum ARMProcFamily; 54 55 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. 56 ARMProcClassEnum ARMProcClass; 57 58 /// HasV4TOps, HasV5TOps, HasV5TEOps, 59 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - 60 /// Specify whether target support specific ARM ISA variants. 61 bool HasV4TOps; 62 bool HasV5TOps; 63 bool HasV5TEOps; 64 bool HasV6Ops; 65 bool HasV6MOps; 66 bool HasV6KOps; 67 bool HasV6T2Ops; 68 bool HasV7Ops; 69 bool HasV8Ops; 70 bool HasV8_1aOps; 71 72 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what 73 /// floating point ISAs are supported. 74 bool HasVFPv2; 75 bool HasVFPv3; 76 bool HasVFPv4; 77 bool HasFPARMv8; 78 bool HasNEON; 79 80 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 81 /// specified. Use the method useNEONForSinglePrecisionFP() to 82 /// determine if NEON should actually be used. 83 bool UseNEONForSinglePrecisionFP; 84 85 /// UseMulOps - True if non-microcoded fused integer multiply-add and 86 /// multiply-subtract instructions should be used. 87 bool UseMulOps; 88 89 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 90 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 91 bool SlowFPVMLx; 92 93 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 94 /// forwarding to allow mul + mla being issued back to back. 95 bool HasVMLxForwarding; 96 97 /// SlowFPBrcc - True if floating point compare + branch is slow. 98 bool SlowFPBrcc; 99 100 /// InThumbMode - True if compiling for Thumb, false for ARM. 101 bool InThumbMode; 102 103 /// HasThumb2 - True if Thumb2 instructions are supported. 104 bool HasThumb2; 105 106 /// NoARM - True if subtarget does not support ARM mode execution. 107 bool NoARM; 108 109 /// IsR9Reserved - True if R9 is a not available as general purpose register. 110 bool IsR9Reserved; 111 112 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 113 /// imms (including global addresses). 114 bool UseMovt; 115 116 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 117 /// must be able to synthesize call stubs for interworking between ARM and 118 /// Thumb. 119 bool SupportsTailCall; 120 121 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 122 /// only so far) 123 bool HasFP16; 124 125 /// HasD16 - True if subtarget is limited to 16 double precision 126 /// FP registers for VFPv3. 127 bool HasD16; 128 129 /// HasHardwareDivide - True if subtarget supports [su]div 130 bool HasHardwareDivide; 131 132 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode 133 bool HasHardwareDivideInARM; 134 135 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 136 /// instructions. 137 bool HasT2ExtractPack; 138 139 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 140 /// instructions. 141 bool HasDataBarrier; 142 143 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 144 /// over 16-bit ones. 145 bool Pref32BitThumb; 146 147 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 148 /// that partially update CPSR and add false dependency on the previous 149 /// CPSR setting instruction. 150 bool AvoidCPSRPartialUpdate; 151 152 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting 153 /// movs with shifter operand (i.e. asr, lsl, lsr). 154 bool AvoidMOVsShifterOperand; 155 156 /// HasRAS - Some processors perform return stack prediction. CodeGen should 157 /// avoid issue "normal" call instructions to callees which do not return. 158 bool HasRAS; 159 160 /// HasMPExtension - True if the subtarget supports Multiprocessing 161 /// extension (ARMv7 only). 162 bool HasMPExtension; 163 164 /// HasVirtualization - True if the subtarget supports the Virtualization 165 /// extension. 166 bool HasVirtualization; 167 168 /// FPOnlySP - If true, the floating point unit only supports single 169 /// precision. 170 bool FPOnlySP; 171 172 /// If true, the processor supports the Performance Monitor Extensions. These 173 /// include a generic cycle-counter as well as more fine-grained (often 174 /// implementation-specific) events. 175 bool HasPerfMon; 176 177 /// HasTrustZone - if true, processor supports TrustZone security extensions 178 bool HasTrustZone; 179 180 /// HasCrypto - if true, processor supports Cryptography extensions 181 bool HasCrypto; 182 183 /// HasCRC - if true, processor supports CRC instructions 184 bool HasCRC; 185 186 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are 187 /// particularly effective at zeroing a VFP register. 188 bool HasZeroCycleZeroing; 189 190 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory 191 /// accesses for some types. For details, see 192 /// ARMTargetLowering::allowsMisalignedMemoryAccesses(). 193 bool AllowsUnalignedMem; 194 195 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT 196 /// blocks to conform to ARMv8 rule. 197 bool RestrictIT; 198 199 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith 200 /// and such) instructions in Thumb2 code. 201 bool Thumb2DSP; 202 203 /// NaCl TRAP instruction is generated instead of the regular TRAP. 204 bool UseNaClTrap; 205 206 /// Force long to be a 64-bit type (RenderScript-specific) 207 bool UseLong64; 208 209 /// Target machine allowed unsafe FP math (such as use of NEON fp) 210 bool UnsafeFPMath; 211 212 /// stackAlignment - The minimum alignment known to hold of the stack frame on 213 /// entry to the function and which must be maintained by every function. 214 unsigned stackAlignment; 215 216 /// CPUString - String name of used CPU. 217 std::string CPUString; 218 219 /// IsLittle - The target is Little Endian 220 bool IsLittle; 221 222 /// TargetTriple - What processor and OS we're targeting. 223 Triple TargetTriple; 224 225 /// SchedModel - Processor specific instruction costs. 226 MCSchedModel SchedModel; 227 228 /// Selected instruction itineraries (one entry per itinerary class.) 229 InstrItineraryData InstrItins; 230 231 /// Options passed via command line that could influence the target 232 const TargetOptions &Options; 233 234 const ARMBaseTargetMachine &TM; 235 236 public: 237 /// This constructor initializes the data members to match that 238 /// of the specified triple. 239 /// 240 ARMSubtarget(const std::string &TT, const std::string &CPU, 241 const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle); 242 243 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 244 /// that still makes it profitable to inline the call. 245 unsigned getMaxInlineSizeThreshold() const { 246 return 64; 247 } 248 /// ParseSubtargetFeatures - Parses features string setting specified 249 /// subtarget options. Definition of function is auto generated by tblgen. 250 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 251 252 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 253 /// so that we can use initializer lists for subtarget initialization. 254 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 255 256 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { 257 return &TSInfo; 258 } 259 const ARMBaseInstrInfo *getInstrInfo() const override { 260 return InstrInfo.get(); 261 } 262 const ARMTargetLowering *getTargetLowering() const override { 263 return &TLInfo; 264 } 265 const ARMFrameLowering *getFrameLowering() const override { 266 return FrameLowering.get(); 267 } 268 const ARMBaseRegisterInfo *getRegisterInfo() const override { 269 return &InstrInfo->getRegisterInfo(); 270 } 271 272 private: 273 ARMSelectionDAGInfo TSInfo; 274 // Either Thumb1FrameLowering or ARMFrameLowering. 275 std::unique_ptr<ARMFrameLowering> FrameLowering; 276 // Either Thumb1InstrInfo or Thumb2InstrInfo. 277 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; 278 ARMTargetLowering TLInfo; 279 280 void initializeEnvironment(); 281 void initSubtargetFeatures(StringRef CPU, StringRef FS); 282 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); 283 284 public: 285 void computeIssueWidth(); 286 287 bool hasV4TOps() const { return HasV4TOps; } 288 bool hasV5TOps() const { return HasV5TOps; } 289 bool hasV5TEOps() const { return HasV5TEOps; } 290 bool hasV6Ops() const { return HasV6Ops; } 291 bool hasV6MOps() const { return HasV6MOps; } 292 bool hasV6KOps() const { return HasV6KOps; } 293 bool hasV6T2Ops() const { return HasV6T2Ops; } 294 bool hasV7Ops() const { return HasV7Ops; } 295 bool hasV8Ops() const { return HasV8Ops; } 296 bool hasV8_1aOps() const { return HasV8_1aOps; } 297 298 bool isCortexA5() const { return ARMProcFamily == CortexA5; } 299 bool isCortexA7() const { return ARMProcFamily == CortexA7; } 300 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 301 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 302 bool isCortexA15() const { return ARMProcFamily == CortexA15; } 303 bool isSwift() const { return ARMProcFamily == Swift; } 304 bool isCortexM3() const { return CPUString == "cortex-m3"; } 305 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } 306 bool isCortexR5() const { return ARMProcFamily == CortexR5; } 307 bool isKrait() const { return ARMProcFamily == Krait; } 308 309 bool hasARMOps() const { return !NoARM; } 310 311 bool hasVFP2() const { return HasVFPv2; } 312 bool hasVFP3() const { return HasVFPv3; } 313 bool hasVFP4() const { return HasVFPv4; } 314 bool hasFPARMv8() const { return HasFPARMv8; } 315 bool hasNEON() const { return HasNEON; } 316 bool hasCrypto() const { return HasCrypto; } 317 bool hasCRC() const { return HasCRC; } 318 bool hasVirtualization() const { return HasVirtualization; } 319 bool useNEONForSinglePrecisionFP() const { 320 return hasNEON() && UseNEONForSinglePrecisionFP; 321 } 322 323 bool hasDivide() const { return HasHardwareDivide; } 324 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } 325 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 326 bool hasDataBarrier() const { return HasDataBarrier; } 327 bool hasAnyDataBarrier() const { 328 return HasDataBarrier || (hasV6Ops() && !isThumb()); 329 } 330 bool useMulOps() const { return UseMulOps; } 331 bool useFPVMLx() const { return !SlowFPVMLx; } 332 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 333 bool isFPBrccSlow() const { return SlowFPBrcc; } 334 bool isFPOnlySP() const { return FPOnlySP; } 335 bool hasPerfMon() const { return HasPerfMon; } 336 bool hasTrustZone() const { return HasTrustZone; } 337 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } 338 bool prefers32BitThumb() const { return Pref32BitThumb; } 339 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 340 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } 341 bool hasRAS() const { return HasRAS; } 342 bool hasMPExtension() const { return HasMPExtension; } 343 bool hasThumb2DSP() const { return Thumb2DSP; } 344 bool useNaClTrap() const { return UseNaClTrap; } 345 346 bool hasFP16() const { return HasFP16; } 347 bool hasD16() const { return HasD16; } 348 349 const Triple &getTargetTriple() const { return TargetTriple; } 350 351 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 352 bool isTargetIOS() const { return TargetTriple.isiOS(); } 353 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 354 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 355 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } 356 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 357 358 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 359 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 360 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 361 362 // ARM EABI is the bare-metal EABI described in ARM ABI documents and 363 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI. 364 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI 365 // even for GNUEABI, so we can make a distinction here and still conform to 366 // the EABI on GNU (and Android) mode. This requires change in Clang, too. 367 // FIXME: The Darwin exception is temporary, while we move users to 368 // "*-*-*-macho" triples as quickly as possible. 369 bool isTargetAEABI() const { 370 return (TargetTriple.getEnvironment() == Triple::EABI || 371 TargetTriple.getEnvironment() == Triple::EABIHF) && 372 !isTargetDarwin() && !isTargetWindows(); 373 } 374 375 // ARM Targets that support EHABI exception handling standard 376 // Darwin uses SjLj. Other targets might need more checks. 377 bool isTargetEHABICompatible() const { 378 return (TargetTriple.getEnvironment() == Triple::EABI || 379 TargetTriple.getEnvironment() == Triple::GNUEABI || 380 TargetTriple.getEnvironment() == Triple::EABIHF || 381 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 382 TargetTriple.getEnvironment() == Triple::Android) && 383 !isTargetDarwin() && !isTargetWindows(); 384 } 385 386 bool isTargetHardFloat() const { 387 // FIXME: this is invalid for WindowsCE 388 return TargetTriple.getEnvironment() == Triple::GNUEABIHF || 389 TargetTriple.getEnvironment() == Triple::EABIHF || 390 isTargetWindows(); 391 } 392 bool isTargetAndroid() const { 393 return TargetTriple.getEnvironment() == Triple::Android; 394 } 395 396 bool isAPCS_ABI() const; 397 bool isAAPCS_ABI() const; 398 399 bool isThumb() const { return InThumbMode; } 400 bool isThumb1Only() const { return InThumbMode && !HasThumb2; } 401 bool isThumb2() const { return InThumbMode && HasThumb2; } 402 bool hasThumb2() const { return HasThumb2; } 403 bool isMClass() const { return ARMProcClass == MClass; } 404 bool isRClass() const { return ARMProcClass == RClass; } 405 bool isAClass() const { return ARMProcClass == AClass; } 406 407 bool isV6M() const { 408 return isThumb1Only() && isMClass(); 409 } 410 411 bool isR9Reserved() const { return IsR9Reserved; } 412 413 bool useMovt(const MachineFunction &MF) const; 414 415 bool supportsTailCall() const { return SupportsTailCall; } 416 417 bool allowsUnalignedMem() const { return AllowsUnalignedMem; } 418 419 bool restrictIT() const { return RestrictIT; } 420 421 const std::string & getCPUString() const { return CPUString; } 422 423 bool isLittle() const { return IsLittle; } 424 425 unsigned getMispredictionPenalty() const; 426 427 /// This function returns true if the target has sincos() routine in its 428 /// compiler runtime or math libraries. 429 bool hasSinCos() const; 430 431 /// True for some subtargets at > -O0. 432 bool enablePostMachineScheduler() const override; 433 434 // enableAtomicExpand- True if we need to expand our atomics. 435 bool enableAtomicExpand() const override; 436 437 /// getInstrItins - Return the instruction itineraries based on subtarget 438 /// selection. 439 const InstrItineraryData *getInstrItineraryData() const override { 440 return &InstrItins; 441 } 442 443 /// getStackAlignment - Returns the minimum alignment known to hold of the 444 /// stack frame on entry to the function and which must be maintained by every 445 /// function for this subtarget. 446 unsigned getStackAlignment() const { return stackAlignment; } 447 448 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 449 /// symbol. 450 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 451 452 }; 453 } // End llvm namespace 454 455 #endif // ARMSUBTARGET_H 456
