1 /* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_ 18 #define ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_ 19 20 #include "dex/compiler_enums.h" 21 #include "dex/reg_location.h" 22 #include "dex/reg_storage.h" 23 24 namespace art { 25 26 /* 27 * Runtime register usage conventions. 28 * 29 * r0-r3: Argument registers in both Dalvik and C/C++ conventions. 30 * However, for Dalvik->Dalvik calls we'll pass the target's Method* 31 * pointer in r0 as a hidden arg0. Otherwise used as codegen scratch 32 * registers. 33 * r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit 34 * r4 : If ARM_R4_SUSPEND_FLAG is set then reserved as a suspend check/debugger 35 * assist flag, otherwise a callee save promotion target. 36 * r5 : Callee save (promotion target) 37 * r6 : Callee save (promotion target) 38 * r7 : Callee save (promotion target) 39 * r8 : Callee save (promotion target) 40 * r9 : (rARM_SELF) is reserved (pointer to thread-local storage) 41 * r10 : Callee save (promotion target) 42 * r11 : Callee save (promotion target) 43 * r12 : Scratch, may be trashed by linkage stubs 44 * r13 : (sp) is reserved 45 * r14 : (lr) is reserved 46 * r15 : (pc) is reserved 47 * 48 * 5 core temps that codegen can use (r0, r1, r2, r3, r12) 49 * 7 core registers that can be used for promotion 50 * 51 * Floating pointer registers 52 * s0-s31 53 * d0-d15, where d0={s0,s1}, d1={s2,s3}, ... , d15={s30,s31} 54 * 55 * s16-s31 (d8-d15) preserved across C calls 56 * s0-s15 (d0-d7) trashed across C calls 57 * 58 * s0-s15/d0-d7 used as codegen temp/scratch 59 * s16-s31/d8-d31 can be used for promotion. 60 * 61 * Calling convention 62 * o On a call to a Dalvik method, pass target's Method* in r0 63 * o r1-r3 will be used for up to the first 3 words of arguments 64 * o Arguments past the first 3 words will be placed in appropriate 65 * out slots by the caller. 66 * o If a 64-bit argument would span the register/memory argument 67 * boundary, it will instead be fully passed in the frame. 68 * o Maintain a 16-byte stack alignment 69 * 70 * Stack frame diagram (stack grows down, higher addresses at top): 71 * 72 * +------------------------+ 73 * | IN[ins-1] | {Note: resides in caller's frame} 74 * | . | 75 * | IN[0] | 76 * | caller's Method* | 77 * +========================+ {Note: start of callee's frame} 78 * | spill region | {variable sized - will include lr if non-leaf.} 79 * +------------------------+ 80 * | ...filler word... | {Note: used as 2nd word of V[locals-1] if long] 81 * +------------------------+ 82 * | V[locals-1] | 83 * | V[locals-2] | 84 * | . | 85 * | . | 86 * | V[1] | 87 * | V[0] | 88 * +------------------------+ 89 * | 0 to 3 words padding | 90 * +------------------------+ 91 * | OUT[outs-1] | 92 * | OUT[outs-2] | 93 * | . | 94 * | OUT[0] | 95 * | cur_method* | <<== sp w/ 16-byte alignment 96 * +========================+ 97 */ 98 99 // First FP callee save. 100 #define ARM_FP_CALLEE_SAVE_BASE 16 101 // Flag for using R4 to do suspend check 102 // #define ARM_R4_SUSPEND_FLAG 103 104 enum ArmResourceEncodingPos { 105 kArmGPReg0 = 0, 106 kArmRegSP = 13, 107 kArmRegLR = 14, 108 kArmRegPC = 15, 109 kArmFPReg0 = 16, 110 kArmFPReg16 = 32, 111 kArmRegEnd = 48, 112 }; 113 114 enum ArmNativeRegisterPool { // private marker to avoid generate-operator-out.py from processing. 115 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0, 116 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1, 117 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2, 118 r3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3, 119 #ifdef ARM_R4_SUSPEND_FLAG 120 rARM_SUSPEND = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4, 121 #else 122 r4 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4, 123 #endif 124 r5 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 5, 125 r6 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 6, 126 r7 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 7, 127 r8 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 8, 128 rARM_SELF = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 9, 129 r10 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 10, 130 r11 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 11, 131 r12 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 12, 132 r13sp = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 13, 133 rARM_SP = r13sp, 134 r14lr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 14, 135 rARM_LR = r14lr, 136 r15pc = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 15, 137 rARM_PC = r15pc, 138 139 fr0 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 0, 140 fr1 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 1, 141 fr2 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 2, 142 fr3 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 3, 143 fr4 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 4, 144 fr5 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 5, 145 fr6 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 6, 146 fr7 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 7, 147 fr8 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 8, 148 fr9 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 9, 149 fr10 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 10, 150 fr11 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 11, 151 fr12 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 12, 152 fr13 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 13, 153 fr14 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 14, 154 fr15 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 15, 155 fr16 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 16, 156 fr17 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 17, 157 fr18 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 18, 158 fr19 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 19, 159 fr20 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 20, 160 fr21 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 21, 161 fr22 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 22, 162 fr23 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 23, 163 fr24 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 24, 164 fr25 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 25, 165 fr26 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 26, 166 fr27 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 27, 167 fr28 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 28, 168 fr29 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 29, 169 fr30 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 30, 170 fr31 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 31, 171 172 dr0 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 0, 173 dr1 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 1, 174 dr2 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 2, 175 dr3 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 3, 176 dr4 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 4, 177 dr5 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 5, 178 dr6 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 6, 179 dr7 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 7, 180 dr8 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 8, 181 dr9 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 9, 182 dr10 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 10, 183 dr11 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 11, 184 dr12 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 12, 185 dr13 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 13, 186 dr14 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 14, 187 dr15 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 15, 188 #if 0 189 // Enable when def/use and runtime able to handle these. 190 dr16 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 16, 191 dr17 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 17, 192 dr18 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 18, 193 dr19 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 19, 194 dr20 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 20, 195 dr21 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 21, 196 dr22 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 22, 197 dr23 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 23, 198 dr24 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 24, 199 dr25 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 25, 200 dr26 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 26, 201 dr27 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 27, 202 dr28 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 28, 203 dr29 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 29, 204 dr30 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 30, 205 dr31 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 31, 206 #endif 207 }; 208 209 constexpr RegStorage rs_r0(RegStorage::kValid | r0); 210 constexpr RegStorage rs_r1(RegStorage::kValid | r1); 211 constexpr RegStorage rs_r2(RegStorage::kValid | r2); 212 constexpr RegStorage rs_r3(RegStorage::kValid | r3); 213 #ifdef ARM_R4_SUSPEND_FLAG 214 constexpr RegStorage rs_rARM_SUSPEND(RegStorage::kValid | rARM_SUSPEND); 215 #else 216 constexpr RegStorage rs_r4(RegStorage::kValid | r4); 217 #endif 218 constexpr RegStorage rs_r5(RegStorage::kValid | r5); 219 constexpr RegStorage rs_r6(RegStorage::kValid | r6); 220 constexpr RegStorage rs_r7(RegStorage::kValid | r7); 221 constexpr RegStorage rs_r8(RegStorage::kValid | r8); 222 constexpr RegStorage rs_rARM_SELF(RegStorage::kValid | rARM_SELF); 223 constexpr RegStorage rs_r10(RegStorage::kValid | r10); 224 constexpr RegStorage rs_r11(RegStorage::kValid | r11); 225 constexpr RegStorage rs_r12(RegStorage::kValid | r12); 226 constexpr RegStorage rs_r13sp(RegStorage::kValid | r13sp); 227 constexpr RegStorage rs_rARM_SP(RegStorage::kValid | rARM_SP); 228 constexpr RegStorage rs_r14lr(RegStorage::kValid | r14lr); 229 constexpr RegStorage rs_rARM_LR(RegStorage::kValid | rARM_LR); 230 constexpr RegStorage rs_r15pc(RegStorage::kValid | r15pc); 231 constexpr RegStorage rs_rARM_PC(RegStorage::kValid | rARM_PC); 232 constexpr RegStorage rs_invalid(RegStorage::kInvalid); 233 234 constexpr RegStorage rs_fr0(RegStorage::kValid | fr0); 235 constexpr RegStorage rs_fr1(RegStorage::kValid | fr1); 236 constexpr RegStorage rs_fr2(RegStorage::kValid | fr2); 237 constexpr RegStorage rs_fr3(RegStorage::kValid | fr3); 238 constexpr RegStorage rs_fr4(RegStorage::kValid | fr4); 239 constexpr RegStorage rs_fr5(RegStorage::kValid | fr5); 240 constexpr RegStorage rs_fr6(RegStorage::kValid | fr6); 241 constexpr RegStorage rs_fr7(RegStorage::kValid | fr7); 242 constexpr RegStorage rs_fr8(RegStorage::kValid | fr8); 243 constexpr RegStorage rs_fr9(RegStorage::kValid | fr9); 244 constexpr RegStorage rs_fr10(RegStorage::kValid | fr10); 245 constexpr RegStorage rs_fr11(RegStorage::kValid | fr11); 246 constexpr RegStorage rs_fr12(RegStorage::kValid | fr12); 247 constexpr RegStorage rs_fr13(RegStorage::kValid | fr13); 248 constexpr RegStorage rs_fr14(RegStorage::kValid | fr14); 249 constexpr RegStorage rs_fr15(RegStorage::kValid | fr15); 250 constexpr RegStorage rs_fr16(RegStorage::kValid | fr16); 251 constexpr RegStorage rs_fr17(RegStorage::kValid | fr17); 252 constexpr RegStorage rs_fr18(RegStorage::kValid | fr18); 253 constexpr RegStorage rs_fr19(RegStorage::kValid | fr19); 254 constexpr RegStorage rs_fr20(RegStorage::kValid | fr20); 255 constexpr RegStorage rs_fr21(RegStorage::kValid | fr21); 256 constexpr RegStorage rs_fr22(RegStorage::kValid | fr22); 257 constexpr RegStorage rs_fr23(RegStorage::kValid | fr23); 258 constexpr RegStorage rs_fr24(RegStorage::kValid | fr24); 259 constexpr RegStorage rs_fr25(RegStorage::kValid | fr25); 260 constexpr RegStorage rs_fr26(RegStorage::kValid | fr26); 261 constexpr RegStorage rs_fr27(RegStorage::kValid | fr27); 262 constexpr RegStorage rs_fr28(RegStorage::kValid | fr28); 263 constexpr RegStorage rs_fr29(RegStorage::kValid | fr29); 264 constexpr RegStorage rs_fr30(RegStorage::kValid | fr30); 265 constexpr RegStorage rs_fr31(RegStorage::kValid | fr31); 266 267 constexpr RegStorage rs_dr0(RegStorage::kValid | dr0); 268 constexpr RegStorage rs_dr1(RegStorage::kValid | dr1); 269 constexpr RegStorage rs_dr2(RegStorage::kValid | dr2); 270 constexpr RegStorage rs_dr3(RegStorage::kValid | dr3); 271 constexpr RegStorage rs_dr4(RegStorage::kValid | dr4); 272 constexpr RegStorage rs_dr5(RegStorage::kValid | dr5); 273 constexpr RegStorage rs_dr6(RegStorage::kValid | dr6); 274 constexpr RegStorage rs_dr7(RegStorage::kValid | dr7); 275 constexpr RegStorage rs_dr8(RegStorage::kValid | dr8); 276 constexpr RegStorage rs_dr9(RegStorage::kValid | dr9); 277 constexpr RegStorage rs_dr10(RegStorage::kValid | dr10); 278 constexpr RegStorage rs_dr11(RegStorage::kValid | dr11); 279 constexpr RegStorage rs_dr12(RegStorage::kValid | dr12); 280 constexpr RegStorage rs_dr13(RegStorage::kValid | dr13); 281 constexpr RegStorage rs_dr14(RegStorage::kValid | dr14); 282 constexpr RegStorage rs_dr15(RegStorage::kValid | dr15); 283 #if 0 284 constexpr RegStorage rs_dr16(RegStorage::kValid | dr16); 285 constexpr RegStorage rs_dr17(RegStorage::kValid | dr17); 286 constexpr RegStorage rs_dr18(RegStorage::kValid | dr18); 287 constexpr RegStorage rs_dr19(RegStorage::kValid | dr19); 288 constexpr RegStorage rs_dr20(RegStorage::kValid | dr20); 289 constexpr RegStorage rs_dr21(RegStorage::kValid | dr21); 290 constexpr RegStorage rs_dr22(RegStorage::kValid | dr22); 291 constexpr RegStorage rs_dr23(RegStorage::kValid | dr23); 292 constexpr RegStorage rs_dr24(RegStorage::kValid | dr24); 293 constexpr RegStorage rs_dr25(RegStorage::kValid | dr25); 294 constexpr RegStorage rs_dr26(RegStorage::kValid | dr26); 295 constexpr RegStorage rs_dr27(RegStorage::kValid | dr27); 296 constexpr RegStorage rs_dr28(RegStorage::kValid | dr28); 297 constexpr RegStorage rs_dr29(RegStorage::kValid | dr29); 298 constexpr RegStorage rs_dr30(RegStorage::kValid | dr30); 299 constexpr RegStorage rs_dr31(RegStorage::kValid | dr31); 300 #endif 301 302 // RegisterLocation templates return values (r0, r0/r1, s0, or d0). 303 // Note: The return locations are shared between quick code and quick helper. This follows quick 304 // ABI. Quick helper assembly routine needs to handle the ABI differences. 305 const RegLocation arm_loc_c_return = 306 {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; 307 const RegLocation arm_loc_c_return_wide = 308 {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 309 RegStorage::MakeRegPair(rs_r0, rs_r1), INVALID_SREG, INVALID_SREG}; 310 const RegLocation arm_loc_c_return_float = kArm32QuickCodeUseSoftFloat 311 ? arm_loc_c_return 312 : RegLocation({kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, rs_fr0, INVALID_SREG, INVALID_SREG}); 313 const RegLocation arm_loc_c_return_double = kArm32QuickCodeUseSoftFloat 314 ? arm_loc_c_return_wide 315 : RegLocation({kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, rs_dr0, INVALID_SREG, INVALID_SREG}); 316 317 enum ArmShiftEncodings { 318 kArmLsl = 0x0, 319 kArmLsr = 0x1, 320 kArmAsr = 0x2, 321 kArmRor = 0x3 322 }; 323 324 /* 325 * The following enum defines the list of supported Thumb instructions by the 326 * assembler. Their corresponding EncodingMap positions will be defined in 327 * Assemble.cc. 328 */ 329 enum ArmOpcode { 330 kArmFirst = 0, 331 kArm16BitData = kArmFirst, // DATA [0] rd[15..0]. 332 kThumbAdcRR, // adc [0100000101] rm[5..3] rd[2..0]. 333 kThumbAddRRI3, // add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0]. 334 kThumbAddRI8, // add(2) [00110] rd[10..8] imm_8[7..0]. 335 kThumbAddRRR, // add(3) [0001100] rm[8..6] rn[5..3] rd[2..0]. 336 kThumbAddRRLH, // add(4) [01000100] H12[01] rm[5..3] rd[2..0]. 337 kThumbAddRRHL, // add(4) [01001000] H12[10] rm[5..3] rd[2..0]. 338 kThumbAddRRHH, // add(4) [01001100] H12[11] rm[5..3] rd[2..0]. 339 kThumbAddPcRel, // add(5) [10100] rd[10..8] imm_8[7..0]. 340 kThumbAddSpRel, // add(6) [10101] rd[10..8] imm_8[7..0]. 341 kThumbAddSpI7, // add(7) [101100000] imm_7[6..0]. 342 kThumbAndRR, // and [0100000000] rm[5..3] rd[2..0]. 343 kThumbAsrRRI5, // asr(1) [00010] imm_5[10..6] rm[5..3] rd[2..0]. 344 kThumbAsrRR, // asr(2) [0100000100] rs[5..3] rd[2..0]. 345 kThumbBCond, // b(1) [1101] cond[11..8] offset_8[7..0]. 346 kThumbBUncond, // b(2) [11100] offset_11[10..0]. 347 kThumbBicRR, // bic [0100001110] rm[5..3] rd[2..0]. 348 kThumbBkpt, // bkpt [10111110] imm_8[7..0]. 349 kThumbBlx1, // blx(1) [111] H[10] offset_11[10..0]. 350 kThumbBlx2, // blx(1) [111] H[01] offset_11[10..0]. 351 kThumbBl1, // blx(1) [111] H[10] offset_11[10..0]. 352 kThumbBl2, // blx(1) [111] H[11] offset_11[10..0]. 353 kThumbBlxR, // blx(2) [010001111] rm[6..3] [000]. 354 kThumbBx, // bx [010001110] H2[6..6] rm[5..3] SBZ[000]. 355 kThumbCmnRR, // cmn [0100001011] rm[5..3] rd[2..0]. 356 kThumbCmpRI8, // cmp(1) [00101] rn[10..8] imm_8[7..0]. 357 kThumbCmpRR, // cmp(2) [0100001010] rm[5..3] rd[2..0]. 358 kThumbCmpLH, // cmp(3) [01000101] H12[01] rm[5..3] rd[2..0]. 359 kThumbCmpHL, // cmp(3) [01000110] H12[10] rm[5..3] rd[2..0]. 360 kThumbCmpHH, // cmp(3) [01000111] H12[11] rm[5..3] rd[2..0]. 361 kThumbEorRR, // eor [0100000001] rm[5..3] rd[2..0]. 362 kThumbLdmia, // ldmia [11001] rn[10..8] reglist [7..0]. 363 kThumbLdrRRI5, // ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0]. 364 kThumbLdrRRR, // ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0]. 365 kThumbLdrPcRel, // ldr(3) [01001] rd[10..8] imm_8[7..0]. 366 kThumbLdrSpRel, // ldr(4) [10011] rd[10..8] imm_8[7..0]. 367 kThumbLdrbRRI5, // ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0]. 368 kThumbLdrbRRR, // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0]. 369 kThumbLdrhRRI5, // ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0]. 370 kThumbLdrhRRR, // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0]. 371 kThumbLdrsbRRR, // ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0]. 372 kThumbLdrshRRR, // ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0]. 373 kThumbLslRRI5, // lsl(1) [00000] imm_5[10..6] rm[5..3] rd[2..0]. 374 kThumbLslRR, // lsl(2) [0100000010] rs[5..3] rd[2..0]. 375 kThumbLsrRRI5, // lsr(1) [00001] imm_5[10..6] rm[5..3] rd[2..0]. 376 kThumbLsrRR, // lsr(2) [0100000011] rs[5..3] rd[2..0]. 377 kThumbMovImm, // mov(1) [00100] rd[10..8] imm_8[7..0]. 378 kThumbMovRR, // mov(2) [0001110000] rn[5..3] rd[2..0]. 379 kThumbMovRR_H2H, // mov(3) [01000111] H12[11] rm[5..3] rd[2..0]. 380 kThumbMovRR_H2L, // mov(3) [01000110] H12[01] rm[5..3] rd[2..0]. 381 kThumbMovRR_L2H, // mov(3) [01000101] H12[10] rm[5..3] rd[2..0]. 382 kThumbMul, // mul [0100001101] rm[5..3] rd[2..0]. 383 kThumbMvn, // mvn [0100001111] rm[5..3] rd[2..0]. 384 kThumbNeg, // neg [0100001001] rm[5..3] rd[2..0]. 385 kThumbOrr, // orr [0100001100] rm[5..3] rd[2..0]. 386 kThumbPop, // pop [1011110] r[8..8] rl[7..0]. 387 kThumbPush, // push [1011010] r[8..8] rl[7..0]. 388 kThumbRev, // rev [1011101000] rm[5..3] rd[2..0] 389 kThumbRevsh, // revsh [1011101011] rm[5..3] rd[2..0] 390 kThumbRorRR, // ror [0100000111] rs[5..3] rd[2..0]. 391 kThumbSbc, // sbc [0100000110] rm[5..3] rd[2..0]. 392 kThumbStmia, // stmia [11000] rn[10..8] reglist [7.. 0]. 393 kThumbStrRRI5, // str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0]. 394 kThumbStrRRR, // str(2) [0101000] rm[8..6] rn[5..3] rd[2..0]. 395 kThumbStrSpRel, // str(3) [10010] rd[10..8] imm_8[7..0]. 396 kThumbStrbRRI5, // strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0]. 397 kThumbStrbRRR, // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0]. 398 kThumbStrhRRI5, // strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0]. 399 kThumbStrhRRR, // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0]. 400 kThumbSubRRI3, // sub(1) [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/ 401 kThumbSubRI8, // sub(2) [00111] rd[10..8] imm_8[7..0]. 402 kThumbSubRRR, // sub(3) [0001101] rm[8..6] rn[5..3] rd[2..0]. 403 kThumbSubSpI7, // sub(4) [101100001] imm_7[6..0]. 404 kThumbSwi, // swi [11011111] imm_8[7..0]. 405 kThumbTst, // tst [0100001000] rm[5..3] rn[2..0]. 406 kThumb2Vldrs, // vldr low sx [111011011001] rn[19..16] rd[15-12] [1010] imm_8[7..0]. 407 kThumb2Vldrd, // vldr low dx [111011011001] rn[19..16] rd[15-12] [1011] imm_8[7..0]. 408 kThumb2Vmuls, // vmul vd, vn, vm [111011100010] rn[19..16] rd[15-12] [10100000] rm[3..0]. 409 kThumb2Vmuld, // vmul vd, vn, vm [111011100010] rn[19..16] rd[15-12] [10110000] rm[3..0]. 410 kThumb2Vstrs, // vstr low sx [111011011000] rn[19..16] rd[15-12] [1010] imm_8[7..0]. 411 kThumb2Vstrd, // vstr low dx [111011011000] rn[19..16] rd[15-12] [1011] imm_8[7..0]. 412 kThumb2Vsubs, // vsub vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10100040] rm[3..0]. 413 kThumb2Vsubd, // vsub vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110040] rm[3..0]. 414 kThumb2Vadds, // vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10100000] rm[3..0]. 415 kThumb2Vaddd, // vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110000] rm[3..0]. 416 kThumb2Vdivs, // vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10100000] rm[3..0]. 417 kThumb2Vdivd, // vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10110000] rm[3..0]. 418 kThumb2VmlaF64, // vmla.F64 vd, vn, vm [111011100000] vn[19..16] vd[15..12] [10110000] vm[3..0]. 419 kThumb2VcvtIF, // vcvt.F32.S32 vd, vm [1110111010111000] vd[15..12] [10101100] vm[3..0]. 420 kThumb2VcvtFI, // vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10101100] vm[3..0]. 421 kThumb2VcvtDI, // vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10111100] vm[3..0]. 422 kThumb2VcvtFd, // vcvt.F64.F32 vd, vm [1110111010110111] vd[15..12] [10101100] vm[3..0]. 423 kThumb2VcvtDF, // vcvt.F32.F64 vd, vm [1110111010110111] vd[15..12] [10111100] vm[3..0]. 424 kThumb2VcvtF64S32, // vcvt.F64.S32 vd, vm [1110111010111000] vd[15..12] [10111100] vm[3..0]. 425 kThumb2VcvtF64U32, // vcvt.F64.U32 vd, vm [1110111010111000] vd[15..12] [10110100] vm[3..0]. 426 kThumb2Vsqrts, // vsqrt.f32 vd, vm [1110111010110001] vd[15..12] [10101100] vm[3..0]. 427 kThumb2Vsqrtd, // vsqrt.f64 vd, vm [1110111010110001] vd[15..12] [10111100] vm[3..0]. 428 kThumb2MovI8M, // mov(T2) rd, #<const> [11110] i [00001001111] imm3 rd[11..8] imm8. 429 kThumb2MovImm16, // mov(T3) rd, #<const> [11110] i [0010100] imm4 [0] imm3 rd[11..8] imm8. 430 kThumb2StrRRI12, // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0]. 431 kThumb2LdrRRI12, // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0]. 432 kThumb2StrRRI8Predec, // str(Imm,T4) rd,[rn,#-imm8] [111110000100] rn[19..16] rt[15..12] [1100] imm[7..0]. 433 kThumb2LdrRRI8Predec, // ldr(Imm,T4) rd,[rn,#-imm8] [111110000101] rn[19..16] rt[15..12] [1100] imm[7..0]. 434 kThumb2Cbnz, // cbnz rd,<label> [101110] i [1] imm5[7..3] rn[2..0]. 435 kThumb2Cbz, // cbn rd,<label> [101100] i [1] imm5[7..3] rn[2..0]. 436 kThumb2AddRRI12, // add rd, rn, #imm12 [11110] i [100000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 437 kThumb2MovRR, // mov rd, rm [11101010010011110000] rd[11..8] [0000] rm[3..0]. 438 kThumb2Vmovs, // vmov.f32 vd, vm [111011101] D [110000] vd[15..12] 101001] M [0] vm[3..0]. 439 kThumb2Vmovd, // vmov.f64 vd, vm [111011101] D [110000] vd[15..12] 101101] M [0] vm[3..0]. 440 kThumb2Ldmia, // ldmia [111010001001] rn[19..16] mask[15..0]. 441 kThumb2Stmia, // stmia [111010001000] rn[19..16] mask[15..0]. 442 kThumb2AddRRR, // add [111010110000] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 443 kThumb2SubRRR, // sub [111010111010] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 444 kThumb2SbcRRR, // sbc [111010110110] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 445 kThumb2CmpRR, // cmp [111010111011] rn[19..16] [0000] [1111] [0000] rm[3..0]. 446 kThumb2SubRRI12, // sub rd, rn, #imm12 [11110] i [101010] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 447 kThumb2MvnI8M, // mov(T2) rd, #<const> [11110] i [00011011110] imm3 rd[11..8] imm8. 448 kThumb2Sel, // sel rd, rn, rm [111110101010] rn[19-16] rd[11-8] rm[3-0]. 449 kThumb2Ubfx, // ubfx rd,rn,#lsb,#width [111100111100] rn[19..16] [0] imm3[14-12] rd[11-8] w[4-0]. 450 kThumb2Sbfx, // ubfx rd,rn,#lsb,#width [111100110100] rn[19..16] [0] imm3[14-12] rd[11-8] w[4-0]. 451 kThumb2LdrRRR, // ldr rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 452 kThumb2LdrhRRR, // ldrh rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 453 kThumb2LdrshRRR, // ldrsh rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 454 kThumb2LdrbRRR, // ldrb rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 455 kThumb2LdrsbRRR, // ldrsb rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 456 kThumb2StrRRR, // str rt,[rn,rm,LSL #imm] [111110000100] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 457 kThumb2StrhRRR, // str rt,[rn,rm,LSL #imm] [111110000010] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 458 kThumb2StrbRRR, // str rt,[rn,rm,LSL #imm] [111110000000] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0]. 459 kThumb2LdrhRRI12, // ldrh rt,[rn,#imm12] [111110001011] rt[15..12] rn[19..16] imm12[11..0]. 460 kThumb2LdrshRRI12, // ldrsh rt,[rn,#imm12] [111110011011] rt[15..12] rn[19..16] imm12[11..0]. 461 kThumb2LdrbRRI12, // ldrb rt,[rn,#imm12] [111110001001] rt[15..12] rn[19..16] imm12[11..0]. 462 kThumb2LdrsbRRI12, // ldrsb rt,[rn,#imm12] [111110011001] rt[15..12] rn[19..16] imm12[11..0]. 463 kThumb2StrhRRI12, // strh rt,[rn,#imm12] [111110001010] rt[15..12] rn[19..16] imm12[11..0]. 464 kThumb2StrbRRI12, // strb rt,[rn,#imm12] [111110001000] rt[15..12] rn[19..16] imm12[11..0]. 465 kThumb2Pop, // pop [1110100010111101] list[15-0]*/ 466 kThumb2Push, // push [1110100100101101] list[15-0]*/ 467 kThumb2CmpRI8M, // cmp rn, #<const> [11110] i [011011] rn[19-16] [0] imm3 [1111] imm8[7..0]. 468 kThumb2CmnRI8M, // cmn rn, #<const> [11110] i [010001] rn[19-16] [0] imm3 [1111] imm8[7..0]. 469 kThumb2AdcRRR, // adc [111010110101] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 470 kThumb2AndRRR, // and [111010100000] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 471 kThumb2BicRRR, // bic [111010100010] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 472 kThumb2CmnRR, // cmn [111010110001] rn[19..16] [0000] [1111] [0000] rm[3..0]. 473 kThumb2EorRRR, // eor [111010101000] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 474 kThumb2MulRRR, // mul [111110110000] rn[19..16] [1111] rd[11..8] [0000] rm[3..0]. 475 kThumb2SdivRRR, // sdiv [111110111001] rn[19..16] [1111] rd[11..8] [1111] rm[3..0]. 476 kThumb2UdivRRR, // udiv [111110111011] rn[19..16] [1111] rd[11..8] [1111] rm[3..0]. 477 kThumb2MnvRR, // mvn [11101010011011110] rd[11-8] [0000] rm[3..0]. 478 kThumb2RsubRRI8M, // rsb rd, rn, #<const> [11110] i [011101] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 479 kThumb2NegRR, // actually rsub rd, rn, #0. 480 kThumb2OrrRRR, // orr [111010100100] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 481 kThumb2TstRR, // tst [111010100001] rn[19..16] [0000] [1111] [0000] rm[3..0]. 482 kThumb2LslRRR, // lsl [111110100000] rn[19..16] [1111] rd[11..8] [0000] rm[3..0]. 483 kThumb2LsrRRR, // lsr [111110100010] rn[19..16] [1111] rd[11..8] [0000] rm[3..0]. 484 kThumb2AsrRRR, // asr [111110100100] rn[19..16] [1111] rd[11..8] [0000] rm[3..0]. 485 kThumb2RorRRR, // ror [111110100110] rn[19..16] [1111] rd[11..8] [0000] rm[3..0]. 486 kThumb2LslRRI5, // lsl [11101010010011110] imm3[14..12] rd[11..8] imm2[7..6] [00] rm[3..0]. 487 kThumb2LsrRRI5, // lsr [11101010010011110] imm3[14..12] rd[11..8] imm2[7..6] [01] rm[3..0]. 488 kThumb2AsrRRI5, // asr [11101010010011110] imm3[14..12] rd[11..8] imm2[7..6] [10] rm[3..0]. 489 kThumb2RorRRI5, // ror [11101010010011110] imm3[14..12] rd[11..8] imm2[7..6] [11] rm[3..0]. 490 kThumb2BicRRI8M, // bic rd, rn, #<const> [11110] i [000010] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 491 kThumb2AndRRI8M, // and rd, rn, #<const> [11110] i [000000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 492 kThumb2OrrRRI8M, // orr rd, rn, #<const> [11110] i [000100] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 493 kThumb2OrnRRI8M, // orn rd, rn, #<const> [11110] i [000110] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 494 kThumb2EorRRI8M, // eor rd, rn, #<const> [11110] i [001000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 495 kThumb2AddRRI8M, // add rd, rn, #<const> [11110] i [010001] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 496 kThumb2AdcRRI8M, // adc rd, rn, #<const> [11110] i [010101] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 497 kThumb2SubRRI8M, // sub rd, rn, #<const> [11110] i [011011] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 498 kThumb2SbcRRI8M, // sub rd, rn, #<const> [11110] i [010111] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0]. 499 kThumb2RevRR, // rev [111110101001] rm[19..16] [1111] rd[11..8] 1000 rm[3..0] 500 kThumb2RevshRR, // rev [111110101001] rm[19..16] [1111] rd[11..8] 1011 rm[3..0] 501 kThumb2It, // it [10111111] firstcond[7-4] mask[3-0]. 502 kThumb2Fmstat, // fmstat [11101110111100011111101000010000]. 503 kThumb2Vcmpd, // vcmp [111011101] D [11011] rd[15-12] [1011] E [1] M [0] rm[3-0]. 504 kThumb2Vcmps, // vcmp [111011101] D [11010] rd[15-12] [1011] E [1] M [0] rm[3-0]. 505 kThumb2LdrPcRel12, // ldr rd,[pc,#imm12] [1111100011011111] rt[15-12] imm12[11-0]. 506 kThumb2BCond, // b<c> [1110] S cond[25-22] imm6[21-16] [10] J1 [0] J2 imm11[10..0]. 507 kThumb2Fmrs, // vmov [111011100000] vn[19-16] rt[15-12] [1010] N [0010000]. 508 kThumb2Fmsr, // vmov [111011100001] vn[19-16] rt[15-12] [1010] N [0010000]. 509 kThumb2Fmrrd, // vmov [111011000100] rt2[19-16] rt[15-12] [101100] M [1] vm[3-0]. 510 kThumb2Fmdrr, // vmov [111011000101] rt2[19-16] rt[15-12] [101100] M [1] vm[3-0]. 511 kThumb2Vabsd, // vabs.f64 [111011101] D [110000] rd[15-12] [1011110] M [0] vm[3-0]. 512 kThumb2Vabss, // vabs.f32 [111011101] D [110000] rd[15-12] [1010110] M [0] vm[3-0]. 513 kThumb2Vnegd, // vneg.f64 [111011101] D [110000] rd[15-12] [1011110] M [0] vm[3-0]. 514 kThumb2Vnegs, // vneg.f32 [111011101] D [110000] rd[15-12] [1010110] M [0] vm[3-0]. 515 kThumb2Vmovs_IMM8, // vmov.f32 [111011101] D [11] imm4h[19-16] vd[15-12] [10100000] imm4l[3-0]. 516 kThumb2Vmovd_IMM8, // vmov.f64 [111011101] D [11] imm4h[19-16] vd[15-12] [10110000] imm4l[3-0]. 517 kThumb2Mla, // mla [111110110000] rn[19-16] ra[15-12] rd[11-8] [0000] rm[3-0]. 518 kThumb2Mls, // mls [111110110000] rn[19-16] ra[15-12] rd[11-8] [0001] rm[3-0]. 519 kThumb2Umull, // umull [111110111010] rn[19-16], rdlo[15-12] rdhi[11-8] [0000] rm[3-0]. 520 kThumb2Ldrex, // ldrex [111010000101] rn[19-16] rt[15-12] [1111] imm8[7-0]. 521 kThumb2Ldrexd, // ldrexd [111010001101] rn[19-16] rt[15-12] rt2[11-8] [11111111]. 522 kThumb2Strex, // strex [111010000100] rn[19-16] rt[15-12] rd[11-8] imm8[7-0]. 523 kThumb2Strexd, // strexd [111010001100] rn[19-16] rt[15-12] rt2[11-8] [0111] Rd[3-0]. 524 kThumb2Clrex, // clrex [11110011101111111000111100101111]. 525 kThumb2Bfi, // bfi [111100110110] rn[19-16] [0] imm3[14-12] rd[11-8] imm2[7-6] [0] msb[4-0]. 526 kThumb2Bfc, // bfc [11110011011011110] [0] imm3[14-12] rd[11-8] imm2[7-6] [0] msb[4-0]. 527 kThumb2Dmb, // dmb [1111001110111111100011110101] option[3-0]. 528 kThumb2LdrPcReln12, // ldr rd,[pc,-#imm12] [1111100011011111] rt[15-12] imm12[11-0]. 529 kThumb2Stm, // stm <list> [111010010000] rn[19-16] 000 rl[12-0]. 530 kThumbUndefined, // undefined [11011110xxxxxxxx]. 531 kThumb2VPopCS, // vpop <list of callee save fp singles (s16+). 532 kThumb2VPushCS, // vpush <list callee save fp singles (s16+). 533 kThumb2Vldms, // vldms rd, <list>. 534 kThumb2Vstms, // vstms rd, <list>. 535 kThumb2BUncond, // b <label>. 536 kThumb2Bl, // bl with linker fixup. [11110] S imm10 [11] J1 [1] J2 imm11. 537 kThumb2MovImm16H, // similar to kThumb2MovImm16, but target high hw. 538 kThumb2AddPCR, // Thumb2 2-operand add with hard-coded PC target. 539 kThumb2Adr, // Special purpose encoding of ADR for switch tables. 540 kThumb2MovImm16LST, // Special purpose version for switch table use. 541 kThumb2MovImm16HST, // Special purpose version for switch table use. 542 kThumb2LdmiaWB, // ldmia [111010011001[ rn[19..16] mask[15..0]. 543 kThumb2OrrRRRs, // orrs [111010100101] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 544 kThumb2Push1, // t3 encoding of push. 545 kThumb2Pop1, // t3 encoding of pop. 546 kThumb2RsubRRR, // rsb [111010111101] rn[19..16] [0000] rd[11..8] [0000] rm[3..0]. 547 kThumb2Smull, // smull [111110111000] rn[19-16], rdlo[15-12] rdhi[11-8] [0000] rm[3-0]. 548 kThumb2LdrdPcRel8, // ldrd rt, rt2, pc +-/1024. 549 kThumb2LdrdI8, // ldrd rt, rt2, [rn +-/1024]. 550 kThumb2StrdI8, // strd rt, rt2, [rn +-/1024]. 551 kArmLast, 552 }; 553 std::ostream& operator<<(std::ostream& os, const ArmOpcode& rhs); 554 555 enum ArmOpDmbOptions { 556 kSY = 0xf, 557 kST = 0xe, 558 kISH = 0xb, 559 kISHST = 0xa, 560 kNSH = 0x7, 561 kNSHST = 0x6 562 }; 563 564 // Instruction assembly field_loc kind. 565 enum ArmEncodingKind { 566 kFmtUnused, // Unused field and marks end of formats. 567 kFmtBitBlt, // Bit string using end/start. 568 kFmtLdmRegList, // Load multiple register list using [15,14,12..0]. 569 kFmtStmRegList, // Store multiple register list using [14,12..0]. 570 kFmtDfp, // Double FP reg. 571 kFmtSfp, // Single FP reg. 572 kFmtModImm, // Shifted 8-bit immed using [26,14..12,7..0]. 573 kFmtImm16, // Zero-extended immed using [26,19..16,14..12,7..0]. 574 kFmtImm6, // Encoded branch target using [9,7..3]0. 575 kFmtImm12, // Zero-extended immediate using [26,14..12,7..0]. 576 kFmtShift, // Shift descriptor, [14..12,7..4]. 577 kFmtLsb, // least significant bit using [14..12][7..6]. 578 kFmtBWidth, // bit-field width, encoded as width-1. 579 kFmtShift5, // Shift count, [14..12,7..6]. 580 kFmtBrOffset, // Signed extended [26,11,13,21-16,10-0]:0. 581 kFmtFPImm, // Encoded floating point immediate. 582 kFmtOff24, // 24-bit Thumb2 unconditional branch encoding. 583 kFmtSkip, // Unused field, but continue to next. 584 }; 585 std::ostream& operator<<(std::ostream& os, const ArmEncodingKind& rhs); 586 587 // Struct used to define the snippet positions for each Thumb opcode. 588 struct ArmEncodingMap { 589 uint32_t skeleton; 590 struct { 591 ArmEncodingKind kind; 592 int end; // end for kFmtBitBlt, 1-bit slice end for FP regs. 593 int start; // start for kFmtBitBlt, 4-bit slice end for FP regs. 594 } field_loc[4]; 595 ArmOpcode opcode; 596 uint64_t flags; 597 const char* name; 598 const char* fmt; 599 int size; // Note: size is in bytes. 600 FixupKind fixup; 601 }; 602 603 } // namespace art 604 605 #endif // ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_ 606
