| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 188 unsigned ADDu = isN64 ? Mips::DADDu : Mips::ADDu;
195 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
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| MipsSEFrameLowering.cpp | 393 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
501 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
527 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
538 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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| MipsSEInstrInfo.cpp | 91 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
364 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
374 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
613 unsigned ADDU = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
621 // addu $ra, $v0, $zero
622 // addu $sp, $sp, $v1
626 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
629 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA
[all...] |
| MipsSEISelDAGToDAG.cpp | 177 // addu $v1, $v0, $t9
182 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
195 // 2. addu $globalbasereg, $2, $t9
205 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
209 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
239 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
719 unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
[all...] |
| MipsLongBranch.cpp | 287 // addu $at, $ra, $at
328 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
|
| MipsAsmPrinter.cpp | [all...] |
| MipsISelLowering.cpp | [all...] |
| MipsFastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 681 // addu $gp, $gp, $reg
718 TmpInst.setOpcode(Mips::ADDu);
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
