| /art/compiler/dex/ |
| mir_dataflow.cc | 45 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
48 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
51 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
66 DF_DA | DF_A_WIDE,
81 DF_UA | DF_A_WIDE,
99 DF_DA | DF_A_WIDE | DF_SETS_CONST,
102 DF_DA | DF_A_WIDE | DF_SETS_CONST,
105 DF_DA | DF_A_WIDE | DF_SETS_CONST,
108 DF_DA | DF_A_WIDE | DF_SETS_CONST,
240 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN
[all...] |
| mir_graph.h | 91 #define DF_A_WIDE (UINT64_C(1) << kAWide)
[all...] |
| mir_optimization.cc | 110 if (df_attributes & DF_A_WIDE) {
[all...] |
| gvn_dead_code_elimination_test.cc | 300 mir->dalvikInsn.vA = SRegToVReg(def->defs[0], (df_attrs & DF_A_WIDE) != 0);
302 if ((df_attrs & DF_A_WIDE) != 0) {
310 mir->dalvikInsn.vA = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_A_WIDE) != 0);
[all...] |
| type_inference.cc | [all...] |
| mir_graph.cc | 779 def_count_ += (df_flags & DF_A_WIDE) ? 2 : 1;
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.cc | 493 if (attrs & DF_A_WIDE) {
518 if (attrs & DF_A_WIDE) {
[all...] |
| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | [all...] |
