| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 185 /// index DefIdx can be bypassed when it's read by an instruction of
187 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
191 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
193 if (Forwardings[FirstDefIdx + DefIdx] == 0)
201 return Forwardings[FirstDefIdx + DefIdx] ==
208 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
213 int DefCycle = getOperandCycle(DefClass, DefIdx);
223 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
|
| MCSubtargetInfo.h | 113 unsigned DefIdx) const {
114 assert(DefIdx < SC->NumWriteLatencyEntries &&
115 "MachineModel does not specify a WriteResource for DefIdx");
117 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 128 unsigned DefIdx = 0;
132 ++DefIdx;
134 return DefIdx;
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
192 STI->getWriteLatencyEntry(SCDesc, DefIdx);
208 // If DefIdx does not exist in the model (e.g. implicit defs), then return
216 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
235 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries
[all...] |
| PeepholeOptimizer.cpp | 195 unsigned DefIdx;
251 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
255 DefIdx = MRI.def_begin(Reg).getOperandNo();
260 /// the pair \p MI, \p DefIdx.
266 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
270 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
272 assert(DefIdx < Def->getDesc().getNumDefs() &&
273 Def->getOperand(DefIdx).isReg() && "Invalid definition");
274 Reg = Def->getOperand(DefIdx).getReg()
[all...] |
| TargetInstrInfo.cpp | 722 SDNode *DefNode, unsigned DefIdx,
732 return ItinData->getOperandCycle(DefClass, DefIdx);
734 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
798 unsigned DefIdx) const {
803 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
811 const MachineInstr *DefMI, unsigned DefIdx,
815 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
844 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
848 const MachineInstr *DefMI, unsigned DefIdx,
859 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx)
[all...] |
| LiveRangeCalc.cpp | 46 SlotIndex DefIdx =
50 LR.createDeadDef(DefIdx, Alloc);
178 unsigned DefIdx;
181 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
184 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
|
| LiveRangeEdit.cpp | 126 SlotIndex DefIdx;
128 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
130 DefIdx = RM.ParentVNI->def;
131 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| MachineVerifier.cpp | [all...] |
| MachineInstr.cpp | 757 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
758 if (DefIdx != -1)
759 tieOperands(DefIdx, OpNo);
[all...] |
| RegisterCoalescer.cpp | 651 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
652 assert(DefIdx != -1);
654 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
755 SlotIndex DefIdx = UseIdx.getRegSlot();
756 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
759 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
760 assert(DVNI->def == DefIdx);
763 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
[all...] |
| InlineSpiller.cpp | [all...] |
| RegAllocFast.cpp | 743 unsigned DefIdx = 0;
744 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
746 << DefIdx << ".\n");
[all...] |
| MachineLICM.cpp | 205 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 292 /// and \p DefIdx.
301 /// with the pair \p MI, \p DefIdx. False otherwise.
309 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
313 /// and \p DefIdx.
319 /// with the pair \p MI, \p DefIdx. False otherwise.
327 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
331 /// and \p DefIdx.
339 /// with the pair \p MI, \p DefIdx. False otherwise.
347 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 43 /// and \p DefIdx.
52 /// with the pair \p MI, \p DefIdx. False otherwise.
56 const MachineInstr &MI, unsigned DefIdx,
60 /// and \p DefIdx.
66 /// with the pair \p MI, \p DefIdx. False otherwise.
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
73 /// and \p DefIdx.
81 /// with the pair \p MI, \p DefIdx. False otherwise.
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
277 const MachineInstr *DefMI, unsigned DefIdx,
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 136 unsigned DefIdx;
154 return DefIdx-1;
|
| ScheduleDAGSDNodes.cpp | 556 DefIdx = 0;
562 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
570 for (;DefIdx < NodeNumDefs; ++DefIdx) {
571 if (!Node->hasAnyUseOfValue(DefIdx))
573 ValueType = Node->getSimpleValueType(DefIdx);
574 ++DefIdx;
636 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
640 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
[all...] |
| InstrEmitter.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 99 const MachineInstr *DefMI, unsigned DefIdx,
103 SDNode *DefNode, unsigned DefIdx,
105 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
111 unsigned DefIdx) const override {
|
| PPCInstrInfo.cpp | 107 const MachineInstr *DefMI, unsigned DefIdx,
110 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
113 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 175 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
|
| MachineInstr.h | [all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 205 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
206 DefIdx != DefEnd; ++DefIdx) {
209 DefIdx);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 425 const MachineInstr *DefMI, unsigned DefIdx,
|
