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  /external/llvm/lib/Transforms/InstCombine/
InstCombineSimplifyDemanded.cpp 26 /// are any bits set in the constant that are not demanded. If so, shrink the
29 APInt Demanded) {
37 // If there are no bits set that aren't demanded, nothing to do.
38 Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth());
39 if ((~Demanded & OpC->getValue()) == 0)
42 // This instruction is producing bits that are not demanded. Shrink the RHS.
43 Demanded &= OpC->getValue();
44 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
96 /// value based on the demanded bits. When this function is called, it is know
    [all...]
  /external/llvm/include/llvm/Target/
TargetLowering.h     [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 283 /// are any bits set in the constant that are not demanded. If so, shrink the
286 const APInt &Demanded) {
299 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
303 if (C->getAPIntValue().intersects(~Demanded)) {
306 DAG.getConstant(Demanded &
326 const APInt &Demanded,
345 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
444 // If all of the demanded bits are known one on one side, return the other.
450 // If all of the demanded bits in the inputs are known zeros, return zero.
475 // If all of the demanded bits are known zero on one side, return the other
    [all...]
DAGCombiner.cpp 181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
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  /external/llvm/lib/Target/R600/
AMDGPUISelLowering.cpp     [all...]
SIISelLowering.cpp     [all...]

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