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  /external/valgrind/callgrind/tests/
notpower2-hwpref.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw
notpower2-use.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw AcCost1 SpLoss1 AcCost2 SpLoss2
notpower2-wb.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw ILdmr DLdmr DLdmw
notpower2.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw
simwork-both.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw Bc Bcm Bi Bim
simwork-cache.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw
simwork1.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw
simwork2.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw ILdmr DLdmr DLdmw
simwork3.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw AcCost1 SpLoss1 AcCost2 SpLoss2
threads-use.stderr.exp 3 Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw AcCost1 SpLoss1 AcCost2 SpLoss2 Ge sysCount sysTime
  /external/valgrind/cachegrind/
cg_main.c 109 CacheCC Dw; /* Data write/modify counts */
274 lineCC->Dw.a = 0;
275 lineCC->Dw.m1 = 0;
276 lineCC->Dw.mL = 0;
410 &n->parent->Dw.m1, &n->parent->Dw.mL);
411 n->parent->Dw.a++;
434 &n->parent->Dw.m1, &n->parent->Dw.mL);
435 n->parent->Dw.a++
    [all...]
  /external/valgrind/callgrind/
main.c 204 notified event where possible (Dw immediately following Dr and
259 } Dw;
283 case Ev_Dw: return ev->Ev.Dw.ea;
292 case Ev_Dw: return ev->Ev.Dw.szB;
344 VG_(printf)("Dw (InstrInfo %p) at +%d %d EA=",
345 ev->inode, ev->inode->instr_offset, ev->Ev.Dw.szB);
346 ppIRExpr(ev->Ev.Dw.ea);
408 // extend event set by Dw counters
457 Dm events have same effect as Dw events */
479 /* Merge an Ir with a following Dw/Dm. *
    [all...]

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