| /external/v8/src/arm64/ |
| constants-arm64.h | 416 FP64 = 0x00400000
[all...] |
| simulator-arm64.cc | [all...] |
| assembler-arm64-inl.h | [all...] |
| /external/vixl/src/vixl/a64/ |
| constants-a64.h | 399 FP64 = 0x00400000
419 NEON_FP_2D = FP64 | NEON_Q
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.h | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 109 MachineBasicBlock::iterator I, bool FP64) const;
111 MachineBasicBlock::iterator I, bool FP64) const;
|
| MipsSEFrameLowering.cpp | 68 MachineBasicBlock::iterator I, bool FP64) const;
70 MachineBasicBlock::iterator I, bool FP64) const;
269 bool FP64) const {
276 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
283 (FP64 && !Subtarget.useOddSPReg())) {
296 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
321 bool FP64) const {
328 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
336 (FP64 && !Subtarget.useOddSPReg())) {
349 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass
[all...] |
| MipsSEInstrInfo.cpp | 514 bool FP64) const {
528 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
545 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
553 bool FP64) const {
579 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
598 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUSubtarget.h | 59 bool FP64;
124 return FP64;
|
| AMDGPUSubtarget.cpp | 38 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
46 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
68 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
|
| /external/llvm/test/MC/SystemZ/ |
| regs-bad.s | 116 # Test FP64 operands
|
| /external/valgrind/coregrind/ |
| m_machine.c | [all...] |
