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    Searched refs:GetRegNum (Results 1 - 18 of 18) sorted by null

  /art/compiler/dex/quick/arm/
call_arm.cc 87 NewLIR2(kThumb2LdmiaWB, r_base.GetReg(), (1 << r_key.GetRegNum()) | (1 << r_disp.GetRegNum()));
417 if ((core_spill_mask_ & ~(0xffu | (1u << rs_rARM_LR.GetRegNum()))) == 0u) {
419 constexpr int lr_bit_shift = rs_rARM_LR.GetRegNum() - 8;
421 (core_spill_mask_ & ~(1u << rs_rARM_LR.GetRegNum())) |
422 ((core_spill_mask_ & (1u << rs_rARM_LR.GetRegNum())) >> lr_bit_shift));
549 bool unspill_LR_to_PC = (core_spill_mask_ & (1 << rs_rARM_LR.GetRegNum())) != 0;
551 core_spill_mask_ &= ~(1 << rs_rARM_LR.GetRegNum());
552 core_spill_mask_ |= (1 << rs_rARM_PC.GetRegNum());
555 if ((core_spill_mask_ & ~(0xffu | (1u << rs_rARM_PC.GetRegNum()))) == 0u)
    [all...]
target_arm.cc 146 ? ResourceMask::TwoBits(reg.GetRegNum() * 2 + kArmFPReg0)
147 : ResourceMask::Bit(reg.IsSingle() ? reg.GetRegNum() + kArmFPReg0 : reg.GetRegNum());
306 reg_id = rs_rARM_LR.GetRegNum();
308 reg_id = rs_rARM_PC.GetRegNum();
607 int sp_reg_num = info->GetReg().GetRegNum();
645 core_spill_mask_ |= (1 << rs_rARM_LR.GetRegNum());
656 DCHECK_GE(reg.GetRegNum(), ARM_FP_CALLEE_SAVE_BASE);
657 int adjusted_reg_num = reg.GetRegNum() - ARM_FP_CALLEE_SAVE_BASE;
672 int reg_num = reg.GetRegNum() << 1
    [all...]
codegen_arm.h 327 DCHECK((low.GetRegNum() % 2 == 0) && (low.GetRegNum() + 1 == high.GetRegNum()));
329 return RegStorage::FloatSolo64(low.GetRegNum() / 2);
340 int reg_num = reg.GetRegNum();
int_arm.cc     [all...]
  /art/compiler/dex/quick/x86/
call_x86.cc 291 (1u << rs_rDI.GetRegNum()) | (1u << rs_rSI.GetRegNum()) | (1u << rs_rRET.GetRegNum());
294 core_spill_mask_ = (1u << rs_rRET.GetRegNum());
305 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rDI.GetRegNum()), 0);
308 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rSI.GetRegNum()), 0);
323 cfi_.Restore(DwarfCoreReg(cu_->target64, rs_rSI.GetRegNum()));
326 cfi_.Restore(DwarfCoreReg(cu_->target64, rs_rDI.GetRegNum()));
assemble_x86.cc     [all...]
target_x86.cc 270 ((reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0) + reg.GetRegNum());
466 core_spill_mask_ |= (1 << rs_rRET.GetRegNum());
473 DCHECK_LT(reg.GetRegNum(), rs_rX86_SP_32.GetRegNum());
483 return cu_->target64 || reg.GetRegNum() < rs_rX86_SP_32.GetRegNum();
677 int sp_reg_num = info->GetReg().GetRegNum();
697 int x_reg_num = info->GetReg().GetRegNum();
740 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum());
761 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum());
    [all...]
x86_lir.h 241 static_assert(rs_rX86_SP_64.GetRegNum() == rs_rX86_SP_32.GetRegNum(), "Unexpected mismatch");
    [all...]
utility_x86.cc 237 if (r_src2.GetRegNum() >= rs_rX86_SP_32.GetRegNum()) {
    [all...]
int_x86.cc 321 (rl_src.location == kLocPhysReg && rl_src.reg.GetRegNum() == rl_result.reg.GetRegNum());
    [all...]
  /art/compiler/dex/quick/
quick_cfi_test.cc 93 m2l->core_spill_mask_ |= 1 << info->GetReg().GetRegNum();
99 m2l->fp_spill_mask_ |= 1 << info->GetReg().GetRegNum();
ralloc_util.cc 148 info->GetReg().GetReg(), info->GetReg().GetRegNum(), info->GetReg().IsFloat() ? 'f' : 'c',
261 int reg_num = reg.GetRegNum();
294 int reg_num = reg.GetRegNum();
352 DCHECK_EQ(info->GetReg().GetRegNum(), partner->Partner().GetRegNum());
379 DCHECK_EQ(info->GetReg().GetRegNum(), partner->Partner().GetRegNum());
    [all...]
  /art/compiler/dex/
reg_storage.h 257 constexpr int GetRegNum() const {
263 return GetRegNum() < 8;
268 return GetRegNum() < 4;
  /art/compiler/dex/quick/mips/
target_mips.cc 180 DCHECK_EQ(reg.GetRegNum() & 1, 0);
181 int reg_num = (reg.GetRegNum() & ~1) | RegStorage::kFloatingPoint;
191 int reg_num = reg.GetRegNum() | RegStorage::kFloatingPoint;
204 ret_reg = RegStorage::FloatSolo64(low.GetRegNum());
296 return ResourceMask::Bit((reg.IsFloat() ? kMipsFPReg0 : 0) + reg.GetRegNum());
299 return ResourceMask::TwoBits((reg.GetRegNum() & ~1) + kMipsFPReg0);
301 return ResourceMask::Bit(reg.GetRegNum() + kMipsFPReg0);
303 return ResourceMask::Bit(reg.GetRegNum());
517 core_spill_mask_ |= (1 << rs_rRA.GetRegNum());
693 int sp_reg_num = info->GetReg().GetRegNum();
    [all...]
call_mips.cc 389 core_spill_mask_ = (1u << TargetPtrReg(kLr).GetRegNum());
  /art/compiler/dex/quick/arm64/
target_arm64.cc 157 (reg.IsFloat() ? kA64FPReg0 : 0) + reg.GetRegNum());
632 int fp_reg_num = info->GetReg().GetRegNum();
645 int x_reg_num = info->GetReg().GetRegNum();
670 core_spill_mask_ |= (1 << rs_xLR.GetRegNum());
arm64_lir.h 103 #define A64_REGSTORAGE_IS_SP_OR_ZR(rs) (((rs).GetRegNum() & 0x1f) == 0x1f)
call_arm64.cc 428 core_spill_mask_ = (1u << rs_xLR.GetRegNum());

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