| /art/compiler/dex/quick/arm64/ |
| assemble_arm64.cc | 118 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1,
122 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
126 kFmtExtend, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
144 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
215 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
219 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
223 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
227 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
239 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
243 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE12
[all...] |
| utility_arm64.cc | 753 if (EncodingMap[opcode].flags & IS_QUAD_OP) {
927 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP)
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | [all...] |
| utility_arm.cc | 410 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) {
501 if (EncodingMap[opcode].flags & IS_QUAD_OP) {
646 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP)
[all...] |
| /art/compiler/dex/quick/ |
| local_optimizations.cc | 40 #define LOAD_STORE_FILTER(flags) ((flags & (IS_QUAD_OP|IS_STORE)) == (IS_QUAD_OP|IS_STORE) || \
41 (flags & (IS_QUAD_OP|IS_LOAD)) == (IS_QUAD_OP|IS_LOAD) || \
|
| mir_to_lir-inl.h | 122 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_QUAD_OP))
|
| mir_to_lir.h | 50 #define IS_QUAD_OP (1ULL << kIsQuadOp)
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 154 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },
158 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },
161 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },
165 { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" },
168 { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" },
233 { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" },
234 { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" },
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 151 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
535 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | REG_USE_LR |
539 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | NEEDS_FIXUP,
543 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0_USE0 | NEEDS_FIXUP,
[all...] |
