| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 644 EVT InnerVT = InnerOp.getValueType();
645 unsigned InnerBits = InnerVT.getSizeInBits();
647 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
648 EVT ShTy = getShiftAmountTy(InnerVT);
650 ShTy = InnerVT;
652 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 597 for (MVT InnerVT : MVT::vector_valuetypes()) {
598 setTruncStoreAction(VT, InnerVT, Expand);
599 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
600 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
601 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
665 for (MVT InnerVT : MVT::all_valuetypes())
666 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 411 for (MVT InnerVT : MVT::vector_valuetypes()) {
412 setTruncStoreAction(VT, InnerVT, Expand);
413 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
414 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
415 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 478 for (MVT InnerVT : MVT::vector_valuetypes()) {
479 setTruncStoreAction(VT, InnerVT, Expand);
480 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
481 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 737 for (MVT InnerVT : MVT::vector_valuetypes())
[all...] |
