/art/compiler/dex/ |
mir_graph.h | 222 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that 249 class MIR : public ArenaObject<kArenaAllocMIR> { 253 * additional fields on as-needed basis. Question: how to support MIR Pseudo-ops; probably 334 int16_t m_unit_index; // From which method was this MIR included 336 MIR* next; 342 MIR* throw_insn; 356 explicit MIR() : offset(0), optimization_flags(0), m_unit_index(0), bb(NullBasicBlockId), 365 MIR* Copy(CompilationUnit *c_unit); 366 MIR* Copy(MIRGraph* mir_Graph); 401 MIR* first_mir_insn 547 MIR* mir; member in struct:art::CallInfo [all...] |
gvn_dead_code_elimination.h | 29 class MIR; 62 explicit MIRData(MIR* m) 63 : mir(m), uses_all_vregs(false), must_keep(false), is_move(false), is_move_src(false), 73 MIR* mir; member in struct:art::GvnDeadCodeElimination::MIRData 74 bool uses_all_vregs : 1; // If mir uses all vregs, uses in mir->ssa_rep are irrelevant. 93 void AddMIRWithDef(MIR* mir, int v_reg, bool wide, uint16_t new_value); 94 void AddMIRWithoutDef(MIR* mir) [all...] |
local_value_numbering.h | 85 uint16_t GetValueNumber(MIR* mir); 307 uint16_t MarkNonAliasingNonNull(MIR* mir); 311 void HandleNullCheck(MIR* mir, uint16_t reg); 312 void HandleRangeCheck(MIR* mir, uint16_t array, uint16_t index); 313 void HandleDivZeroCheck(MIR* mir, uint16_t reg) [all...] |
post_opt_passes.cc | 30 MIR* mir = bb->first_mir_insn; local 32 while (mir != nullptr) { 33 MIR* next = mir->next; 35 Instruction::Code opcode = mir->dalvikInsn.opcode; 38 bb->RemoveMIR(mir); 41 mir = next; 44 // We do not care in reporting a change or not in the MIR.
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mir_graph.cc | 169 int MIRGraph::ParseInsn(const uint16_t* code_ptr, MIR::DecodedInstruction* decoded_instruction) { 187 MIR* insn = orig_block->first_mir_insn; 188 MIR* prev = nullptr; // Will be set to instruction before split. 272 MIR* p = insn; 319 MIR* p = bottom_block->first_mir_insn; 335 if ((opcode == kMirOpCheck) || !MIR::DecodedInstruction::IsPseudoMirOp(opcode)) { 455 BasicBlock* MIRGraph::ProcessCanBranch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, 513 BasicBlock* MIRGraph::ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, 595 BasicBlock* MIRGraph::ProcessCanThrow(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, 679 * pseudo exception edge MIR. Note also that this new block i 998 const MIR* mir; local 1153 MIR* mir = *it; local 1259 MIR* mir = first_mir_insn; local 1773 MIR* mir = new (arena_) MIR(); local [all...] |
mir_optimization.cc | 59 MIR* mir; local 61 for (mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) { 62 // Skip pass if BB has MIR without SSA representation. 63 if (mir->ssa_rep == nullptr) { 67 uint64_t df_attributes = GetDataFlowAttributes(mir); 69 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn 823 MIR* mir = bb->last_mir_insn; local 1805 MIR* mir = NewMIR(); local [all...] |
type_inference.h | 33 class MIR; 378 void AddCheckCast(MIR* check_cast, Type type); 386 void ProcessCheckCast(MIR* mir); 391 BasicBlock* FindDefBlock(MIR* check_cast); 400 // Map check-cast mir to special sreg and type. 405 ScopedArenaSafeMap<MIR*, CheckCastMapValue> check_cast_map_; 436 const Type* const ifields_; // Indexed by MIR::meta::ifield_lowering_info. 437 const Type* const sfields_; // Indexed by MIR::meta::sfield_lowering_info. 438 const MethodSignature* const signatures_; // Indexed by MIR::meta::method_lowering_info [all...] |
mir_dataflow.cc | 25 * instructions, where extended opcode at the MIR level are appended 800 // Beginning of extended MIR opcodes 926 const MIR::DecodedInstruction& d_insn) { 986 MIR* mir; local 998 for (mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) { 999 uint64_t df_attributes = GetDataFlowAttributes(mir); [all...] |
global_value_numbering.h | 127 uint16_t GetIFieldId(MIR* mir) { 128 return GetMirGraph()->GetGvnIFieldId(mir); 132 uint16_t GetSFieldId(MIR* mir) { 133 return GetMirGraph()->GetGvnSFieldId(mir);
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gvn_dead_code_elimination.cc | 90 void GvnDeadCodeElimination::VRegChains::AddMIRWithDef(MIR* mir, int v_reg, bool wide, 93 mir_data_.emplace_back(mir); 122 inline void GvnDeadCodeElimination::VRegChains::AddMIRWithoutDef(MIR* mir) { 123 mir_data_.emplace_back(mir); 152 DCHECK_EQ(static_cast<int>(last_data->mir->dalvikInsn.opcode), static_cast<int>(kMirOpNop)); 365 SSARepresentation* ssa_rep = mir_data_[c].mir->ssa_rep; 380 SSARepresentation* ssa_rep = mir_data_[c].mir->ssa_rep; 393 SSARepresentation* ssa_rep = mir_data_[c].mir->ssa_rep 411 MIR* mir = mir_data_[c].mir; local [all...] |
local_value_numbering.cc | 489 const MIR* mir = fall_through_bb->first_mir_insn; local 490 DCHECK(mir != nullptr); 492 if ((mir->dalvikInsn.FlagsOf() & Instruction::kInvoke) != 0) { 493 HandleInvokeArgs(mir, lvn); [all...] |
type_inference.cc | 158 check_cast_map_(std::less<MIR*>(), alloc->Adapter()), 162 void TypeInference::CheckCastData::AddCheckCast(MIR* check_cast, Type type) { 317 void TypeInference::CheckCastData::ProcessCheckCast(MIR* mir) { 318 auto mir_it = check_cast_map_.find(mir); 320 auto sreg_it = split_sreg_data_.find(mir->ssa_rep->uses[0]); 330 BasicBlock* TypeInference::CheckCastData::FindDefBlock(MIR* check_cast) { 423 MIR* mir = bb->first_mir_insn; local 424 MIR* main_mirs_end = ((bb_df_attrs & DF_SAME_TYPE_AB) != 0u) ? bb->last_mir_insn : nullptr [all...] |
gvn_dead_code_elimination_test.cc | 260 mirs_ = reinterpret_cast<MIR*>(cu_.arena.Alloc(sizeof(MIR) * count, kArenaAllocMIR)); 264 MIR* mir = &mirs_[i]; local 267 bb->AppendMIR(mir); 268 mir->dalvikInsn.opcode = def->opcode; 269 mir->dalvikInsn.vB = static_cast<int32_t>(def->value); 270 mir->dalvikInsn.vB_wide = def->value; 273 mir->meta.ifield_lowering_info = def->field_info; 278 mir->meta.sfield_lowering_info = def->field_info [all...] |
/art/compiler/dex/quick/ |
dex_file_method_inliner.h | 36 class MIR; 95 bool GenInline(MIRGraph* mir_graph, BasicBlock* bb, MIR* invoke, uint32_t method_idx) 360 static bool GenInlineConst(MIRGraph* mir_graph, BasicBlock* bb, MIR* invoke, 361 MIR* move_result, const InlineMethod& method); 362 static bool GenInlineReturnArg(MIRGraph* mir_graph, BasicBlock* bb, MIR* invoke, 363 MIR* move_result, const InlineMethod& method); 364 static bool GenInlineIGet(MIRGraph* mir_graph, BasicBlock* bb, MIR* invoke, 365 MIR* move_result, const InlineMethod& method); 366 static bool GenInlineIPut(MIRGraph* mir_graph, BasicBlock* bb, MIR* invoke, 367 MIR* move_result, const InlineMethod& method) [all...] |
mir_to_lir.h | 142 class MIR; 233 MIR* switch_mir; // The switch mir. 521 MIR* current_mir_; [all...] |
dex_file_method_inliner.cc | 113 MIR* AllocReplacementMIR(MIRGraph* mir_graph, MIR* invoke) { 114 MIR* insn = mir_graph->NewMIR(); 120 uint32_t GetInvokeReg(MIR* invoke, uint32_t arg) { 122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 131 bool WideArgIsInConsecutiveDalvikRegs(MIR* invoke, uint32_t arg) { 133 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 642 bool DexFileMethodInliner::GenInline(MIRGraph* mir_graph, BasicBlock* bb, MIR* invoke, 654 MIR* move_result = nullptr; [all...] |
mir_to_lir.cc | 242 bool Mir2Lir::GenSpecialIGet(MIR* mir, const InlineMethod& special) { 284 GenPrintLabel(mir); 310 bool Mir2Lir::GenSpecialIPut(MIR* mir, const InlineMethod& special) { 358 GenPrintLabel(mir); 374 bool Mir2Lir::GenSpecialIdentity(MIR* mir, const InlineMethod& special) { 384 GenPrintLabel(mir); 394 bool Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special) 1212 MIR* mir; local 1317 MIR* mir = bb->first_mir_insn; local [all...] |
codegen_util.cc | 798 MIR* prev_mir = nullptr; 804 MIR* mir = entry.second; local 805 UpdateReferenceVRegs(mir, prev_mir, references); 807 prev_mir = mir; 824 MIR* mir = entry.second; local 825 UpdateReferenceVRegs(mir, prev_mir, references); 829 prev_mir = mir; 836 MIR* mir = entry.second local [all...] |
/art/compiler/dex/quick/x86/ |
codegen_x86.h | 268 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; 269 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; 270 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; 280 void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 281 void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE [all...] |
target_x86.cc | [all...] |
quick_assemble_x86_test.cc | 193 typedef void (X86Mir2Lir::*AsmFn)(MIR*); 201 // Create a vector MIR. 202 MIR* mir = cu_->mir_graph->NewMIR(); local 203 mir->dalvikInsn.opcode = opcode; 204 mir->dalvikInsn.vA = 0; // Destination and source. 205 mir->dalvikInsn.vB = 1; // Source. 208 mir->dalvikInsn.vC = (vector_type << 16) | vector_size; // Type size. 209 (m2l->*f)(mir);
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/art/compiler/dex/quick/arm/ |
codegen_arm.h | 177 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 178 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 179 void GenSelect(BasicBlock* bb, MIR* mir); 191 void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 192 void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) [all...] |
/art/compiler/dex/quick/arm64/ |
codegen_arm64.h | 178 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; 179 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; 180 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; 193 void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 194 void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE [all...] |
/art/compiler/dex/quick/mips/ |
codegen_mips.h | 178 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 179 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 180 void GenSelect(BasicBlock* bb, MIR* mir); 190 void GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); 191 void GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) [all...] |
call_mips.cc | 35 bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special) { 37 UNUSED(bb, mir, special); 72 void MipsMir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { 73 const uint16_t* table = mir_graph_->GetTable(mir, table_offset); 77 tab_rec->switch_mir = mir; 145 void MipsMir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { 146 const uint16_t* table = mir_graph_->GetTable(mir, table_offset) [all...] |