| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 103 ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,
109 ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,
115 ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
121 ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
127 ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,
133 ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,
139 ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,
177 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" },
178 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" },
189 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" }
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 120 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC | NEEDS_FIXUP,
124 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP,
231 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC
235 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP
284 IS_BINARY_OP | REG_DEF0 | SETS_CCODES,
356 IS_BINARY_OP | REG_DEF0 | REG_USE0 | REG_USE_LIST1 | IS_STORE,
478 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE012,
518 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
522 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 151 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
255 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
263 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
409 kFmtUnused, -1, -1, IS_UNARY_OP | REG_DEF0 | REG_USE_HI,
413 kFmtUnused, -1, -1, IS_UNARY_OP | REG_DEF0 | REG_USE_LO,
535 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | REG_USE_LR |
539 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | NEEDS_FIXUP,
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 59 #define REG_DEF0 (1ULL << kRegDef0)
109 #define REG_DEF01 (REG_DEF0 | REG_DEF1)
110 #define REG_DEF012 (REG_DEF0 | REG_DEF1 | REG_DEF2)
111 #define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
112 #define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
113 #define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
114 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
115 #define REG_DEF0_USE123 (REG_DEF0 | REG_USE123)
116 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
117 #define REG_DEF0_USE2 (REG_DEF0 | REG_USE2
[all...] |
| local_optimizations.cc | 342 ((target_flags & (REG_DEF0 | REG_DEF1)) == (REG_DEF0 | REG_DEF1)) ||
|
| mir_to_lir-inl.h | 215 if (flags & REG_DEF0) {
|
| /art/compiler/dex/quick/arm64/ |
| assemble_arm64.cc | 132 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | NEEDS_FIXUP,
136 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0 | NEEDS_FIXUP,
303 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
388 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP,
393 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP,
465 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0,
469 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0,
[all...] |
