| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 164 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR |
168 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR |
172 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR | NEEDS_FIXUP,
176 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR | NEEDS_FIXUP,
181 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
415 * Note: The encoding map entries for vldrd and vldrs include REG_DEF_LR, even though
422 * another use of lr could be moved across a vldrd/vldrs. By setting REG_DEF_LR, we
423 * prevent that from happening. Note that we set REG_DEF_LR on all vldrd/vldrs - even those
430 REG_DEF_LR | NEEDS_FIXUP, "vldr", "!0s, [!1C, #!2E]", 4, kFixupVLoad),
434 REG_DEF_LR | NEEDS_FIXUP, "vldr", "!0S, [!1C, #!2E]", 4, kFixupVLoad)
[all...] |
| target_arm.cc | 173 REG_USE_LIST1 | REG_USE_FPCS_LIST0 | REG_USE_FPCS_LIST2 | REG_DEF_LR)) != 0) {
237 if (flags & REG_DEF_LR) {
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 115 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR |
243 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
547 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
[all...] |
| target_mips.cc | 325 if (flags & REG_DEF_LR) {
[all...] |
| /art/compiler/dex/quick/arm64/ |
| target_arm64.cc | 175 if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) {
184 if (flags & REG_DEF_LR) {
|
| assemble_arm64.cc | 161 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
169 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR | NEEDS_FIXUP,
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 68 #define REG_DEF_LR (1ULL << kRegDefLR)
[all...] |
