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  /external/llvm/lib/Target/R600/
AMDGPUInstrInfo.cpp 121 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
123 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
135 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
137 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
144 calculateIndirectAddress(RegIndex, Channel),
294 unsigned RegIndex;
296 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
297 ++RegIndex) {
298 if (IndirectRC->getRegister(RegIndex) == Reg
    [all...]
AMDGPUInstrInfo.h 154 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
159 /// address in this virtual address space that maps to the given \p RegIndex
161 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
R600InstrInfo.h 215 unsigned calculateIndirectAddress(unsigned RegIndex,
SIInstrInfo.h 309 unsigned calculateIndirectAddress(unsigned RegIndex,
R600InstrInfo.cpp     [all...]
R600ISelLowering.cpp 608 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
609 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
641 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
642 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
    [all...]
SIInstrInfo.cpp     [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600ISelLowering.cpp 99 int64_t RegIndex = MI->getOperand(1).getImm();
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
  /external/llvm/lib/CodeGen/
RegisterCoalescer.cpp     [all...]
  /external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp     [all...]

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