| /art/compiler/dex/quick/arm/ |
| arm_lir.h | 115 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
116 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
117 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2,
118 r3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3,
120 rARM_SUSPEND = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4
[all...] |
| codegen_arm.h | 38 RegStorage GetNextReg(ShortyArg arg) OVERRIDE;
70 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
71 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
73 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
75 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
76 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
77 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src
[all...] |
| target_arm.cc | 32 static constexpr RegStorage core_regs_arr[] =
36 static constexpr RegStorage core_regs_arr[] =
40 static constexpr RegStorage sp_regs_arr[] =
45 static constexpr RegStorage dp_regs_arr[] =
49 static constexpr RegStorage reserved_regs_arr[] =
51 static constexpr RegStorage core_temps_arr[] = {rs_r0, rs_r1, rs_r2, rs_r3, rs_r12};
53 static constexpr RegStorage reserved_regs_arr[] =
55 static constexpr RegStorage core_temps_arr[] = {rs_r0, rs_r1, rs_r2, rs_r3, rs_r4, rs_r12};
57 static constexpr RegStorage sp_temps_arr[] =
60 static constexpr RegStorage dp_temps_arr[]
[all...] |
| utility_arm.cc | 78 DCHECK(RegStorage::IsSingle(r_dest));
223 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
270 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
285 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
418 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
422 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
428 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type)
[all...] |
| /art/compiler/dex/quick/mips/ |
| mips_lir.h | 144 rZERO = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
145 rZEROd = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0,
146 rAT = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
147 rATd = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 1,
148 rV0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2
[all...] |
| codegen_mips.h | 33 virtual RegStorage GetNextReg(ShortyArg arg);
46 virtual RegStorage GetNextReg(ShortyArg arg);
81 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
82 void ForceImplicitNullCheck(RegStorage reg, int opt_flags, bool is_wide);
83 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
85 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
87 LIR* LoadConstantNoClobber(RegStorage r_dest, int value)
[all...] |
| target_mips.cc | 33 static constexpr RegStorage core_regs_arr_32[] =
38 static constexpr RegStorage sp_regs_arr_32[] =
41 static constexpr RegStorage dp_fr0_regs_arr_32[] =
44 static constexpr RegStorage dp_fr1_regs_arr_32[] =
47 static constexpr RegStorage reserved_regs_arr_32[] =
49 static constexpr RegStorage core_temps_arr_32[] =
52 static constexpr RegStorage sp_fr0_temps_arr_32[] =
55 static constexpr RegStorage sp_fr1_temps_arr_32[] =
57 static constexpr RegStorage dp_fr0_temps_arr_32[] =
60 static constexpr RegStorage dp_fr1_temps_arr_32[]
[all...] |
| fp_mips.cc | 186 static RegStorage GetWideArgFP(bool fpuIs32Bit, size_t base) {
192 return RegStorage(RegStorage::k64BitPair, rFARG0, rFARG1);
194 return RegStorage(RegStorage::k64BitPair, rFARG2, rFARG3);
199 return RegStorage(RegStorage::k64BitSolo, rFARG0);
201 return RegStorage(RegStorage::k64BitSolo, rFARG2);
235 RegStorage r_tmp1
[all...] |
| call_mips.cc | 89 RegStorage r_end = AllocPtrSizeTemp();
108 RegStorage r_base = AllocPtrSizeTemp();
116 RegStorage r_key = AllocTemp();
122 RegStorage r_disp = AllocTemp();
124 const RegStorage rs_ra = TargetPtrReg(kLr);
162 RegStorage r_key;
197 RegStorage r_base = AllocPtrSizeTemp();
201 RegStorage r_disp = AllocTemp();
205 const RegStorage rs_ra = TargetPtrReg(kLr);
218 RegStorage reset_reg = AllocTempRef()
[all...] |
| utility_mips.cc | 32 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
42 RegStorage t_opnd = r_src;
57 RegStorage t_opnd = r_src;
78 RegStorage t_opnd = r_src;
130 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
133 RegStorage r_dest_save = r_dest;
163 LIR* MipsMir2Lir::LoadConstantWideNoClobber(RegStorage r_dest, int64_t value) {
166 RegStorage r_dest_save = r_dest;
280 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src)
[all...] |
| /art/compiler/dex/ |
| reg_storage_eq.h | 24 // Define == and != operators for RegStorage. These are based on exact equality of the reg storage,
28 inline bool operator==(const RegStorage& lhs, const RegStorage& rhs) {
32 inline bool operator!=(const RegStorage& lhs, const RegStorage& rhs) {
|
| reg_storage.h | 69 * one view will affect the other views. The RegStorage class does not concern itself
71 * Distinct RegStorage elements should be created for each view of a physical register
76 class RegStorage : public ValueObject {
108 constexpr RegStorage(RegStorageKind rs_kind, int reg)
114 constexpr RegStorage(RegStorageKind rs_kind, int low_reg, int high_reg)
124 constexpr explicit RegStorage(uint16_t val) : reg_(val) {}
125 RegStorage() : reg_(kInvalid) {}
134 bool ExactlyEquals(const RegStorage& rhs) const {
138 bool NotExactlyEquals(const RegStorage& rhs) const {
233 // Create a stand-alone RegStorage from the low reg of a pair
[all...] |
| reg_location.h | 53 RegStorage reg; // Encoded physical registers.
|
| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 122 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
123 r0q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0,
125 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
126 r1q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 1,
128 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2
[all...] |
| codegen_x86.h | 37 virtual RegStorage GetNextReg(ShortyArg arg);
52 virtual RegStorage GetNextReg(ShortyArg arg);
73 std::vector<RegStorage> temp_regs_;
91 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
92 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
94 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
96 LIR* LoadConstantNoClobber(RegStorage r_dest, int value)
[all...] |
| target_x86.cc | 38 static constexpr RegStorage core_regs_arr_32[] = {
41 static constexpr RegStorage core_regs_arr_64[] = {
45 static constexpr RegStorage core_regs_arr_64q[] = {
49 static constexpr RegStorage sp_regs_arr_32[] = {
52 static constexpr RegStorage sp_regs_arr_64[] = {
56 static constexpr RegStorage dp_regs_arr_32[] = {
59 static constexpr RegStorage dp_regs_arr_64[] = {
63 static constexpr RegStorage xp_regs_arr_32[] = {
66 static constexpr RegStorage xp_regs_arr_64[] = {
70 static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}
[all...] |
| quick_assemble_x86_test.cc | 165 RegStorage::Solo128(0).GetReg(), RegStorage::Solo128(1).GetReg());
167 RegStorage::Solo128(0).GetReg(), RegStorage::Solo128(1).GetReg());
172 RegStorage::Solo128(0).GetReg(), RegStorage::Solo128(1).GetReg());
174 RegStorage::Solo128(0).GetReg(), RegStorage::Solo128(1).GetReg());
179 RegStorage::Solo128(0).GetReg(), RegStorage::Solo128(1).GetReg())
[all...] |
| utility_x86.cc | 33 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
87 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
88 RegStorage r_dest_save = r_dest;
126 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
139 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
201 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
235 // TODO: Similar to Arm's reg < 8 check. Perhaps add attribute checks to RegStorage?
257 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type)
[all...] |
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 34 virtual RegStorage GetNextReg(ShortyArg arg);
66 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
67 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
69 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
71 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE;
72 LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE;
73 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size
[all...] |
| arm64_lir.h | 133 rw##nr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | nr, \
134 rx##nr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | nr, \
135 rf##nr = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | nr, \
136 rd##nr = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | nr,
140 rxzr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0x3f
[all...] |
| target_arm64.cc | 32 static constexpr RegStorage core_regs_arr[] =
38 static constexpr RegStorage core64_regs_arr[] =
44 static constexpr RegStorage sp_regs_arr[] =
49 static constexpr RegStorage dp_regs_arr[] =
56 static constexpr RegStorage reserved_regs_arr[] = {rs_wSELF, rs_wsp, rs_wLR, rs_wzr};
57 static constexpr RegStorage reserved64_regs_arr[] = {rs_xSELF, rs_sp, rs_xLR, rs_xzr};
59 static constexpr RegStorage core_temps_arr[] =
63 static constexpr RegStorage core64_temps_arr[] =
67 static constexpr RegStorage sp_temps_arr[] =
71 static constexpr RegStorage dp_temps_arr[]
[all...] |
| utility_arm64.cc | 112 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) {
136 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) {
394 LIR* Arm64Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
458 LIR* Arm64Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
552 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
564 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) {
630 LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
664 LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2)
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 323 RegisterInfo(RegStorage r, const ResourceMask& mask = kEncodeAll);
354 RegStorage GetReg() { return reg_; }
355 void SetReg(RegStorage reg) { reg_ = reg; }
368 RegStorage Partner() { return partner_; }
369 void SetPartner(RegStorage partner) { partner_ = partner; }
403 RegStorage reg_;
408 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register.
423 const ArrayRef<const RegStorage>& core_regs,
424 const ArrayRef<const RegStorage>& core64_regs,
425 const ArrayRef<const RegStorage>& sp_regs
[all...] |
| local_optimizations.cc | 71 void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src) {
94 DCHECK(RegStorage::SameRegType(lir->operands[0], reg_id));
95 RegStorage dest_reg, src_reg;
104 switch (reg_id & RegStorage::kShapeTypeMask) {
105 case RegStorage::k32BitSolo | RegStorage::kCoreRegister:
106 dest_reg = RegStorage::Solo32(lir->operands[0]);
107 src_reg = RegStorage::Solo32(reg_id);
109 case RegStorage::k64BitSolo | RegStorage::kCoreRegister
[all...] |
| ralloc_util.cc | 45 Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask)
63 const ArrayRef<const RegStorage>& core_regs,
64 const ArrayRef<const RegStorage>& core64_regs,
65 const ArrayRef<const RegStorage>& sp_regs,
66 const ArrayRef<const RegStorage>& dp_regs,
67 const ArrayRef<const RegStorage>& reserved_regs,
68 const ArrayRef<const RegStorage>& reserved64_regs,
69 const ArrayRef<const RegStorage>& core_temps,
70 const ArrayRef<const RegStorage>& core64_temps,
71 const ArrayRef<const RegStorage>& sp_temps
[all...] |
