| /external/llvm/unittests/Transforms/Utils/ |
| Cloning.cpp | 148 BinaryOperator *SDiv = BinaryOperator::Create(Instruction::SDiv, V, V);
149 EXPECT_FALSE(this->clone(SDiv)->isExact());
151 SDiv->setIsExact(true);
152 EXPECT_TRUE(this->clone(SDiv)->isExact());
|
| IntegerDivision.cpp | 23 TEST(IntegerDivision, SDiv) {
42 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv);
163 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv);
|
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 101 /// code generated, e.g. at the sdiv instruction. This will generate a udiv in
437 assert((Div->getOpcode() == Instruction::SDiv ||
453 if (Div->getOpcode() == Instruction::SDiv) {
591 assert((Div->getOpcode() == Instruction::SDiv ||
617 if (Div->getOpcode() == Instruction::SDiv) {
641 assert((Div->getOpcode() == Instruction::SDiv ||
667 if (Div->getOpcode() == Instruction::SDiv) {
|
| BypassSlowDivision.cpp | 233 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
235 bool UseSignedOp = Opcode == Instruction::SDiv ||
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 164 case Instruction::SDiv:
|
| /external/llvm/include/llvm/IR/ |
| Operator.h | 73 /// Add, Sub, and Mul. It does not include SDiv, despite that operator having
125 /// A udiv or sdiv instruction, which can be marked as "exact",
147 return OpC == Instruction::SDiv ||
348 : public ConcreteOperator<PossiblyExactOperator, Instruction::SDiv> {
|
| PatternMatch.h | 476 inline BinaryOp_match<LHS, RHS, Instruction::SDiv> m_SDiv(const LHS &L,
478 return BinaryOp_match<LHS, RHS, Instruction::SDiv>(L, R);
669 /// \brief Matches UDiv and SDiv.
671 inline BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>
673 return BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>(L, R);
[all...] |
| InstrTypes.h | 270 DEFINE_HELPERS(SDiv, Exact) // CreateExactSDiv
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreLowerThreadLocal.cpp | 93 case Instruction::SDiv:
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 10 // This file implements the visit functions for mul, fmul, sdiv, udiv, fdiv,
300 BO->getOpcode() != Instruction::SDiv)) {
308 BO->getOpcode() == Instruction::SDiv)) {
312 if (PossiblyExactOperator *SDiv = dyn_cast<PossiblyExactOperator>(BO))
313 if (SDiv->isExact()) {
776 /// instructions (udiv and sdiv). It is called by the visitors to those integer
798 bool IsSigned = I.getOpcode() == Instruction::SDiv;
875 bool isSigned = I.getOpcode() == Instruction::SDiv;
899 bool isSigned = I.getOpcode() == Instruction::SDiv;
[all...] |
| InstCombineVectorOps.cpp | 617 case Instruction::SDiv:
680 case Instruction::SDiv:
780 case Instruction::SDiv:
[all...] |
| /external/lldb/source/Expression/ |
| IRInterpreter.cpp | 514 case Instruction::SDiv:
620 case Instruction::SDiv:
681 case Instruction::SDiv:
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 403 case Instruction::SDiv:
|
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 203 case SDiv: return "sdiv";
|
| ConstantFold.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 90 case Instruction::SDiv:
296 if (ISD == ISD::SDIV &&
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 385 J->getOpcode() == Instruction::SDiv ||
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| ARCInstKind.cpp | 271 case Instruction::SDiv:
|
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 876 case Instruction::SDiv: Out << "getSDiv("; break;
[all...] |
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 765 case Instruction::SDiv:
783 case Instruction::SDiv:GV.IntVal = LHS.IntVal.sdiv(RHS.IntVal); break;
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 449 /// Keyword sdiv, float, ...
704 INSTKEYWORD(udiv, UDiv); INSTKEYWORD(sdiv, SDiv); INSTKEYWORD(fdiv, FDiv);
|
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 345 case 3:{Op = (isFloat?Instruction::FDiv : Instruction::SDiv); break; }
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 91 if (ISD == ISD::SDIV &&
114 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
116 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
161 { ISD::SDIV, MVT::v32i8, 32*20 },
162 { ISD::SDIV, MVT::v16i16, 16*20 },
163 { ISD::SDIV, MVT::v8i32, 8*20 },
164 { ISD::SDIV, MVT::v4i64, 4*20 },
209 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
211 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
218 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()
[all...] |
