| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 391 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
394 if (!isRegUsed(SReg)) {
395 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
396 return SReg;
412 Scavenged[SI].Reg = SReg;
416 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
420 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
428 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
439 // Scavenged[SI].Reg = SReg;
441 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 106 unsigned getDPRLaneFromSPR(unsigned SReg);
121 unsigned getPrefSPRLane(unsigned SReg);
150 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
151 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
159 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
160 if (!TRI->isVirtualRegister(SReg))
161 return getDPRLaneFromSPR(SReg);
163 MachineInstr *MI = MRI->getVRegDef(SReg);
165 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
172 SReg = MI->getOperand(1).getReg()
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| VirtRegMap.h | 137 /// @brief records virtReg is a split live interval from SReg.
138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
139 Virt2SplitMap[virtReg] = SReg;
|
| /art/compiler/dex/quick/ |
| ralloc_util.cc | 150 info->IsDirty(), info->SReg(), info->DefStart() != nullptr);
226 if (info->SReg() == s_reg) {
350 if (info->SReg() != INVALID_SREG) {
374 ClobberSReg(info->SReg());
463 if ((info->SReg() == s_reg) && info->IsLive()) {
652 DCHECK_EQ(info->SReg(), s_reg); // Make sure we're on the same page.
741 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) {
744 int v_reg = mir_graph_->SRegToVReg(info1->SReg());
752 int v_reg = mir_graph_->SRegToVReg(info->SReg());
[all...] |
| mir_to_lir-inl.h | 31 if (p->SReg() != INVALID_SREG) {
|
| mir_to_lir.h | 206 // Mask to denote sreg as the start of a 64-bit item. Must not interfere with low 16 bits.
292 * reused as live, it must both be marked live and the associated SReg() must match the
348 if (SReg() != INVALID_SREG) {
370 int SReg() { return (!IsTemp() || IsLive()) ? s_reg_ : INVALID_SREG; }
[all...] |
| codegen_util.cc | 1374 int32_t sreg = first_vreg_to_ssa_map[vreg]; local
[all...] |
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| MemRegion.h | 419 SubRegion(const MemRegion* sReg, Kind k) : MemRegion(k), superRegion(sReg) {}
480 TypedRegion(const MemRegion* sReg, Kind k) : SubRegion(sReg, k) {}
502 TypedValueRegion(const MemRegion* sReg, Kind k) : TypedRegion(sReg, k) {}
534 CodeTextRegion(const MemRegion *sreg, Kind k) : TypedRegion(sreg, k) {}
548 FunctionTextRegion(const NamedDecl *fd, const MemRegion* sreg)
549 : CodeTextRegion(sreg, FunctionTextRegionKind), FD(fd)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 831 SReg = MF.getRegInfo().createVirtualRegister(RC);
836 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| MemRegion.cpp | 229 ObjCIvarRegion::ObjCIvarRegion(const ObjCIvarDecl *ivd, const MemRegion* sReg)
230 : DeclRegion(ivd, sReg, ObjCIvarRegionKind) {}
337 const MemRegion *sreg) {
340 ID.AddPointer(sreg);
387 const MemRegion *sReg) {
392 ID.AddPointer(sReg);
401 const MemRegion *sReg) {
403 ID.AddPointer(sReg);
413 const MemRegion *SReg) {
416 ID.AddPointer(SReg);
[all...] |
