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    Searched refs:SRegToVReg (Results 1 - 15 of 15) sorted by null

  /art/compiler/dex/
vreg_analysis.cc 72 reg_location_[i].s_reg_low = SRegToVReg(orig_sreg);
gvn_dead_code_elimination.cc 382 if (mir_graph->SRegToVReg(ssa_rep->uses[i]) == v_reg) {
522 int v_reg = mir_graph_->SRegToVReg(s_reg);
566 DCHECK_EQ(mir_graph_->SRegToVReg(new_s_reg) + 1, mir_graph_->SRegToVReg(new_s_reg + 1));
591 DCHECK_EQ(mir_graph_->SRegToVReg(old_s_reg), mir_graph_->SRegToVReg(new_s_reg));
630 int v_reg = mir_graph_->SRegToVReg(data->mir->ssa_rep->uses[i]);
677 old_s_reg, mir_graph_->SRegToVReg(old_s_reg),
678 new_s_reg, mir_graph_->SRegToVReg(new_s_reg));
690 uint32_t src_v_reg = mir_graph_->SRegToVReg(src_s_reg)
    [all...]
mir_graph.cc     [all...]
mir_optimization.cc 700 int def_vreg = SRegToVReg(mir->ssa_rep->defs[0]);
    [all...]
gvn_dead_code_elimination_test.cc 238 int SRegToVReg(int32_t s_reg, bool wide) {
239 int v_reg = cu_.mir_graph->SRegToVReg(s_reg);
247 int SRegToVReg(int32_t* uses, size_t* use, bool wide) {
248 int v_reg = SRegToVReg(uses[*use], wide);
300 mir->dalvikInsn.vA = SRegToVReg(def->defs[0], (df_attrs & DF_A_WIDE) != 0);
310 mir->dalvikInsn.vA = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_A_WIDE) != 0);
313 mir->dalvikInsn.vB = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_B_WIDE) != 0);
316 mir->dalvikInsn.vC = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_C_WIDE) != 0);
    [all...]
type_inference.cc 213 int v_reg = mir_graph_->SRegToVReg(s_reg);
337 int v_reg = mir_graph_->SRegToVReg(s_reg);
374 DCHECK_EQ(v_reg, mir_graph_->SRegToVReg(s_reg));
    [all...]
ssa_transformation.cc 513 int v_reg = SRegToVReg(ssa_reg);
mir_graph.h     [all...]
local_value_numbering.cc 531 bool live = live_in_v->IsBitSet(gvn_->GetMirGraph()->SRegToVReg(entry.first));
554 bool live_and_same = live_in_v->IsBitSet(gvn_->GetMirGraph()->SRegToVReg(entry.first));
    [all...]
  /art/compiler/dex/quick/
gen_loadstore.cc 268 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1),
269 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low)));
332 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1),
333 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low)));
ralloc_util.cc 253 int v_reg = mir_graph_->SRegToVReg(s_reg);
260 int v_reg = mir_graph_->SRegToVReg(s_reg);
293 int v_reg = mir_graph_->SRegToVReg(s_reg);
741 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) {
744 int v_reg = mir_graph_->SRegToVReg(info1->SReg());
752 int v_reg = mir_graph_->SRegToVReg(info->SReg());
764 int v_reg = mir_graph_->SRegToVReg(info->SReg());
    [all...]
codegen_util.cc     [all...]
  /art/compiler/dex/quick/x86/
fp_x86.cc 632 int v_src_reg = mir_graph_->SRegToVReg(rl_src.s_reg_low);
633 int v_dst_reg = mir_graph_->SRegToVReg(rl_dest.s_reg_low);
683 int v_src_reg = mir_graph_->SRegToVReg(rl_src.s_reg_low);
684 int v_dst_reg = mir_graph_->SRegToVReg(rl_dest.s_reg_low);
int_x86.cc 907 if (mir_graph_->SRegToVReg(rl_src1.s_reg_low) ==
908 mir_graph_->SRegToVReg(rl_src2.s_reg_low)) {
    [all...]
  /art/compiler/dex/quick/arm/
target_arm.cc 841 int v_reg = mir_graph_->SRegToVReg(s_reg);
894 int v_reg = mir_graph_->SRegToVReg(s_reg);
    [all...]

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