| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 107 COMPARE(and_(r2, r3, Operand(r4), SetCC),
114 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
118 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
123 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
134 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
143 COMPARE(add(r7, r8, Operand(ip), SetCC),
145 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
152 COMPARE(adc(r5, sp, Operand(ip), SetCC),
154 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| test-assembler-arm.cc | 951 __ mov(r1, Operand(r1, ASR, 1), SetCC);
956 __ mov(r2, Operand(r2, ASR, 1), SetCC);
963 __ mov(r3, Operand(r1, ASR, 1), SetCC); // Set the carry.
969 __ mov(r3, Operand(r2, ASR, 1), SetCC); // Unset the carry.
[all...] |
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | 34 return SetCC;
260 DCHECK_EQ(SetCC, i.OutputSBit());
264 DCHECK_EQ(SetCC, i.OutputSBit());
268 DCHECK_EQ(SetCC, i.OutputSBit());
272 DCHECK_EQ(SetCC, i.OutputSBit());
277 DCHECK_EQ(SetCC, i.OutputSBit());
|
| /external/v8/src/arm/ |
| codegen-arm.cc | 139 __ sub(chars, chars, Operand(64), SetCC);
198 __ bic(temp1, chars, Operand(0x3), SetCC);
206 __ bic(temp2, chars, Operand(0x3), SetCC);
218 __ mov(chars, Operand(chars, LSL, 31), SetCC);
301 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs
|
| code-stubs-arm.cc | 193 __ rsb(scratch, scratch, Operand(51), SetCC);
370 __ orr(r0, r3, Operand(r2), SetCC);
[all...] |
| constants-arm.h | 215 SetCC = 1 << 20, // Set condition code.
|
| regexp-macro-assembler-arm.cc | 231 __ sub(r1, r1, r0, SetCC); // Length of capture.
342 __ sub(r1, r1, r0, SetCC); // Length to check.
618 __ sub(r0, sp, r0, SetCC);
681 __ sub(r2, r2, Operand(1), SetCC);
[all...] |
| lithium-codegen-arm.cc | 873 __ sub(r1, r1, Operand(1), SetCC);
[all...] |
| macro-assembler-arm.cc | [all...] |
| full-codegen-arm.cc | 179 __ sub(r2, r2, Operand(1), SetCC);
345 __ sub(r3, r3, Operand(Smi::FromInt(delta)), SetCC);
[all...] |
| builtins-arm.cc | 496 __ sub(r3, r3, Operand(r6), SetCC);
645 __ sub(r3, r3, Operand(2), SetCC);
[all...] |
| macro-assembler-arm.h | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 208 // setcc operations results (slt, sgt, ...).
243 // Used by legalize types to correctly generate the setcc result.
244 // Without this, every float setcc comes with a AND/OR with the result,
247 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
261 setOperationAction(ISD::SETCC, MVT::f32, Custom);
262 setOperationAction(ISD::SETCC, MVT::f64, Custom);
527 // Creates and returns an FPCmp node from a setcc node.
528 // Returns Op if setcc is not a floating point comparison.
530 // must be a SETCC node
531 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
285 setOperationAction(ISD::SETCC, Ty, Legal);
322 setOperationAction(ISD::SETCC, Ty, Legal);
[all...] |
| /external/v8/src/ia32/ |
| disasm-ia32.cc | 338 int SetCC(byte* data);
662 int DisassemblerIA32::SetCC(byte* data) {
1100 data += SetCC(data);
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | 413 int SetCC(byte* data);
807 int DisassemblerX64::SetCC(byte* data) {
[all...] |
| /external/v8/src/x87/ |
| disasm-x87.cc | 338 int SetCC(byte* data);
662 int DisassemblerX87::SetCC(byte* data) {
1121 data += SetCC(data);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 102 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
103 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
215 setTargetDAGCombine(ISD::SETCC);
747 if (Intr->getOpcode() == ISD::SETCC) {
749 SDNode *SetCC = Intr;
750 assert(SetCC->getConstantOperandVal(1) == 1);
751 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
753 Intr = SetCC->getOperand(0).getNode();
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
720 setOperationAction(ISD::SETCC, VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 654 // Return true if this node is a setcc, or is a select_cc
656 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
661 if (N.getOpcode() == ISD::SETCC) {
683 /// Return true if this is a SetCC-equivalent operation with only one use.
[all...] |
| LegalizeIntegerTypes.cpp | 73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
550 // Promote all the way up to the canonical SetCC type.
591 // Get the SETCC result using the canonical SETCC type.
592 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
597 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| LegalizeDAG.cpp | 51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| /external/v8/src/ic/arm/ |
| ic-arm.cc | 544 __ sub(r5, r5, r6, SetCC);
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
285 setOperationAction(ISD::SETCC, MVT::f16, Promote);
353 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
386 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
540 setOperationAction(ISD::SETCC, MVT::v1f64, Expand)
[all...] |
