| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 607 unsigned ShAmt = SA->getZExtValue();
611 if (ShAmt >= BitWidth)
614 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
619 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
622 int Diff = ShAmt-C1;
636 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
646 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
649 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
653 TLO.DAG.getConstant(ShAmt, ShTy))
[all...] |
| LegalizeVectorOps.cpp | 554 SDValue Lo, Hi, ShAmt;
557 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
558 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
567 ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
569 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
586 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
588 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
589 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 380 Constant *ShAmt = ConstantExpr::getZExt(COp1, TrOp->getType());
382 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
708 unsigned ShAmt = Op1C->getZExtValue();
713 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt),
721 ComputeNumSignBits(I.getOperand(0), 0, &I) > ShAmt) {
751 unsigned ShAmt = Op1C->getZExtValue();
761 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
771 MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt),
795 unsigned ShAmt = Op1C->getZExtValue();
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineMulDivRem.cpp | [all...] |
| InstCombineAndOrXor.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| SROA.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
457 unsigned ShAmt) {
464 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
582 unsigned ShAmt = Log2_32(RHSC);
584 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
610 unsigned ShAmt = 0;
620 ShAmt = Sh->getZExtValue();
621 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
624 ShAmt = 0
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | 270 unsigned ShAmt = Amt->getZExtValue();
272 if ((ShAmt & 7) != 0)
274 ShAmt >>= 3;
277 if (ByteStart >= CSize-ShAmt)
281 if (ByteStart+ByteSize+ShAmt <= CSize)
282 return ExtractConstantBytes(CE->getOperand(0), ByteStart+ShAmt, ByteSize);
292 unsigned ShAmt = Amt->getZExtValue();
294 if ((ShAmt & 7) != 0)
296 ShAmt >>= 3;
299 if (ByteStart+ByteSize <= ShAmt)
[all...] |
| /external/clang/lib/Lex/ |
| PPExpressions.cpp | 613 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
614 if (ShAmt >= LHS.getBitWidth())
615 Overflow = true, ShAmt = LHS.getBitWidth()-1;
616 Res = LHS.Val >> ShAmt;
|
| /external/llvm/lib/Support/ |
| APInt.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | [all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | [all...] |
